CN110764447A

CN110764447A - FPGA-based multi-path extensible sampling system and method

Info

Publication number: CN110764447A
Application number: CN201911021036.7A
Authority: CN
Inventors: 张新雷; 周宇; 王环; 窦德刚
Original assignee: Institute of Electrical Engineering of CAS
Current assignee: Institute of Electrical Engineering of CAS
Priority date: 2019-10-25
Filing date: 2019-10-25
Publication date: 2020-02-07

Abstract

The invention relates to a multi-path extensible sampling system and a multi-path extensible sampling method based on an FPGA (field programmable gate array), wherein the multi-path extensible sampling system comprises an FPGA and at least one ADC (analog to digital converter) chip; the ADC conversion chip comprises: the device comprises a conversion starting control pin, a conversion finishing zone bit output pin, a multi-channel analog signal input pin, a data reading control pin and a parallel data output bus; the connection mode of the FPGA and the ADC chip is as follows: parallel data output buses of the ADC chip are collected into a group of buses and then are accessed into the FPGA, a conversion starting control pin and a data reading control pin are respectively collected and then are accessed into the FPGA, and a flag bit output pin and an ADC chip selection pin which are subjected to conversion are respectively accessed into the FPGA without collection processing; the FPGA controls the ADC chip to sample through a Finite State Machine (FSM) according to a control time sequence provided in the ADC chip number manual, and the sampling data is stored in a double-port RAM opened in the FPGA.

Description

FPGA-based multi-path extensible sampling system and method

Technical Field

The invention relates to the field of power electronic digital control, in particular to an electric multi-path extensible sampling system and method based on an FPGA (field programmable gate array).

Background

In a digital control system of power electronics, a voltage and current signal of equipment firstly passes through a conditioning circuit to obtain a voltage range which can be received by an analog/digital conversion chip (ADC chip), a corresponding digital signal is obtained after the conversion of the ADC chip, and finally, the operation and the output of a controller are realized. When one controller is adopted to realize centralized control of a plurality of devices, or control variables are too much, a single ADC chip is difficult to meet the sampling requirement.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The technical problem of the invention is solved: the defects of the prior art are overcome, the multi-path extensible sampling system and the multi-path extensible sampling method based on the FPGA are provided, the extension of the sampling system can be conveniently and rapidly realized, and the hardware can be adapted to the change with small change.

The technical scheme of the invention is as follows: a multi-path expandable sampling system and a method based on FPGA,

in a first aspect, a hardware architecture based on an FPGA and an ADC chip:

the system disclosed by the invention comprises an ADC chip and an FPGA which can simultaneously convert multi-path analog input into digital quantity. Wherein the ADC conversion chip generally comprises: the device comprises a conversion starting control pin, a conversion finishing zone bit output pin, a multi-channel analog signal input pin, an ADC chip selection pin, a data reading control pin and a parallel data output bus, wherein the device can also comprise an additional configuration pin according to different types of ADC chips, and the parallel data output bus can be 12bit, 14bit, 16bit and the like according to the precision of the ADC chips. The system may include 1 to N (N >1) ADC chips, the specific number of ADC chips depends on the number of analog samples and ADC chip signals. The connection mode of the FPGA and the ADC chip is as follows: parallel data output buses of the ADC chip are collected into a group of buses and then are accessed into the FPGA, a conversion start control pin and a data reading control pin are respectively collected and then are accessed into the FPGA, a conversion completion zone bit output pin and an ADC chip selection pin are respectively accessed into the FPGA without collection processing, and in addition, according to the type of the ADC chip, the ADC chip selection pin can also comprise some extra configuration pins which are respectively accessed into the FPGA after being respectively collected according to functions

In a second aspect, the FPGA controls the sampling and sampling data access mode of the ADC chip:

according to the control time sequence of the ADC chip, the sampling start and data reading of the ADC chip are controlled through a Finite State Machine (FSM), a double-port RAM is opened up inside the FPGA, a data bus of the RAM receives digital quantity converted by the ADC chip, a counter is driven by a sampling reading signal, a count value is mapped to an RAM address, a data reading control signal sent to the ADC chip by the FPGA is used as write-in enabling of the RAM, and data converted by the ADC chip is stored in the RAM.

Compared with the prior art, the invention has the advantages that:

(1) the invention provides a method for realizing a complete set of FPGA-based multi-path extensible sampling system from hardware design to software, and the extension of the sampling system can be conveniently and rapidly realized according to the hardware connection mode and the FPGA internal architecture.

(2) The invention solves the problem of controlling the simultaneous sampling of ultra-multipath AD, and provides a method for realizing a complete set of FPGA-based multipath extensible sampling system from hardware design to software.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

FIG. 1 illustrates a hardware connection diagram in accordance with an exemplary embodiment of the present disclosure;

FIG. 2 illustrates an FPGA implementation according to an exemplary embodiment of the present disclosure.

Detailed Description

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

In the exemplary embodiment of the invention, a Cyclone3 series FPGA chip from Intel corporation is adopted, and an AD7656 chip from ADI corporation is used as an ADC chip. The ADC chip is configured in parallel mode by peripheral circuitry. The system comprises an FPGA chip S101, 3 AD7656 chips ADC 1S 102, ADC 2S 103 and ADC 3S 104. Referring to fig. 1, AD7656 chip ADC 1S 102, ADC 2S 103, and ADC 3S 104 have 16-bit parallel DATA output buses, bus bits with numbers from high to low are DB 15-DB 0, bus bits with corresponding numbers of 3-chip ADC chips are collected and then accessed to FPGA as collected bus AD _ DATA S105 in fig. 1, chip select lines AD _ CS1S 106, AD _ CS 2S 107, and AD _ CS 3S 108 of the 3-chip ADC are respectively accessed to FPGA, as shown in fig. 1, flag bit output pins AD1_ busy S109, AD2_ busy S110, and AD3_ busy S111 of the 3-chip ADC are respectively accessed to FPGA S101, AD _ RD S112 is accessed to FPGA S101 after ADC DATA reading control pins are collected, and AD _ convs 113 is counted to FPGA S101 after ADC conversion start control pins are collected.

The embodiment of the invention also comprises an implementation mode of FPGA S101 control. Referring to fig. 2, where IN fig. 2 is a system input port and OUT is a system output, the implementation of the FPGA S101 IN the exemplary embodiment of the present invention specifically includes 3 main portions: a finite state machine FSM S201, an address encoder S202 and a dual-port RAM S203. The FSM S201 is written according to the timing sequence of the ADC chip ADC 1S 102, ADC 2S 103, and ADC 3S 104 manual, and is responsible for controlling the start of ADC sampling, receiving the conversion completion signals AD1_ busy S215, AD1_ busy S216, AD1_ busy S217 of the ADC chip and outputting a read signal AD _ RD S205, and reading the sampling data of the three ADC chips ADC 1S 102, ADC 2S 103, and ADC 3S 104 by chip selection output AD _ CS1S206, AD _ CS 2S 207, and AD _ CS 3S 208; the principle of the address encoder S202 is: when receiving the AD conversion enable signal AD _ CONVSTx S204, the internal ADDRESS offset counter is cleared, the ADDRESS offset +1 is controlled by the rising edge of the AD _ RD signal S205, the current ADDRESS offset is mapped to an ADDRESS of the dual port RAM S203, the read DATA AD _ DATA S211 is written to the corresponding ADDRESS by the read signal AD _ RD S205 through the write port ADDRESS bus W _ ADDRESS S212 and the write port DATA bus DATA _ IN S213 of the dual port RAM S203 using the AD _ RD S205 as the write enable of the dual port RAM S203, and the read port of the dual port RAM S203 includes the read enable RDEN S209, the read port ADDRESS bus R _ ADDRESS S210, and the read port ADDRESS bus DATA _ OUT S214. In the present exemplary embodiment, the dual-port RAMS203 is generated by setting parameters using a tool in the Quartus II software, and determines the depth of the RAM according to the amount of data to be stored, thereby determining the number of bits of the address line used by the RAM S203. In this embodiment, since 18 pieces of data are required to be stored, the address width is 5 bits.

In the exemplary embodiment, the reason why the write port of the RAM S203 drives the clock clk S217 and the read clock rd _ clkS218, and the write clock and the read clock are configured separately is that the write port and the read port of the dual-port RAM S203 can operate at different frequencies, thereby increasing the versatility of the whole sampling system.

The number of ADC chips in the system is expanded by using the same connection mode, and the expansion of the sampling system can be realized by simply modifying the internal implementation mode of the FPGA, so that the requirement of the system on multi-path sampling is met.

Claims

1. A multi-path extensible sampling system based on FPGA is characterized by comprising: a FPGA and at least one ADC chip; each ADC conversion chip comprises: the device comprises a conversion starting control pin, a conversion finishing zone bit output pin, a multi-channel analog signal input pin, an ADC chip selection pin, a data reading control pin and a parallel data output bus; the connection mode of the FPGA and the ADC chip is as follows: parallel data output buses of the ADC chip are collected into a group of buses and then are accessed into the FPGA, and a conversion starting control pin and a data reading control pin are respectively collected and then are accessed into the FPGA; the conversion completion flag bit output pin and the ADC chip selection pin of each ADC chip are respectively connected to the FPGA without collecting; and the FPGA controls the ADC chip to sample and sample data to be accessed.

2. The FPGA-based multi-way scalable sampling system of claim 1, wherein: the FPGA comprises a state machine (FSM), an address encoder and a double-port RAM (random access memory) which are compiled according to the time sequence of an ADC (analog to digital converter) chip, the FPGA controls the ADC chip to sample and sample data to be accessed, and the specific mode is as follows: according to a control time sequence provided in a data manual of an ADC chip, a Finite State Machine (FSM) is used for controlling the starting of sampling and data reading of the ADC chip, a double-port RAM is opened up in an FPGA, a data bus of the RAM receives digital quantity converted by the ADC chip, a counter is driven by using a sampling reading signal, a count value is mapped to a double-port RAM address, a data reading control signal sent to the ADC chip by the FPGA is used as the write-in enabling of the double-port RAM, and data converted by the ADC chip is stored in the double-port RAM by using an address generated by an address encoder; and accessing the dual-port RAM to obtain the sampling data stored in different addresses.

3. The FPGA-based multi-way scalable sampling system of claim 1, wherein: the ADC chip can also comprise some additional configuration pins according to different models, and the configuration pins are respectively collected according to functions and then are respectively connected to the FPGA; meanwhile, the data buses are parallelly output to be 12 bits, 14 bits and 16 bits according to the precision of the ADC chip.

4. The FPGA-based multi-way scalable sampling system of claim 1, wherein: the ADC chip comprises 1 to N pieces, wherein N is more than 1; the number of ADC chips is expanded at will according to needs, and a large amount of IO (input/output) resources of the FPGA cannot be occupied due to expansion of the parallel bus.

5. A multi-path extensible sampling method based on FPGA is characterized in that: the FPGA controls the ADC chip to sample and sample data to be accessed, and the process is as follows: according to a control time sequence provided in a data manual of an ADC chip, a Finite State Machine (FSM) is used for controlling the starting and data reading of sampling of the ADC chip, a double-port RAM is opened up inside an FPGA, a data bus of the RAM receives data converted by the ADC chip, a counter is driven by a sampling reading signal, a count value is mapped to an address of the double-port RAM, the sampling reading signal is used as a write-in enable of the double-port RAM, and the data converted by the ADC chip is stored in the double-port RAM; and accessing the dual-port RAM to obtain the sampling data stored in different addresses.