CN215600374U - Semiconductor device with a plurality of semiconductor chips - Google Patents

Abstract

The present disclosure discloses a semiconductor device. The semiconductor device includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed within the substrate and includes a plurality of first active segments, a plurality of second active segments, and a plurality of third active segments, wherein the first active segments, the second active segments, and the third active segments extend in parallel to each other, spaced apart from each other, toward the first direction. According to the semiconductor device disclosed by the present disclosure, the structure around the first active segment (i.e., the structure of the second active region) can be stabilized and strengthened by providing different extension lengths through the second active segment and the third active segment, so as to improve the stress around the semiconductor device and avoid the problems of collapse or crack of the surrounding structure.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

The present disclosure relates generally to semiconductor devices, and more particularly to a semiconductor device including an active structure and a shallow trench isolation.

Background

As semiconductor devices are miniaturized and integrated circuits are complicated, device sizes are continuously reduced and structures are continuously changed, so that maintaining the performance of small-sized semiconductor devices is a major goal in the industry. In a semiconductor fabrication process, a plurality of active regions are defined on a substrate as a basis, and then required components are formed on the active regions. Generally, the active regions are formed by photolithography and etching processes to form a plurality of patterns on the substrate, but the width of the active regions is gradually reduced and the distance between the active regions is also gradually reduced under the requirement of size reduction, so that the manufacturing process thereof also faces many limitations and challenges, and thus cannot meet the product requirements.

SUMMERY OF THE UTILITY MODEL

It is an object of the present disclosure to provide a semiconductor device having an active structure with a plurality of active segments of different lengths, wherein the active segments can be directly connected to the peripheral active region. Therefore, the stress around the semiconductor device can be improved, the collapse or damage of the semiconductor structure can be avoided, and the semiconductor device can achieve optimized element efficiency.

To achieve the above objective, one embodiment of the present disclosure provides a semiconductor device including a substrate, an active structure, and a shallow trench isolation. The active structure is disposed within the substrate, and includes a plurality of first active segments and a plurality of second active segments, the first active segments and the second active segments extending in a first direction parallel to each other and spaced apart from each other. A plurality of first openings are disposed in the substrate and between any two adjacent first active segments. A plurality of second openings are disposed in the substrate and between adjacent second active segments, wherein a maximum aperture of the second openings is larger than a maximum aperture of the first openings. The shallow trench isolation is arranged in the substrate and filled into the first opening and the second opening so as to surround the active structure.

Drawings

Fig. 1 to 2 are schematic views illustrating a semiconductor device according to a first preferred embodiment of the present disclosure; wherein

FIG. 1 is a schematic top view of an active structure of a semiconductor device according to the present disclosure; and

fig. 2 is a schematic cross-sectional view taken along line a-a' of fig. 1.

FIGS. 3-5 illustrate a method of forming a semiconductor device according to a preferred embodiment of the present disclosure; wherein

FIG. 3 is a top view of a semiconductor structure with shallow trenches and active area cells;

FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 3; and

fig. 5 is a top view of a semiconductor structure with a first opening and a second opening formed therein.

FIG. 6 is a schematic diagram of a semiconductor device according to a second preferred embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a semiconductor device according to a third preferred embodiment of the present disclosure.

Wherein the reference numerals are as follows:

100. 300, 500 semiconductor memory device

110 substrate

120 shallow trench isolation

121 shallow trench

122 first isolation region

124 second isolation region

130 first active region

130a active area cell

131 first active segment

132 first opening

133 second active segment

133a side edge

134 second opening

135 third active segment

140. 340, 540 second active region

141. 341, 541 first side edge

143. 343, 543 second side edge

150 active structure

341a, 343a fragment

342. 344 opening

541a, 543a fragment

542. 544 opening

D1 first direction

D2 second direction

Third direction D3

L1, L2 maximum width

Maximum pore diameters of O1 and O2

Length of S1, S2, S3

Detailed Description

To further clarify the disclosure and its intended advantages, those skilled in the art will recognize that there is no intent to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims. Those of skill in the art to which the present disclosure pertains will be readily able to devise alternative embodiments, arrangements and mixtures of features which, without departing from the spirit of the present disclosure, are capable of being substituted and reconfigured for additional embodiments.

Referring to fig. 1 to 2, a schematic diagram of a semiconductor device 100 according to a first preferred embodiment of the present disclosure is shown, in which fig. 1 is a top view of the semiconductor device 100, and fig. 2 is a cross-sectional diagram of the semiconductor device 100. The semiconductor device 100 includes a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe) or a silicon-on-insulator (SOI) substrate, and at least one Shallow Trench Isolation (STI) 120 is disposed in the substrate 110 to define an active structure 150 on the substrate 110, i.e., the STI 120 is disposed around the active structure 150. The active structure 150 further includes a first active region 130 and a second active region 140, wherein the second active region 140 preferably surrounds the outside of the first active region 130. In one embodiment, the first active region 130 is disposed in a region with a relatively high device integration level, such as an active region, a memory region, etc., of the semiconductor device 100, and the second active region 140 is disposed in a region with a relatively low device integration level, such as a peripheral region, of the semiconductor device 100, but not limited thereto.

As shown in fig. 1 and fig. 2, the detailed portion of the first active region 130 includes a plurality of first active segments 131, a plurality of second active segments 133, and a plurality of third active segments 135, which extend parallel to each other along a same direction (e.g., the first direction D1), wherein the first direction D1 is not perpendicular to the x direction (e.g., the second direction D2) or the y direction (e.g., the third direction D3). In detail, the first active segment 131, the second active segment 133 and the third active segment 135 are spaced apart from each other and are sequentially arranged in a plurality of columns along the first direction D1, and the whole may be in a specific arrangement, such as an array arrangement (array arrangement) shown in fig. 1, but not limited thereto. It is noted that the STI 120 includes a plurality of first isolation regions 122 and a plurality of second isolation regions 124, two adjacent first active segments 131 are separated by the first isolation regions 122, and each first active segment 131 has a same length S1 in the first direction D1. Also, the third active segments 135 are disposed on two opposite sides (upper side and lower side as shown in fig. 1) of all the first active segments 131 in the third direction D3 and directly contact the second active regions 140, the adjacent first active segments 131 and third active segments 135 are also separated by the first isolation region 122, and each of the third active segments 135 has a different length (e.g., lengths S2, S3, etc.) in the first direction D1 and is not equal to the length S1 of the first active segment 131. In addition, the second active segments 133 are disposed on two opposite sides of all of the first active segments 131 and the third active segments 135 in the second direction D2 and partially contact the second active regions 140, adjacent second active segments 133 are separated by the second isolation region 124, and have a length (not shown) less than that of the first active segment 131 (length S1) in the first direction D1, respectively. The maximum width L2 of the second isolation region 124 in the second direction D2 is greater than the maximum width L1 of the first isolation region 122, so that the second active segments 133 adjacent to each other in the second direction D2 may have mutually aligned sides 133a, as shown in fig. 1.

In another aspect, the second isolation regions 124 are disposed on two opposite sides (left side and right side as shown in fig. 1) of all the first isolation regions 122 along the second direction D2, and the second isolation regions 124 and the first isolation regions 122 are sequentially arranged in a plurality of columns along the third direction D3, the second isolation regions 124 or the first isolation regions 122 in each column are opposite to each other, and the second isolation regions 124 or the first isolation regions 122 in adjacent columns are staggered from each other along the second direction D2, so that the second isolation regions 124 and the first isolation regions 122 may also be integrally arranged in an array, but are not limited thereto.

The second active region 140 includes at least one first side 141 extending along the second direction D2 and at least one second side 143 extending along the third direction D3, such that the second active region 140 may be a rectangular frame directly contacting the third active segment 135 and a portion of the second active segment 133. That is, all of the third active segments 135 may be further connected to the first side 141 of the second active region 140, and a portion of the second active segment 133 may be selectively connected to the first side 141, the second side 143, or both the first side 141 and the second side 143 of the second active region 140, so that another portion of the second active segment 133 may not be connected to the first side 141 and/or the second side 143 of the second active region 140, as shown in fig. 1. With this arrangement, the second active region 140 can more uniformly bear the stress influence from the first active region 130 and the shallow trench isolation 120, so as to obtain a more stable structure. It should be understood by those skilled in the art that the specific number of the first sides or the second sides can be adjusted according to actual requirements, or other sides can be further included, so that the second active region can take other shapes as a whole, not limited to the rectangular frame shape.

Thus, in the semiconductor device 100 according to the first preferred embodiment of the present disclosure, the second active segment 133 and the third active segment 135 with different lengths are respectively disposed on the left side, the right side, the upper side and the lower side of the first active segment 131, such that a portion of the second active segment 133 is further connected to at least one side (including the first side 141, the second side 143, or the first side 141 and the second side 143) of the second active region 140, and the third active segment 135 is further connected to the first side 141 of the second active region 140. In this way, the structures around the first active segment 131 (i.e., the structures of the second active region 140) can be stabilized and strengthened by providing different extension lengths through the second active segment 133 and the third active segment 135, so as to improve the stress around the semiconductor device 100 and avoid the problems of collapse or crack of the surrounding structures. Subsequently, the semiconductor device 100 may be used to form other semiconductor active devices, such as memory devices or transistor devices, to further enhance the performance of the subsequently formed devices.

To enable one of ordinary skill in the art to practice the present disclosure, a method of forming the semiconductor device 100 of the present disclosure is further described below. Referring to fig. 3 to 5, a patterning process of the semiconductor device 100 according to a preferred embodiment of the present disclosure is illustrated, wherein the active structure 150 is formed by, but not limited to, the patterning process described below. First, a mask layer (not shown) is formed on the substrate 110, the mask layer includes a pattern for defining a plurality of active area units 130a and exposes a portion of the substrate 110, an etching process is performed using the mask layer to remove the portion of the substrate 110 to form at least one shallow trench (shallow trench)121, and active area units 130a extending along a first direction D1 and parallel to each other are defined on the substrate 110, as shown in fig. 3 and 4. Then, referring to fig. 5, another mask layer (not shown) is formed on the substrate 110, where the another mask layer includes a pattern that can be used to define the first opening 132 and the second opening 134 and exposes a portion of the active area unit 130a, another etching process is performed using the another mask layer to remove the portion of the active area unit 130a to form the first opening 132 and the second opening 134 (shown by a dashed rectangle in fig. 5), and the active area unit 130a is simultaneously cut off to form the first active segment 131, the second active segment 133, and the third active segment 135. In detail, the aperture O2 of the second opening 134 in the second direction D2 is larger than the aperture O1 of the first opening 132 in the second direction D2, and the second openings 134 are disposed on two opposite sides (left side and right side as shown in fig. 5) of all the first openings 132 in the second direction D2, meanwhile, the second openings 134 and the first openings 132 are sequentially arranged in a plurality of columns along the third direction D3, the second openings 134 or the first openings 132 in each column are opposite to each other, and the second openings 134 or the first openings 132 in adjacent columns are offset from each other in the second direction D2, so that the second openings 134 and the first openings 132 can also be arranged in an array as a whole, but not limited thereto. Then, an insulating material (not shown), such as silicon oxide, silicon nitride or silicon oxynitride, is filled into the shallow trench 121, the first opening 132 and the second opening 134, so as to form the shallow trench isolation 120 (including the first isolation region 122 and the second isolation region 124) having a top surface aligned with the surface of the substrate 110.

After forming the first active region 130, the formation of the second active region 140 may continue on the substrate 110. In the present embodiment, the second active region 140 may be formed by a patterning process of the substrate 110, and may be optionally performed together with the patterning process of the first active region 130. That is, as shown in fig. 3, the patterns of the first active region 130 and the second active region 140 may be simultaneously or separately defined by using the same or different mask layers (not shown), and the substrate 110 is etched and filled with the insulating material. Herein, the first active region 130 and the second active region 140 may include the same material (i.e., the material of the substrate 110), and the first side 141 and the second side 143 of the second active region 140, and the third active segment 135 and the second active segment 133 connected thereto may be integrally formed, as shown in fig. 5. In this case, the second active region 140 may have a relatively stable and strengthened structure, which may effectively protect the first active region 130 disposed inside thereof from structural collapse or damage. However, it should be understood by those skilled in the art that the formation of the second active region is not limited to the above method, and may be formed by other methods, for example, separately from the manufacturing process of the first active region. For example, in another embodiment, the manufacturing process of the second active region may be performed before the manufacturing process of the first active region, the second active region is formed by a patterning manufacturing process of the substrate, and the first active region is formed by an epitaxial growth process (not shown), where top surfaces of the second active region and the first active region may not be coplanar (not shown); alternatively, in another embodiment, the manufacturing process of the second active region may be performed after the manufacturing process of the first active region, the first active region is formed by a patterning process of the substrate, and then the second active region is formed by a deposition process (for example, a material different from the substrate, such as polysilicon, a dielectric material, etc.), where the second active region and the first active region may comprise different materials.

It should be readily apparent to those skilled in the art that the semiconductor device and the method of forming the same disclosed herein may have other aspects or may be implemented by other means without being limited to the foregoing embodiments in order to meet the actual product requirements. For example, in an embodiment, the corner portions may be rounded by adjusting the etching conditions during the patterning process of the first active region 130 and/or the second active region 140, but not limited thereto. Further description will be made below with respect to other embodiments or variations of the semiconductor device. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present disclosure are denoted by the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 6, a schematic diagram of a semiconductor device 300 according to a second preferred embodiment of the utility model is shown. The semiconductor device 300 of the present embodiment is substantially the same as the semiconductor device 100 of the first preferred embodiment, and also includes a substrate 110; an active structure 150 (e.g., including a first active region 130 and a second active region 340); and the shallow trench isolation 120 (including the first isolation region 122 and the second isolation region 124), the same parts will not be described again. The main difference between the present embodiment and the previous embodiments is that a plurality of openings 342 and 344 are additionally formed on the substrate 110, and the first side 341 and the second side 343 of the second active region 340 are respectively cut into a plurality of segments 341a and 343 a.

In detail, the segments 341a of the first side 341 are surrounded by the sti 120 and separated from each other, and the segments 341a directly contact two adjacent third active segments 135, two adjacent second active segments 133, or adjacent third active segments 135 and second active segments 133. When each segment 341a is connected to two third active segments 135 or to adjacent third active segments 135 and second active segments 133, the lengths of the two third active segments 135 or adjacent third active segments 135 and second active segments 133 in the first direction D1 are different from each other; however, when each segment 341a is connected to two second active segments 133, the lengths of the two second active segments 133 in the first direction D1 are the same as each other, as shown in fig. 6. On the other hand, each segment 343a of the second side 343 is also surrounded by the shallow trench isolation 120 and directly contacts at least one second active segment 133, preferably connects to two second active segments 133 adjacent to each other in the third direction D3.

Thus, the semiconductor device 300 according to the second preferred embodiment of the present disclosure can also stabilize and strengthen the structure of the second active region 340 by providing different extension lengths through the second active segment 133 and the third active segment 135, so as to improve the stress around the semiconductor device 300 and avoid the problems of collapse or crack of the surrounding structure. In addition, in the semiconductor device 300 of the present embodiment, the openings 342 and 344 are additionally disposed on the second active region 340, so that the stress borne by the sides (including the first side 341 and the second side 343) of the second active region 340 can be further dispersed, and the performance of the devices subsequently formed on the semiconductor device 300 can be further improved.

Referring to fig. 7, a semiconductor device 500 according to a third preferred embodiment of the present invention is shown. The semiconductor device 500 of the present embodiment is substantially the same as the semiconductor device 100 of the first preferred embodiment, and also includes a substrate 110; an active structure 150 (e.g., including a first active region 130 and a second active region 540); and the shallow trench isolation 120 (including the first isolation region 122 and the second isolation region 124), the same parts will not be described again. The main difference between the present embodiment and the previous embodiments is that a plurality of openings 542 and 544 are additionally formed on the substrate 110, and the first side 541 and the second side 543 of the second active region 540 are respectively cut into a plurality of segments 541a and 543 a.

In detail, the segments 541a of the first side 541 are respectively surrounded by the sti 120 and separated from each other, and the segments 541a respectively contact the third active segment 135 or the second active segment 133. On the other hand, the segments 543a of the second side 543 are also separated from each other by the sti 120, and contact portions of the second active segment 133, as shown in fig. 7. Thus, the semiconductor device 500 according to the third preferred embodiment of the present disclosure can also stabilize and strengthen the structure of the second active region 540 by providing different extension lengths through the second active segment 133 and the third active segment 135, so as to improve the stress around the semiconductor device 500 and avoid the problem of collapse or crack of the surrounding structure. In addition, in the semiconductor device 500 of the present embodiment, the openings 542 and 544 are additionally disposed on the second active region 540, so that the stress borne by the sides (including the first side 541 and the second side 543) of the second active region 540 can be further dispersed, so as to further enhance the performance of the devices subsequently formed on the semiconductor device 500.

In general, the semiconductor device of the present disclosure is provided with active segments having different lengths on the left and right sides and the upper and lower sides of the active segment of the active region or the memory region, respectively, and the active segments having different lengths are further connected to at least one side of the active region of the peripheral region. Therefore, different extension lengths can be provided through the active segments with different lengths to stabilize and strengthen the structure of the active region, so as to improve the stress around the semiconductor device and avoid the problems of collapse or crack of the surrounding structure and the like. In addition, the side of the active region may further include a plurality of segments separated from each other to further distribute the stress applied to the side. In this context, the semiconductor device of the present disclosure may be used to form other semiconductor active devices, such as memory devices or transistor devices, to further enhance the device performance of the subsequently formed devices.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (11)

1. A semiconductor device, comprising:

a substrate;

an active structure disposed within the substrate, the active structure including a plurality of first active segments and a plurality of second active segments, the first and second active segments extending in a first direction parallel to each other and spaced apart from each other; and

the shallow trench isolation is arranged in the substrate and surrounds the active structure, the shallow trench isolation comprises a plurality of first isolation regions and a plurality of second isolation regions, the first isolation regions are arranged between any two adjacent first active segments, the second isolation regions are arranged between the second active segments, and the maximum width of the second isolation regions is larger than that of the first isolation regions.

2. The semiconductor device according to claim 1, wherein the first active segments have the same first length in the first direction, and the first length is greater than the length of the second active segments in the first direction.

3. The semiconductor device according to claim 1, wherein any two adjacent second active segments have mutually aligned side edges in a second direction, wherein the second direction intersects but is not perpendicular to the first direction.

4. The semiconductor device according to claim 3, wherein the second isolation regions are disposed on opposite sides of the first isolation region and are aligned with each other in a third direction perpendicular to the second direction.

5. The semiconductor device of claim 4, wherein the active structure further comprises an active region surrounding the first active segment and the second active segment and directly contacting a portion of the second active segment.

6. The semiconductor device according to claim 5, wherein the active region comprises at least one first side extending in the second direction and at least one second side extending in a third direction.

7. The semiconductor device of claim 5, wherein the active structure further comprises a plurality of third active segments extending parallel to and spaced apart from each other toward the first direction, the third active segments all directly contacting the active region.

8. The semiconductor device according to claim 7, wherein the third active segments have different lengths in the first direction, respectively.

9. The semiconductor device according to claim 7, wherein a length of the third active segment in the first direction is different from the first length.

10. The semiconductor device according to claim 7, wherein the active region further comprises a plurality of segments, each of the segments being separated from each other and directly contacting any two adjacent third active segments, any two adjacent second active segments, or adjacent third active segments and second active segments.

11. The semiconductor device according to claim 10, wherein lengths of the two adjacent third active segments in the first direction are different from each other.

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