CN215578558U - Capacitor, power circuit and chip - Google Patents
Capacitor, power circuit and chip Download PDFInfo
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- CN215578558U CN215578558U CN202122682537.9U CN202122682537U CN215578558U CN 215578558 U CN215578558 U CN 215578558U CN 202122682537 U CN202122682537 U CN 202122682537U CN 215578558 U CN215578558 U CN 215578558U
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- 239000003990 capacitor Substances 0.000 title claims abstract description 203
- 229910052751 metal Inorganic materials 0.000 claims description 88
- 239000002184 metal Substances 0.000 claims description 88
- 239000000758 substrate Substances 0.000 claims description 15
- 239000012212 insulator Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012938 design process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- NRZWYNLTFLDQQX-UHFFFAOYSA-N p-tert-Amylphenol Chemical compound CCC(C)(C)C1=CC=C(O)C=C1 NRZWYNLTFLDQQX-UHFFFAOYSA-N 0.000 description 1
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Abstract
The embodiment of the utility model provides a capacitor, a power supply circuit and a chip. The capacitor includes: MIM capacitor, MOM capacitor and MOS capacitor; the first end of the MOM capacitor is connected with the grid electrode of the MOS capacitor and the upper polar plate of the MIM capacitor; the second end of the MOM capacitor is connected with the source electrode and the drain electrode of the MOS capacitor and the lower electrode plate of the MIM capacitor; the polarity of the upper polar plate is opposite to that of the lower polar plate. The utility model fully utilizes the photomask layer resources in the chip manufacturing process, further improves the capacitance value of the decoupling capacitor in unit area, saves the layout area and reduces the chip cost.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a capacitor, a power supply circuit and a chip.
Background
With the rapid progress of semiconductor technology, especially after the ultra-deep submicron level, the influence of power supply noise on the chip becomes more serious. In designing a power supply network, a large number of decoupling capacitors are usually added to each power supply domain of a chip to suppress power supply noise. The decoupling capacitor can also be used as a charge storage to supply power to the circuit additionally, so that the voltage drop caused by sudden change of current is prevented, and the time sequence and the performance of the circuit are prevented from being influenced.
For mass-produced chips, designers pay more and more attention to the cost of the chip while considering the performance. And compressing chip area is the most cost effective approach. To remove noise and reduce voltage fluctuations, a large area of decoupling capacitor is typically added, which can significantly increase chip manufacturing costs. How to obtain a decoupling capacitor with a larger capacitance value in a smaller area is a problem to be solved urgently.
SUMMERY OF THE UTILITY MODEL
In view of this, the present invention provides a capacitor to further increase the capacitance of the decoupling capacitor per unit area, and save the layout area, thereby reducing the chip cost.
In order to achieve the purpose, the technical scheme of the utility model is realized as follows:
a capacitor, comprising: MIM capacitor, MOM capacitor and MOS capacitor; the first end of the MOM capacitor is connected with the grid electrode of the MOS capacitor and the upper polar plate of the MIM capacitor; the second end of the MOM capacitor is connected with the source electrode and the drain electrode of the MOS capacitor and the lower electrode plate of the MIM capacitor; the polarity of the upper polar plate is opposite to that of the lower polar plate.
Further, the capacitor further comprises a substrate and a first metal layer (M1), wherein the substrate is positioned below the MOS capacitor, and the first metal layer (M1) is positioned between the MOS capacitor and the MOM capacitor; the gate of the MOS capacitor is connected to the first metal layer (M1) through the contact hole to serve as the anode of the MOS capacitor; the source electrode, the drain electrode and the substrate of the MOS capacitor are connected to the first metal layer (M1) through the contact hole to serve as the cathode of the MOS capacitor.
Further, the capacitor also comprises a top layer metal (Mn) and a second top layer metal (Mtop-1), wherein the top layer metal (Mn) is positioned above the upper plate of the MIM capacitor, and the lower plate of the MIM capacitor is arranged in the second top layer metal (Mtop-1); the first end of the MOM capacitor is connected with the upper plate of the MIM capacitor at the top metal (Mn); and the second end of the MOM capacitor is connected with the lower electrode plate of the MIM capacitor through the contact hole.
Further, the upper plate between the top metal (Mn) and the second top metal (Mtop-1) comprises at least one CTM medium.
Further, the CTM medium is an insulator metal.
Further, the MOM capacitor is formed by overlapping a plurality of capacitor layers.
Further, the capacitor comprises a plurality of finger electrodes, and the finger electrodes form an interdigital electrode array; the finger electrodes are connected with the finger electrodes through metal strips.
The utility model also provides a power supply circuit comprising a power domain and a capacitor as described in any one of the above, the capacitor being connected in parallel with the power domain.
The utility model also provides a chip which comprises at least one capacitor.
The capacitor provided by the utility model introduces the MIM capacitor on the basis of parallel connection of the MOS capacitor and the MOM capacitor, because the MIM capacitor is generally arranged between the top layer metal (Mn) and the next top layer metal (Mtop-1), the MIM capacitor is connected with the MOS and the MOM capacitor in parallel in space, the photomask layer resource in the chip manufacturing process is fully utilized, the capacitance value of the decoupling capacitor in unit area is further improved, the layout area is saved, and the chip cost is reduced.
Additional features and advantages of the utility model will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the utility model and, together with the description, serve to explain the utility model and not to limit the utility model. In the drawings:
FIG. 1 is a schematic diagram of a capacitor of the present invention;
fig. 2 is a schematic structural diagram of a capacitor of the present invention.
Detailed Description
In addition, the embodiments of the present invention and the features of the embodiments may be combined with each other without conflict.
The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a schematic diagram of a capacitor according to the present invention, as shown in fig. 1, the capacitor includes an MIM capacitor 300, an MOM capacitor 200, and a MOS capacitor 100; a first end of the MOM capacitor 200 is connected to a gate of the MOS capacitor 100 and an upper plate of the MIM capacitor 300; the second end of the MOM capacitor 200 is connected to the source and drain of the MOS capacitor 100 and the lower plate of the MIM capacitor 300; the polarity of the upper polar plate is opposite to that of the lower polar plate.
Fig. 2 is a schematic structural diagram of a capacitor of the present invention. The capacitor of fig. 2 is, from bottom to top: the structure comprises a substrate, an epitaxial layer, a CONT contact hole, a first metal layer (M1), a first through hole (VIA 1), a second metal layer (M2), a second through hole (VIA 2), a third metal layer (M3), a third through hole (VIA 3), a fourth metal layer (M4), a penultimate metal layer (Mtop-2), an n-1 through hole (VIAtop-1), a second top layer metal (Mtop-1), an nth through hole (VIAn) and a top layer metal (Mn).
As shown in fig. 2, the capacitor includes a MIM capacitor, a MOM capacitor, and a MOS capacitor. The capacitor is formed by spatially overlapping and connecting an MIM capacitor, an MOM capacitor and a MOS capacitor in parallel. The MOM capacitor is superposed on the MOS capacitor, and the MIM capacitor is superposed on the MOM capacitor. Specifically, the MOS capacitor includes: a substrate, an epitaxial layer, a CONT contact hole, a first metal layer (M1); the MOM capacitor comprises: a second metal layer (M2), a second through hole (VIA 2), a third metal layer (M3), a third through hole (VIA 3), a fourth metal layer (M4) and a penultimate metal layer (Mtop-2); the MIM capacitor includes: the second top layer metal (Mtop-1), the nth through hole (VIAn) and the top layer metal (Mn).
According to a specific embodiment, the MOS capacitor is an NMOS capacitor. The MOS capacitor is of a two-end structure, the capacitance value is not accurate, the capacitance value which changes along with the change of control voltage can be realized, and the connection method of an upper electrode plate and a lower electrode plate is not interchangeable. The MOM capacitor is an interdigital capacitor and mainly comprisesWith the capacitance between the edges of the same layer of metal, in the layout design process, in order to reduce the area, multiple layers of metal (such as M2, M3, M4 … M shown in fig. 2) can be stackedtop-2). MOM is formed naturally by the metal of the connecting wire, and can be formed by multiple layers of stack interdigital, and the connection method of an upper polar plate and a lower polar plate can be interchanged. The capacitor further comprises a substrate and a first metal layer (M1), wherein the substrate is positioned below the MOS capacitor, the source electrode, the drain electrode and the ptap of the MOS capacitor are positioned on an epitaxial layer, the epitaxial layer is positioned above the substrate, and the first metal layer (M1) is positioned between the MOS capacitor and the MOM capacitor; the gate of the MOS capacitor is connected to the first metal layer (M1) through the contact hole to serve as the anode of the MOS capacitor; the source electrode, the drain electrode and the substrate of the MOS capacitor are connected to the first metal layer (M1) through the contact hole to serve as the cathode of the MOS capacitor. The MOM capacitor is formed by overlapping a plurality of capacitor layers. The capacitor layer includes a capacitor and at least two sets of metal strips. The capacitor comprises a plurality of finger electrodes which form an interdigital electrode array; the finger electrodes are connected by metal strips. The first end of the MOM capacitor is a positive electrode, and the second end of the MOM capacitor is a negative electrode.
The capacitor may further include a top layer metal (Mn) located above the top plate of the MIM capacitor and a next top layer metal (Mtop-1) located within the next top layer metal (Mtop-1). The MIM capacitor is called as a plate capacitor and is formed by Mn and Mn-1 metals, and is formed by utilizing a capacitor between an upper layer metal and a lower layer metal, because the upper layer metal and the lower layer metal rest an oxide layer far away in a three-dimensional space, a CTM layer is added on the upper layer metal and the lower layer metal, and the upper layer metal and the lower layer metal are connected by using a through hole, so that the distance between plates is reduced, and the capacitance is increased. The MIM capacitor is similar to a plate capacitor, the capacitance value is more accurate, and the capacitance value cannot change along with the change of bias voltage. The first end of the MOM capacitor is connected with the upper plate of the MIM capacitor at the top metal (Mn); and the second end of the MOM capacitor is connected with the lower electrode plate of the MIM capacitor through the contact hole. The upper plate between the top metal (Mn) and the second top metal (Mtop-1) comprises at least one CTM medium. The CTM medium is an insulator metal.
The utility model discloses a capacitor, which comprises a decoupling capacitor structure capable of effectively saving the area of a chip and relates to the technical field of semiconductors. Taking an N-type MOM capacitor as an example, the gate and source-drain ends of an NMOS and a substrate are connected to M1 (a first metal layer) through a CONT contact hole, the source-drain end of an MOS transistor and the substrate are connected to each other through metal 1 in an M1 layer to serve as a cathode of the MOS capacitor, and the metal 1 connected to the gate of the MOS transistor serves as an anode of the MOS capacitor. The MOM capacitor is formed between M2 (the second metal layer) and Mtop-2 (the second last metal layer), and the capacitor is formed by the side surfaces of two different metal wires in each metal layer. The two layers of metal are interconnected by VIAs VIA between them. The positive electrode and the negative electrode of the MOS capacitor are respectively connected through the positive electrode and the negative electrode of the VIA1 and the MOM capacitor to form a parallel capacitor. And the MIM capacitor is formed between Mtop-1 (next top metal) and Mn (top metal). The CTM is a special metal layer between a top metal (Mn) and a next top metal (Mtop-1) and is used as an upper plate of the MIM capacitor, the next top metal (Mtop-1) is a lower plate of the MIM capacitor, and a medium is arranged between the top metal (Mn) and the next top metal (Mtop-1) to form the MIM capacitor. The anode of the MOM capacitor is upwards communicated to the top layer metal (Mn) through VIAtop-1 and VIAn, and the cathode of the MOM capacitor is connected with the lower pole plate of the MIM capacitor through VIAtop-1. The upper and lower plates of the MIM capacitor are communicated to the top metal (Mn) through VIAn, and the MOM capacitor anode and the upper plate of the MIM capacitor are interconnected by the top metal (Mn) in the Mn layer. Thus, three kinds of decoupling capacitors connected in parallel are realized.
The utility model also provides a power supply circuit, which comprises a power supply domain and the capacitor, wherein the capacitor is connected with the power supply domain in parallel. The MOS capacitor, the MOM capacitor and the MIM capacitor are overlapped from bottom to top in space. The positive and negative electrodes of the MOS capacitor are connected with the positive and negative electrodes of the MOM capacitor through a plurality of groups of through holes, and the positive and negative electrodes of the MOM capacitor are connected with the upper and lower electrode plates of the MIM capacitor through a plurality of groups of through holes, so that three capacitor structures connected in parallel are formed. One end of the MOM capacitor is connected with the grid electrode of the MOS tube and the upper polar plate of the MIM capacitor and is connected with a power supply; and the other end of the MOM capacitor is connected with the source and drain ends of the MOS tube and the lower electrode plate of the MIM capacitor, and is connected with the ground wire and the substrate in contact. And the positive electrode and the negative electrode of the parallel capacitor are respectively connected with the power ground of the power domain needing noise filtering at the top layer of the chip, so that the decoupling effect is realized. The decoupling capacitor fully utilizes the resources of the mask layer, has high capacitance density, and can effectively reduce the area of a decoupling capacitor domain, thereby reducing the area of a chip and saving the cost.
The capacitor provided by the utility model introduces the MIM capacitor on the basis of parallel connection of the MOS capacitor and the MOM capacitor, and the MIM capacitor is generally arranged between the top layer metal (Mn) and the next top layer metal (Mtop-1) and can be connected with the MOS and the MOM capacitor in parallel in space, so that the photomask layer resources in the chip manufacturing process are fully utilized, the capacitance value of the decoupling capacitor in unit area is further improved, the layout area is saved, and the chip cost is reduced.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the utility model. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination. The same shall be construed as disclosed in the embodiments of the present invention as long as it does not depart from the idea of the embodiments of the present invention.
Claims (9)
1. A capacitor, comprising:
MIM capacitor, MOM capacitor and MOS capacitor;
the first end of the MOM capacitor is connected with the grid electrode of the MOS capacitor and the upper polar plate of the MIM capacitor;
the second end of the MOM capacitor is connected with the source electrode and the drain electrode of the MOS capacitor and the lower electrode plate of the MIM capacitor;
the polarity of the upper polar plate is opposite to that of the lower polar plate.
2. The capacitor according to claim 1,
the capacitor further comprises a substrate and a first metal layer, wherein the substrate is positioned below the MOS capacitor, and the first metal layer is positioned between the MOS capacitor and the MOM capacitor;
the grid electrode of the MOS capacitor is connected to the first metal layer through the contact hole to serve as the anode of the MOS capacitor;
and the source electrode, the drain electrode and the substrate of the MOS capacitor are connected to the first metal layer through the contact hole to serve as the cathode of the MOS capacitor.
3. The capacitor according to claim 1,
the capacitor also comprises a top metal and a secondary top metal, the top metal is positioned above an upper polar plate of the MIM capacitor, and a lower polar plate of the MIM capacitor is arranged in the secondary top metal;
the first end of the MOM capacitor is connected with the upper plate of the MIM capacitor at the top metal layer;
and the second end of the MOM capacitor is connected with the lower plate of the MIM capacitor through the contact hole.
4. The capacitor according to claim 3,
the upper plate between the top metal and the second top metal comprises at least one CTM dielectric.
5. The capacitor according to claim 4,
the CTM medium is an insulator metal.
6. The capacitor according to claim 1,
the MOM capacitor is formed by overlapping a plurality of capacitor layers.
7. The capacitor according to claim 1,
the capacitor comprises a plurality of finger electrodes which form an interdigital electrode array;
the finger electrodes are connected by metal strips.
8. A power supply circuit comprising a power domain and a capacitor as claimed in any one of claims 1 to 7 connected in parallel with the power domain.
9. A chip comprising at least one capacitor according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122682537.9U CN215578558U (en) | 2021-11-04 | 2021-11-04 | Capacitor, power circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122682537.9U CN215578558U (en) | 2021-11-04 | 2021-11-04 | Capacitor, power circuit and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215578558U true CN215578558U (en) | 2022-01-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122682537.9U Active CN215578558U (en) | 2021-11-04 | 2021-11-04 | Capacitor, power circuit and chip |
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| Country | Link |
|---|---|
| CN (1) | CN215578558U (en) |
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2021
- 2021-11-04 CN CN202122682537.9U patent/CN215578558U/en active Active
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