CN117613037A - Integrated circuit, chip and electronic equipment - Google Patents
Integrated circuit, chip and electronic equipment Download PDFInfo
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- CN117613037A CN117613037A CN202311447060.3A CN202311447060A CN117613037A CN 117613037 A CN117613037 A CN 117613037A CN 202311447060 A CN202311447060 A CN 202311447060A CN 117613037 A CN117613037 A CN 117613037A
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- 239000002184 metal Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an integrated circuit, a chip and electronic equipment, wherein the resistor insulation layer spans a plurality of grids and intervals between adjacent MOS tubes; forming a resistor layer on the resistor insulating layer, wherein the resistor layer spans a plurality of grids and intervals between adjacent MOS tubes, the resistor is formed by the resistor layer, and the projection of the resistor layer towards the active layer does not fall into the source electrode area and the drain electrode area; the resistor layer is connected with respective endpoints in the metal connecting layer above the resistor layer through resistor contact holes at two ends of the resistor layer, the grid electrode passing through the grid electrode contact holes, the source electrode region passing through the source electrode contact holes and the drain electrode region passing through the drain electrode contact holes, wherein projections of the resistor contact holes, the grid electrode contact holes, the source electrode contact holes and the drain electrode contact holes towards the active layer are not overlapped with each other.
Description
Technical Field
The present invention relates to the field of circuits, and in particular, to an integrated circuit, a chip, and an electronic device.
Background
In the conventional CMOS fabrication process of an integrated circuit, resistors and MOS transistors are often disposed in different regions of a substrate. In order to ensure uniformity of the subsequent CMP (chemical mechanical polishing) step, an Active Area (AA) blank (dummy) pattern is inserted under the resistor to increase the active area density (AAdensity) to meet the manufacturing requirements where the resistor is used in a large area. Therefore, the area below the resistor array is not really used as a device for a circuit, the integration level of the unit area of the silicon chip is low, and a certain area cost is lost.
In some integrated circuits, resistors are formed on the active layer, but the structure of these integrated circuits is not compact and reasonable.
Disclosure of Invention
Based on the above-mentioned current situation, a main object of the present invention is to provide an integrated circuit, a chip and an electronic device, which can reduce the influence of the resistor on the MOS transistor on the basis of making the integrated circuit compact in structure and high in wafer utilization.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
an integrated circuit comprising a resistor and a plurality of MOS transistors side by side, each MOS transistor comprising a gate, and a channel region, a source region, and a drain region in an active layer with a space between adjacent MOS transistors, the integrated circuit further comprising a resistor insulating layer formed on a surface of the gate, the resistor insulating layer spanning the plurality of gates and the space between adjacent MOS transistors; forming a resistor layer on the resistor insulating layer, wherein the resistor layer spans a plurality of grids and intervals between adjacent MOS tubes, the resistor is formed by the resistor layer, and the projection of the resistor layer towards the active layer does not fall into the source electrode area and the drain electrode area; the resistor layer is connected with respective endpoints in the metal connecting layer above the resistor layer through resistor contact holes at two ends of the resistor layer, the grid electrode passing through the grid electrode contact holes, the source electrode region passing through the source electrode contact holes and the drain electrode region passing through the drain electrode contact holes, wherein projections of the resistor contact holes, the grid electrode contact holes, the source electrode contact holes and the drain electrode contact holes towards the active layer are not overlapped, and the grid electrode contact holes are staggered with the resistor layer.
Preferably, the thickness of the resistive insulating layer is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold.
Preferably, the active layers of the plurality of MOS transistors are located in the same well of the active substrate.
Preferably, the projection of the resistive layer towards the gate is located in the middle of the gate.
In the above scheme, the resistor layer is disposed on the multiple MOS transistors, and the resistor layer 400 spans the gates on the multiple MOS transistors, so that the utilization efficiency of the wafer is improved, and meanwhile, since the resistor layer does not span the source region and the drain region, the influence of the resistor on the MOS transistors can be limited to the gates, and the influence on the source region and the drain region is reduced.
The invention also provides an integrated circuit, which comprises a resistor and a plurality of MOS tubes arranged side by side, wherein each MOS tube comprises a grid electrode, a channel region, a source region and a drain region which are positioned on an active layer, and a space is reserved between adjacent MOS tubes; forming a resistor layer on the resistor insulating layer, wherein the resistor layer spans the plurality of gates, the plurality of source regions, the plurality of drain regions and the intervals between adjacent MOS tubes, and the resistor is formed by the resistor layer; the resistor layer is connected with respective endpoints in the metal connecting layer above the resistor layer through resistor contact holes at two ends of the resistor layer, the grid electrode passes through the grid electrode contact holes, the source electrode region passes through the source electrode contact holes, and the drain electrode region passes through the drain electrode contact holes, wherein projections of the resistor contact holes, the grid electrode contact holes, the source electrode contact holes and the drain electrode contact holes towards the active layer are not overlapped, and the source electrode contact holes and the drain electrode contact holes are staggered with the resistor layer respectively.
Preferably, the thickness of the resistive insulating layer is greater than a thickness threshold and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold to avoid a voltage formed on the resistive layer from affecting the channel region.
Preferably, the active layers of the plurality of MOS transistors are located in the same well of the active substrate.
Preferably, the projection of the resistive layer towards the gate is located in the middle of the gate, the source region and the drain region.
In the scheme, the resistor layer is arranged on the MOS tubes, so that the utilization efficiency of the wafer is improved, and meanwhile, the resistor layer spans across the grid electrode, the source electrode regions and the drain electrode regions on the MOS tubes, so that the influence of the resistor on the MOS tubes can be dispersed to the grid electrode, the source electrode regions and the drain electrode regions.
The invention also provides an integrated circuit, which comprises a resistor and a MOS tube, wherein the MOS tube comprises a grid electrode, a channel region, a source region and a drain region which are positioned on an active layer, and the integrated circuit further comprises a resistor insulating layer which is formed on the surface of the grid electrode, and the projection of the resistor insulating layer towards the grid electrode is smaller than and falls into the region of the grid electrode; forming a resistor layer on the resistor insulating layer, wherein the projection of the resistor layer towards the grid electrode is smaller than and falls into the region of the grid electrode, and the projection of the resistor layer towards the active layer does not fall into the source electrode region and the drain electrode region, and the resistor is formed by the resistor layer; the resistor layer is connected with respective endpoints in the metal connecting layer above the resistor layer through resistor contact holes at two ends of the resistor layer, the grid electrode passing through the grid electrode contact holes, the source electrode region passing through the source electrode contact holes and the drain electrode region passing through the drain electrode contact holes, wherein projections of the resistor contact holes, the grid electrode contact holes, the source electrode contact holes and the drain electrode contact holes towards the active layer are not overlapped with each other.
Since the projection of the resistive layer toward the gate electrode is smaller than and falls into the region of the gate electrode, the length and width of the resistive layer can be set according to actual needs, and can be set longer in the length along the drain-source electrode connection line direction or longer in the perpendicular direction of the connection line direction.
Preferably, the thickness of the resistive insulating layer is greater than a thickness threshold and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold to avoid a voltage formed on the resistive layer from affecting the channel region.
Preferably, the projection of the resistive layer towards the gate is located in the middle of the gate.
The invention also provides a chip comprising any one of the integrated circuits.
The invention also provides electronic equipment comprising the chip.
In the scheme, the resistor layer is arranged on one MOS tube, so that the utilization efficiency of the wafer is improved, and meanwhile, the influence of the resistor on the MOS tube can be limited to the grid electrode because the projection of the resistor layer to the grid electrode is smaller than the projection of the resistor layer to the grid electrode and falls into the region of the grid electrode, and the influence on the source electrode region and the drain electrode region is reduced.
Other advantages of the present invention will be set forth in the description of specific technical features and solutions, by which those skilled in the art should understand the advantages that the technical features and solutions bring.
Drawings
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. In the figure:
FIG. 1 is a schematic cross-sectional view of an integrated circuit according to a preferred embodiment of the present invention;
FIG. 2 is a schematic top view of the integrated circuit of the embodiment of FIG. 1;
FIG. 3 is a schematic cross-sectional view of an integrated circuit according to another preferred embodiment of the present invention;
FIG. 4 is a schematic top view of the integrated circuit of the embodiment of FIG. 3;
FIG. 5 is a schematic cross-sectional view of an integrated circuit according to another preferred embodiment of the invention;
FIG. 6 is a schematic top view of the integrated circuit of the embodiment of FIG. 5;
fig. 7 is a schematic cross-sectional view of an integrated circuit according to another preferred embodiment of the invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in order to avoid obscuring the present invention, and in order to avoid obscuring the present invention, well-known methods, procedures, flows, and components are not presented in detail.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
Example 1
Fig. 1 and 2 are schematic diagrams of an integrated circuit according to an embodiment of the present invention, where the integrated circuit includes a resistor 400, a resistor insulation layer 300, and a plurality of MOS transistors 200 (3 MOS transistors 200 are shown in the drawings) arranged side by side, and in this embodiment, the resistor 400 is formed on the plurality of MOS transistors 200. The multiple MOS transistors 200 are sequentially arranged, where each MOS transistor 200 includes a gate 210 (formed by a metal layer located on a channel region 230), and a channel region 230, a source region 240, and a drain region 250 located on an active layer 110, and adjacent MOS transistors 200 are separated by a space, for example, by Shallow Trench Isolation (STI) 120; the resistive insulating layer 300 is formed on the surface of the gate electrode 210, and the resistive insulating layer 300 spans the plurality of gate electrodes 210 and the intervals between the adjacent MOS transistors 200; a resistive layer 400 is formed on the resistive insulating layer 300, the resistive layer 400 also spans the plurality of gates 210 and the spacing between adjacent MOS transistors 200, the resistive layer 400 is formed of the resistive layer 400, and a projection of the resistive layer 400 toward the active layer 110 does not fall into the source region 240 and the drain region 250, i.e., the resistive layer 400 does not span the source region 240 and the drain region 250. It will be appreciated that the source region 240 and the drain region 250 in the figures may be interchanged.
The resistor layer 400 is connected to respective terminals 411 in a metal connection layer (e.g., the first metal layer M1 nearest to the active layer 110) above the resistor layer 400 through resistor contact holes 410 (i.e., metal pillars) at both ends of the resistor layer 400, and the resistor 400 can be connected to other components in the integrated circuit through the terminals 411; the gate 210 is connected to a corresponding terminal 212 in the metal connection layer above the resistive layer 400 through a gate contact hole 211 (i.e., a metal pillar), and the gate 210 can be connected to other components in the integrated circuit through the terminal 212; the source region 240 is connected to a corresponding terminal 242 in the metal connection layer above the resistive layer 400 through a source contact 241 (i.e., a metal pillar), and the source region 240 can be connected to other components in the integrated circuit through the terminal 242; the drain region 250 is connected to a corresponding terminal 252 in the metal connection layer above the resistive layer 400 through a drain contact hole 251 (i.e., a metal pillar), and the drain region 250 can be connected to other components in the integrated circuit through the terminal 252; the resistive contact hole 410, the gate contact hole 211, the source contact hole 241, and the drain contact hole 251 do not overlap each other in projection toward the active layer 110, and the gate contact hole 211 is offset from the resistive layer 400.
In this embodiment, the resistor layer 400 is disposed on the multiple MOS transistors 200, and the resistor layer 400 spans the gates 210 on the multiple MOS transistors 200, but does not span the source region 240 and the drain region 250, so that the influence of the resistor 400 on the MOS transistors 200 can be limited to the gates 210, and the influence on the source region 240 and the drain region 250 can be reduced.
In some embodiments, the thickness of the resistive insulating layer 300 is greater than a thickness threshold and the dielectric constant of the resistive insulating layer 300 is greater than a dielectric constant threshold to avoid a voltage formed on the resistive layer 400 from affecting the channel region 230, e.g., to avoid a potential on the resistive layer 400 from causing conduction of the channel region 230 when the gate 210 is low.
The active layers 110 of the MOS transistors 200 may be located in the same well (well) of the active substrate 100 or may be disposed in different wells. In some embodiments, the active layers 110 of the multiple MOS transistors 200 are located in the same well of the active substrate 100, so that the parasitic capacitance between the resistive layer 400 and the different MOS transistors 200 is kept as uniform as possible, which may bring about some benefits, such as simpler circuit design.
In some embodiments, the projection of the resistive layer 400 toward the gate 210 is positioned in the middle of the gate 210, which may provide benefits, such as a more balanced effect of the resistive layer 400 on the gate 210 and the channel region 230, facilitating circuit design.
Other metal capacitors such as MOM or MIM can be further stacked above the resistor 400, and therefore the scheme can be compatible with the integrated circuit structure of the traditional metal capacitor.
Example 2
Fig. 3 and 4 are schematic diagrams of an integrated circuit according to another embodiment of the present invention, where the integrated circuit includes a resistor 400, a resistor insulation layer 300, and a plurality of MOS transistors 200 (3 MOS transistors 200 are shown in the drawing), and in this embodiment, the resistor 400 is formed on the plurality of MOS transistors 200. The multiple MOS transistors 200 are sequentially arranged, where each MOS transistor 200 includes a gate 210 (formed by a metal layer located on a channel region 230), and a channel region 230, a source region 240, and a drain region 250 located on an active layer 110, and adjacent MOS transistors 200 are separated by a space, for example, by Shallow Trench Isolation (STI) 120; the resistive insulating layer 300 is formed on the surface of the gate electrode 210, and the resistive insulating layer 300 spans the plurality of gate electrodes 210, the plurality of source regions 240, the plurality of drain regions 250, and the spaces between adjacent MOS transistors 200; a resistive layer 400 is formed on the resistive insulating layer 300, the resistive layer 400 also spans the plurality of gates 210, the plurality of source regions 240, the plurality of drain regions 250, and the spacing between adjacent MOS transistors 200, the resistive layer 400 being formed of the resistive layer 400. It will be appreciated that the source region 240 and the drain region 250 in the figures may be interchanged.
The resistor layer 400 is connected to respective terminals 411 in a metal connection layer (e.g., the first metal layer M1 nearest to the active layer 110) above the resistor layer 400 through resistor contact holes 410 (i.e., metal pillars) at both ends of the resistor layer 400, and the resistor 400 can be connected to other components in the integrated circuit through the terminals 411; the gate 210 is connected to a corresponding terminal 212 in the metal connection layer above the resistive layer 400 through a gate contact hole 211 (i.e., a metal pillar), and the gate 210 can be connected to other components in the integrated circuit through the terminal 212; the source region 240 is connected to a corresponding terminal 242 in the metal connection layer above the resistive layer 400 through a source contact 241 (i.e., a metal pillar), and the source region 240 can be connected to other components in the integrated circuit through the terminal 242; the drain region 250 is connected to a corresponding terminal 252 in the metal connection layer above the resistive layer 400 through a drain contact hole 251 (i.e., a metal pillar), and the drain region 250 can be connected to other components in the integrated circuit through the terminal 252; the resistive contact hole 410, the gate contact hole 211, the source contact hole 241, and the drain contact hole 251 do not overlap each other in projection toward the active layer 110, and the source contact hole 241 and the drain contact hole 251 are respectively offset from the resistive layer 400.
In this embodiment, the resistor layer 400 is disposed on the plurality of MOS transistors 200, and the resistor layer 400 spans the gate 210, the plurality of source regions 240, and the plurality of drain regions 250 on the plurality of MOS transistors 200, so that the influence of the resistor 400 on the MOS transistors 200 can be dispersed to the gate 210, the source regions 240, and the drain regions 250.
In some embodiments, the thickness of the resistive insulating layer 300 is greater than a thickness threshold and the dielectric constant of the resistive insulating layer 300 is greater than a dielectric constant threshold to avoid a voltage formed on the resistive layer 400 from affecting the channel region 230, e.g., to avoid a potential on the resistive layer 400 from causing conduction of the channel region 230 when the gate 210 is low.
The active layers 110 of the MOS transistors 200 may be located in the same well (well) of the active substrate 100 or may be disposed in different wells. In some embodiments, the active layers 110 of the multiple MOS transistors 200 are located in the same well of the active substrate 100, so that the parasitic capacitance between the resistive layer 400 and the different MOS transistors 200 is kept as uniform as possible, which may bring about some benefits, such as simpler circuit design.
In some embodiments, the projection of the resistive layer 400 toward the gate 210 is positioned in the middle of the gate 210, the source region 240, and the drain region 250, which may provide benefits such as a more balanced effect of the resistive layer 400 on the gate 210, the channel region 230, the source region 240, and the drain region 250, facilitating circuit design.
Other metal capacitors such as MOM or MIM can be further stacked above the resistor 400, and therefore the scheme can be compatible with the integrated circuit structure of the traditional metal capacitor.
Example 3
Fig. 5 and 6 are schematic diagrams of an integrated circuit according to another embodiment of the present invention, the integrated circuit includes a resistor 400, a resistor insulation layer 300, and a MOS transistor 200, and in this embodiment, the resistor 400 is formed on the MOS transistor 200. The MOS transistor 200 includes a gate 210 (composed of a metal layer on a channel region 230), a channel region 230 on an active layer 110, a source region 240, and a drain region 250; the resistive insulating layer 300 is formed on the surface of the gate electrode 210, and the projection of the resistive insulating layer 300 toward the gate electrode 210 is smaller than and falls into the region inside the gate electrode 210; the resistive layer 400 is formed on the resistive insulating layer 300, the projection of the resistive layer 400 toward the gate electrode 210 is smaller than and falls inside the region of the gate electrode 210, and the projection of the resistive layer 400 toward the active layer 110 does not fall into the source region 240 and the drain region 250, and the resistive layer 400 is formed of the resistive layer 400. It will be appreciated that the source region 240 and the drain region 250 in the figures may be interchanged.
The resistor layer 400 is connected to respective terminals 411 in a metal connection layer (e.g., a first metal layer nearest to the active layer 110) above the resistor layer 400 through resistor contact holes 410 (i.e., metal pillars) at both ends of the resistor layer 400, and the resistor 400 can be connected to other components in the integrated circuit through the terminals 411; the gate 210 is connected to a corresponding terminal 212 in the metal connection layer above the resistive layer 400 through a gate contact hole 211 (i.e., a metal pillar), and the gate 210 can be connected to other components in the integrated circuit through the terminal 212; the source region 240 is connected to a corresponding terminal 242 in the metal connection layer above the resistive layer 400 through a source contact 241 (i.e., a metal pillar), and the source region 240 can be connected to other components in the integrated circuit through the terminal 242; the drain region 250 is connected to a corresponding terminal 252 in the metal connection layer above the resistive layer 400 through a drain contact hole 251 (i.e., a metal pillar), and the drain region 250 can be connected to other components in the integrated circuit through the terminal 252; wherein, the projections of the resistive contact hole 410, the gate contact hole 211, the source contact hole 241, and the drain contact hole 251 toward the active layer 110 do not overlap each other.
In this embodiment, the resistor layer 400 is disposed on one MOS transistor 200, and the projection of the resistor layer 400 toward the gate 210 is smaller than and falls into the region of the gate 210, so that the influence of the resistor 400 on the MOS transistor 200 can be limited to the gate 210, and the influence on the source region 240 and the drain region 250 can be reduced.
In some embodiments, the thickness of the resistive insulating layer 300 is greater than a thickness threshold and the dielectric constant of the resistive insulating layer 300 is greater than a dielectric constant threshold to avoid a voltage formed on the resistive layer 400 from affecting the channel region 230, e.g., to avoid a potential on the resistive layer 400 from causing conduction of the channel region 230 when the gate 210 is low.
In some embodiments, the projection of the resistive layer 400 toward the gate 210 is located in the middle of the gate 210, the source region 240, and the drain region 250, which may provide benefits such as a more balanced effect of the resistive layer 400 on the gate 210 and the channel region 230, and convenience in circuit design.
As shown in fig. 7, MOM capacitance, e.g., a plurality of MOM layers 510, 520, and 530, may continue to be superimposed over resistor 400; in other embodiments, other metal capacitors such as MIM may be further stacked above the resistor 400, so that the scheme may be compatible with the integrated circuit structure of the conventional metal capacitor.
The invention also provides a chip comprising the integrated circuit of the previous embodiment.
The invention also provides electronic equipment, which comprises the chip.
Those skilled in the art will appreciate that the above-described preferred embodiments can be freely combined and stacked without conflict.
Those skilled in the art will appreciate that the above-described preferred embodiments can be freely combined and stacked without conflict.
It will be understood that the above-described embodiments are merely illustrative and not restrictive, and that all obvious or equivalent modifications and substitutions to the details given above may be made by those skilled in the art without departing from the underlying principles of the invention, are intended to be included within the scope of the appended claims.
Claims (13)
1. An integrated circuit comprising a resistor and a plurality of MOS transistors arranged side by side, each MOS transistor comprising a gate, a channel region, a source region and a drain region in an active layer, and a space between adjacent MOS transistors, characterized in that,
the integrated circuit further includes a resistive insulating layer formed on a surface of the gate electrode, the resistive insulating layer spanning the plurality of gate electrodes and the spacing between adjacent MOS transistors; forming a resistor layer on the resistor insulating layer, wherein the resistor layer spans a plurality of grids and intervals between adjacent MOS tubes, the resistor is formed by the resistor layer, and the projection of the resistor layer towards the active layer does not fall into the source electrode area and the drain electrode area;
the resistor layer is connected with respective endpoints in the metal connecting layer above the resistor layer through resistor contact holes at two ends of the resistor layer, the grid electrode passing through the grid electrode contact holes, the source electrode region passing through the source electrode contact holes and the drain electrode region passing through the drain electrode contact holes, wherein projections of the resistor contact holes, the grid electrode contact holes, the source electrode contact holes and the drain electrode contact holes towards the active layer are not overlapped, and the grid electrode contact holes are staggered with the resistor layer.
2. The integrated circuit of claim 1, wherein the integrated circuit comprises a plurality of integrated circuits,
the thickness of the resistive insulating layer is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold.
3. An integrated circuit as claimed in claim 1 or 2, characterized in that,
the active layers of the MOS tubes are located in the same well of the active substrate.
4. The integrated circuit of claim 1, wherein the integrated circuit comprises a plurality of integrated circuits,
the projection of the resistance layer towards the gate is positioned in the middle of the gate.
5. An integrated circuit comprising a resistor and a plurality of MOS transistors arranged side by side, each MOS transistor comprising a gate, a channel region, a source region and a drain region in an active layer, and a space between adjacent MOS transistors, characterized in that,
the integrated circuit further includes a resistive insulating layer formed on a surface of the gate electrode, the resistive insulating layer spanning the plurality of gate electrodes, the plurality of source regions, the plurality of drain regions, and the spacing between adjacent MOS transistors; forming a resistor layer on the resistor insulating layer, wherein the resistor layer spans the plurality of gates, the plurality of source regions, the plurality of drain regions and the intervals between adjacent MOS tubes, and the resistor is formed by the resistor layer;
the resistor layer is connected with respective endpoints in the metal connecting layer above the resistor layer through resistor contact holes at two ends of the resistor layer, the grid electrode passes through the grid electrode contact holes, the source electrode region passes through the source electrode contact holes, and the drain electrode region passes through the drain electrode contact holes, wherein projections of the resistor contact holes, the grid electrode contact holes, the source electrode contact holes and the drain electrode contact holes towards the active layer are not overlapped, and the source electrode contact holes and the drain electrode contact holes are staggered with the resistor layer respectively.
6. The integrated circuit of claim 5, wherein the integrated circuit comprises a plurality of integrated circuits,
the thickness of the resistive insulating layer is greater than a thickness threshold and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold to avoid a voltage formed on the resistive layer from affecting the channel region.
7. An integrated circuit as claimed in claim 5 or 6, characterized in that,
the active layers of the MOS tubes are located in the same well of the active substrate.
8. The integrated circuit of claim 5, wherein the integrated circuit comprises a plurality of integrated circuits,
the projection of the resistive layer toward the gate is positioned intermediate the gate, the source region, and the drain region.
9. An integrated circuit comprising a resistor and a MOS transistor, wherein the MOS transistor comprises a grid electrode, a channel region, a source region and a drain region which are positioned on an active layer,
the integrated circuit further includes a resistive insulating layer formed on a surface of the gate, a projection of the resistive insulating layer toward the gate being smaller than and falling within a region of the gate; forming a resistor layer on the resistor insulating layer, wherein the projection of the resistor layer towards the grid electrode is smaller than and falls into the region of the grid electrode, and the projection of the resistor layer towards the active layer does not fall into the source electrode region and the drain electrode region, and the resistor is formed by the resistor layer;
the resistor layer is connected with respective endpoints in the metal connecting layer above the resistor layer through resistor contact holes at two ends of the resistor layer, the grid electrode passing through the grid electrode contact holes, the source electrode region passing through the source electrode contact holes and the drain electrode region passing through the drain electrode contact holes, wherein projections of the resistor contact holes, the grid electrode contact holes, the source electrode contact holes and the drain electrode contact holes towards the active layer are not overlapped with each other.
10. The integrated circuit of claim 9, wherein the integrated circuit comprises a plurality of integrated circuits,
the thickness of the resistive insulating layer is greater than a thickness threshold and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold to avoid a voltage formed on the resistive layer from affecting the channel region.
11. The integrated circuit of claim 9, wherein the integrated circuit comprises a plurality of integrated circuits,
the projection of the resistance layer towards the gate is positioned in the middle of the gate.
12. A chip comprising an integrated circuit as claimed in any one of claims 1 to 11.
13. An electronic device comprising the chip of claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311447060.3A CN117613037A (en) | 2023-11-01 | 2023-11-01 | Integrated circuit, chip and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311447060.3A CN117613037A (en) | 2023-11-01 | 2023-11-01 | Integrated circuit, chip and electronic equipment |
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| Publication Number | Publication Date |
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| CN117613037A true CN117613037A (en) | 2024-02-27 |
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| CN202311447060.3A Pending CN117613037A (en) | 2023-11-01 | 2023-11-01 | Integrated circuit, chip and electronic equipment |
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| CN (1) | CN117613037A (en) |
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