JP2009071007A - Method for layout of integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for layout of an integrated circuit using auxiliary integrated circuit elements that can cope with either a decoupling capacitor or an antenna diode, by merely changing a wiring layer. <P>SOLUTION: An N-type diffusion region 22 is formed within a P-type substrate 20, while a P-type diffusion region 25 is formed inside an N-type well 23. On the N-type diffusion region 22 and the P-type diffusion region 25, a common cell is prearranged, where polysilicon layers 27, 28 are formed to intersect with each other via an insulating layer 26. When a decoupling capacitor, the N-type diffusion region 22 and the polysilicon layer 28 are to be connected to a grounding region 21 via a grounding wiring layer 29X, while the P-type diffusion region 25 and the polysilicon layer 27 are connected to a power supply region 24 via a power supply wiring layer 31X. When it is to be used as an antenna diode, the N-type diffusion region 22 and the P-type diffusion region 25 are connected to a gate region of a logic cell on the integrated circuit via a metal wiring layer 33 of the lowest layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated circuit layout method using an auxiliary integrated circuit element capable of supporting both a decoupling capacitor and an antenna diode in integrated circuit design.

  In a manufacturing process of a semiconductor integrated circuit that has been miniaturized, a phenomenon has occurred in which charges are accumulated on a wiring pattern in a semiconductor chip etching process or the like. When charges are accumulated in the wiring pattern during the manufacturing process, the charge flows into the element through the gate electrode of the transistor connected to the wiring pattern, resulting in a phenomenon that the performance deteriorates or the element itself is destroyed (antenna effect). appear. For this reason, measures are taken to connect a diode (antenna diode) for discharging charges accumulated during the manufacturing process between the wiring pattern predicted to increase the antenna effect and the power supply region or the ground region. Yes.

  Further, in a circuit that operates at a high speed, the influence of a voltage drop due to the resistance of the power supply wiring or the like is increased due to fluctuations in current supplied from the power supply to the circuit during operation. As a countermeasure, a decoupling capacitor using a gate capacitance of a MOS transistor is generally connected between the power supply wiring and the ground wiring.

FIG. 2 is a configuration diagram of a conventional decoupling capacitor and antenna diode.
As shown in FIG. 2A, the decoupling capacitor includes a ground region 2 in which P + impurities are diffused and an N-type diffusion layer 3 in which N + impurities are diffused on a P-type substrate 1, for example. A power source region 5 in which N + impurities are diffused and a P-type diffusion layer 6 in which P + impurities are diffused are provided in an N-type well 4 formed on the substrate 1. On the surface of the P-type substrate 1 on which the N-type diffusion layer 3 and the P-type diffusion layer 6 are formed, polysilicon layers 8a and 8b corresponding to the gate electrodes of the MOS transistors are provided via the insulating layer 7. Yes.

  Further, a ground wiring layer 9 is formed on the ground region 2 via an insulating layer 7, and the ground region 2 and the ground wiring layer 9 are electrically connected by a contact 10. Further, the polysilicon layer 8 a and the ground wiring layer 9 are also electrically connected by the contact 11.

  Similarly, a power supply wiring layer 12 is formed on the power supply region 5 via an insulating layer 7, and the power supply region 5 and the power supply wiring layer 12 are electrically connected by a contact 13. Further, the polysilicon layer 8 b and the power supply wiring layer 12 are also electrically connected by a contact 14.

  As a result, a capacitor composed of the P-type diffusion layer 6 and the polysilicon layer 8a in the N-type well 4 and a capacitor composed of the N-type diffusion layer 3 and the polysilicon layer 8b on the P-type substrate 1 are formed. And between the power supply wiring layers 12.

  On the other hand, as shown in FIG. 2B, the antenna diode has, for example, a ground region 2 in which P + impurities are diffused on an P-type substrate 1 and an N-type diffusion layer 3 in which N + impurities are diffused. The N-type well 4 formed on the substrate 1 has a power supply region 5 in which N + impurities are diffused. On the surface of the P-type substrate 1 on which the N-type diffusion layer 3 and the N-type well 4 are formed, a ground wiring layer 9, a power supply wiring layer 12, and a lowermost metal wiring layer 15 are interposed via an insulating layer 7. Is formed.

  The ground wiring layer 9 is connected to the ground region 2 through a contact 10, and the power supply wiring layer 12 is connected to the power supply region 5 through a contact 13. The lowermost metal wiring layer 15 is connected to the N-type diffusion layer 3 through a contact 16 and is connected to a gate that leads to a wiring pattern in which an antenna effect is assumed.

  As a result, a diode is formed between the P-type substrate 1 and the N-type diffusion layer 3, and the cathode side of this diode is connected through the lowermost metal wiring layer 15 to a gate that leads to a wiring pattern in which an antenna effect is assumed. become.

  Such shape structures of decoupling capacitors and antenna diodes are registered as a library, read from the library as necessary when designing an integrated circuit, and appropriately arranged.

JP 2006-303377 A

  In the above-mentioned Patent Document 1, in order to improve the frequency characteristics of the decoupling capacitor and suppress the reduction of the area efficiency of the decoupling capacitor arrangement, a capacitor having a large gate length and a small capacitor are mixed for a high-speed circuit. For low-speed circuits, a semiconductor device formed only with a capacitor having a long gate length is described.

  However, since the decoupling capacitors and the antenna diodes have different shape structures, it may be difficult to prepare necessary and sufficient decoupling capacitors and antenna diodes in advance in a semiconductor chip layout in which the proportion of logic circuit elements is large. is expected. For this reason, the simulation after the layout design may reveal the existence of a wiring pattern having a large antenna effect or a power supply wiring having a large power supply voltage drop.

  In such a case, it is necessary to perform wiring for a spare decoupling cell or antenna diode cell at a long distance, or to re-arrange the logic circuit element, decoupling cell, or antenna diode cell. When the wiring is changed to a spare cell at a long distance, there are problems that the wiring length becomes long and the wiring does not converge in a layout where the wiring is congested. Further, when re-arranging, there is a problem that the layout design man-hour is increased due to re-arrangement.

  The present invention provides an integrated circuit using an auxiliary integrated circuit element that can be used for both the decoupling capacitor and the antenna diode by changing the wiring layer by sharing the base structure of the decoupling capacitor and the antenna diode. The purpose is to provide a layout method.

  The integrated circuit layout method of the present invention includes a registration process for additionally registering a shared cell having a ground pattern that can be shared by a decoupling capacitor and an antenna diode in a library in which patterns of a plurality of logic cells performing a logic operation are registered. A design process for designing an integrated circuit that performs a desired operation by combining a plurality of logic cells registered in the library; an additional process for adding a decoupling capacitor and an antenna diode to the integrated circuit designed by the design process; Based on the integrated circuit to which the decoupling capacitor and the antenna diode are added, and the library, the logic cell and the common cell constituting the integrated circuit are arranged to perform wiring between the cells, and the shared cell is disposed in an unused area. Layout processing to be arranged and the integration obtained by the layout processing A verification process for verifying the characteristics of the path, and when a desired characteristic is not obtained by the verification process, a wiring change for the shared cell and an adjustment process for repeating the verification process are sequentially executed until the desired characteristic is obtained. It is characterized by that.

  Further, the base pattern of the shared cell is formed by diffusing a second conductivity type impurity in the first conductivity type semiconductor substrate and diffusing a high concentration first conductivity type impurity in the substrate. A first power source region; a second power source region formed by diffusing a high concentration second conductivity type impurity in the well; and a high concentration in the substrate between the first power source region and the second power source region. A second conductive type diffusion layer formed by diffusing the second conductive type impurity and a high concentration first conductive type impurity diffused into the well between the first power source region and the second power source region. A first conductive type diffusion layer formed, an insulating layer formed on the surface of the substrate and well, and a first poly layer formed so as to intersect the second conductive type diffusion layer via the insulating layer. Crossing the silicon layer and the first conductivity type diffusion layer through the insulating layer And a second polysilicon layer has been made.

  In the present invention, the decoupling capacitor added to stabilize the operation of the integrated circuit and the base pattern of the antenna diode added to prevent trouble during the manufacturing process are shared. Thus, when used as a decoupling capacitor, the second conductivity type diffusion layer and the second polysilicon layer are electrically connected to the first power source region via the first power source wiring layer, and the first The conductive diffusion layer and the first polysilicon layer are electrically connected to the second power supply region via the second power supply wiring layer. Further, when used as an antenna diode, one or both of the first conductivity type diffusion layer and the second conductivity type diffusion layer are connected to the gate region of the logic cell constituting the integrated circuit via the lowermost metal wiring layer. Connect to. Since these changes only require the wiring layer and the contact, the development time can be shortened as compared with the case where the layout is changed from the change of the logic cell arrangement. In addition, there is no need to extend the wiring from a spare decoupling capacitor or antenna diode disposed at a long distance, and the wiring can be simplified.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a configuration diagram of an auxiliary integrated circuit element showing an embodiment of the present invention, in which FIG. 1 (a) is a plan view, and FIG. 1 (b) is an XX line in FIG. 1 (a). FIG.

  This integrated circuit element is a shared cell that can be used for both the decoupling capacitor and the antenna diode only by changing the wiring layer by sharing the base pattern of the decoupling capacitor and the antenna diode. Although this integrated circuit element is not used as a logic cell like an inverter or an OR gate, it is registered in the library as an auxiliary shared cell, and is read from the library as needed when designing the integrated circuit. Thus, they are appropriately arranged on the layout pattern.

  This integrated circuit element has a ground region 21 in which a high concentration P + impurity is diffused on a P type substrate 20 and an N type diffusion layer 22 in which a high concentration N + impurity is diffused, and is formed on the P type substrate 1. The N-type well 23 has a power source region 24 in which N + impurities are diffused and a P-type diffusion layer 25 in which P + impurities are diffused. The ground region 21 and the power source region 24 are arranged in parallel to both ends of the integrated circuit element. The N type diffusion layer 22 is formed adjacent to the ground region 21 in parallel, and the P type diffusion layer 25 is formed adjacent to the power source region 24 in parallel.

  Polysilicon layers 27 and 28 are provided on the surfaces of the N-type diffusion layer 22 and the P-type diffusion layer 25 with an insulating layer 26 interposed therebetween. The polysilicon layer 27 extends between the ground region 21 and the power supply region 24 so as to intersect the N-type diffusion layer 22. The polysilicon layer 28 extends between the ground region 21 and the power supply region 24 so as to intersect with the P-type diffusion layer 25. However, the N-type diffusion layer 22 and the P-type diffusion layer 25 are not connected to the ground region 21 and the power source region 24. The N type diffusion layer 22, the P type diffusion layer 25, and the polysilicon layers 27 and 28 serve as a base pattern.

  Further, a ground wiring 29 is provided on the ground region 21 via an insulating layer 26, and the ground region 21 and the ground wiring 29 are electrically connected by a contact 30. Similarly, a power supply wiring 31 is provided on the power supply region 24 via an insulating layer 26, and the power supply region 24 and the power supply wiring 31 are electrically connected by a contact 32.

  This integrated circuit element can constitute an antenna diode or a decoupling capacitor by adding a wiring layer and a contact.

  3A and 3B are configuration diagrams of an antenna diode using the integrated circuit element of FIG. 1, in which FIG. 3A is a plan view, and FIG. 3B is along the YY line in FIG. It is sectional drawing of a part.

  This antenna diode has a lowermost metal wiring layer 33 formed on the insulating layer 26. One end of the lowermost metal wiring layer 33 extends to above the N-type diffusion layer 22 or the P-type diffusion layer 25, and is connected to the N-type diffusion layer 22 or the P-type diffusion layer 25 through the contact 34 at this one end. Has been. The other end of the lowermost metal wiring layer 33 is connected to the gate of a logic cell that is assumed to have an antenna effect (not shown).

  Thereby, an antenna diode is formed between the P-type substrate 20 and the N-type diffusion layer 22, and the cathode side of the antenna diode is connected to the gate where the antenna effect is assumed through the lowermost metal wiring layer 33. An antenna diode is formed between the N-type well 23 and the P-type diffusion layer 25, and the anode side of the antenna diode is connected through the lowermost metal wiring layer 33 to the gate where the antenna effect is assumed. Therefore, since these antenna diodes are connected in the opposite direction with respect to the power supply potential, there is no influence during actual operation. Further, during the manufacturing process, it acts as a diode for preventing electrostatic breakdown for discharging charges accumulated in the lowermost metal wiring layer 33 to the substrate side.

  4 is a configuration diagram of a decoupling capacitor using the integrated circuit element of FIG. 1. FIG. 4A is a plan view, and FIG. 4B is a ZZ line in FIG. It is sectional drawing of the part which follows.

  This decoupling capacitor has a ground wiring layer 29X extending from the ground wiring layer 29 to above the N-type diffusion layer 22 and the polysilicon layer 28. The ground wiring layer 29X, the N-type diffusion layer 22 and the polysilicon layer 28 is electrically connected by a contact 30X. Further, the decoupling capacitor has a power supply wiring layer 31X extending from the power supply wiring layer 31 to above the P-type diffusion layer 25 and the polysilicon layer 27. The power supply wiring layer 31X, the P-type diffusion layer 25, and the poly The silicon layer 27 is electrically connected by a contact 32X.

  Thus, a capacitor is formed by the N-type diffusion layer 22 and the polysilicon layer 27 intersecting with the N-type diffusion layer 22, and a capacitor is formed by the P-type diffusion layer 25 and the polysilicon layer 28 intersecting with the P-type diffusion layer 25. These capacitors are connected between the ground wiring layer 29 and the power supply wiring layer 31, respectively, and function as decoupling capacitors.

Next, an integrated circuit layout method using the integrated circuit element of FIG. 1 will be described.
First, the base pattern of the integrated circuit element of FIG. 1 is additionally registered as a shared cell of the decoupling capacitor and the antenna diode in a library in which patterns of a plurality of logic cells performing various logic operations are registered.

  Next, using the logic cells registered in the library, a circuit design for performing a desired logic operation of the target integrated circuit is performed. At this point, a decoupling capacitor for stabilizing the operation and an antenna diode for suppressing the antenna effect in the manufacturing process are added to a circuit composed of logic cells necessary for performing a desired logic operation.

  Based on the designed circuit and library, layout design is performed in which logic cells and shared cells constituting the integrated circuit are arranged and wiring between the cells is performed. At this time, as the decoupling capacitor and the antenna diode, the ground pattern of the shared cell is arranged without being distinguished on the layout. In addition, an unconnected shared cell is arranged in an unused area on the layout.

  Thereafter, a simulation is performed based on the designed layout, and it is confirmed whether or not desired characteristics with respect to the antenna effect and the power supply voltage drop are obtained. If the antenna effect is not sufficiently suppressed, the wiring is changed to use an unconnected shared cell as an antenna diode or to change a shared cell arranged as a decoupling capacitor to an antenna diode. If the power supply voltage drop is not sufficiently suppressed, an unconnected shared cell is used as a decoupling capacitor, or a shared cell arranged as an antenna diode is changed to a decoupling capacitor. This change does not change the arrangement of the cells themselves, but only changes the wiring between the cells.

  Then, the wiring change and the simulation are repeated until the desired characteristics are obtained, and the layout of the layout and wiring of the integrated circuit that finally satisfies the desired characteristics is completed. The layout change at this time is to allocate an unused shared cell to an antenna diode or a decoupling capacitor, and to replace the antenna diode and the decoupling capacitor. Here, the ground pattern of the antenna diode and the decoupling capacitor (N-type diffusion layer 22, P-type diffusion layer 25, and polysilicon layers 27 and 28) is the same as shown in FIG. Only the wiring layer (the ground wiring layer 29, the power supply wiring layer 31, and the lowermost metal wiring layer 33) and the contact are targeted.

  As described above, the integrated circuit element of this embodiment has a shared cell structure having a base pattern that can be used for both the decoupling capacitor and the antenna diode. As a result, if the desired performance cannot be confirmed by simulation or the like, spare integrated circuit elements can be assigned to decoupling capacitors or antenna diodes only by changing wiring layers and contacts, or antenna diodes and decoupling capacitors can be changed mutually. Therefore, development time can be shortened compared with the case where the layout is changed from the change of the logic cell arrangement. In addition, there is no need to extend the wiring from a spare decoupling capacitor or antenna diode disposed at a long distance, so that there is an advantage that the wiring can be simplified.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) Although an example using a P-type substrate has been shown, the present invention can be similarly applied to an N-type substrate.
(B) Performance evaluation of the designed layout is not limited to simulation, but can also be performed using a prototype.

It is a block diagram of the Example of this invention. It is a block diagram of the conventional decoupling capacitor and an antenna diode. It is a block diagram of the antenna diode which uses the integrated circuit element of FIG. It is a block diagram of a decoupling capacitor using the integrated circuit element of FIG.

Explanation of symbols

20 P-type substrate 21 Ground region 22 N-type diffusion layer 23 N-type well 24 Power supply region 25 P-type diffusion layer 26 Insulating layer 27, 28 Polysilicon layer 29, 29X Ground wiring layer 30, 30X, 32, 32X, 34 Contact 31 , 31X Power wiring layer 33 Lowermost metal wiring layer

Claims (4)

A registration process for additionally registering a shared cell having a ground pattern that can be shared by a decoupling capacitor and an antenna diode in a library in which patterns of a plurality of logic cells performing a logic operation are registered;
A design process for designing an integrated circuit that performs a desired operation by combining a plurality of logic cells registered in the library;
An additional process of adding a decoupling capacitor and an antenna diode to the integrated circuit designed in the design process;
Based on the integrated circuit to which the decoupling capacitor and the antenna diode are added, and the library, the logic cell and the common cell constituting the integrated circuit are arranged to perform wiring between the cells, and the shared cell is disposed in an unused area. Layout processing to place,
Verification processing for verifying the characteristics of the integrated circuit obtained by the layout processing;
When a desired characteristic is not obtained by the verification process, a wiring change for the shared cell and an adjustment process for repeating the verification process until the desired characteristic is obtained,
An integrated circuit layout method, which is sequentially executed. The base pattern of the shared cell is:
A well formed by diffusing a second conductivity type impurity in a substrate of a first conductivity type semiconductor;
A first power source region formed by diffusing a high-concentration first conductivity type impurity in the substrate;
A second power source region formed by diffusing a high-concentration second conductivity type impurity in the well;
A second conductivity type diffusion layer formed by diffusing a high concentration second conductivity type impurity in the substrate between the first power source region and the second power source region;
A first conductivity type diffusion layer formed by diffusing a high concentration first conductivity type impurity in the well between the first power source region and the second power source region;
An insulating layer formed on the surface of the substrate and well;
A first polysilicon layer formed to intersect the second conductivity type diffusion layer via the insulating layer;
A second polysilicon layer formed so as to intersect the first conductivity type diffusion layer via the insulating layer;
2. The integrated circuit layout method according to claim 1, further comprising: The decoupling capacitor is
The second conductivity type diffusion layer and the second polysilicon layer are electrically connected to the first power source region via a first power supply wiring layer, and the first conductivity type diffusion layer and the first polysilicon layer are electrically connected. The polysilicon layer is electrically connected to the second power supply region via the second power supply wiring layer,
The antenna diode is
One or both of the first conductivity type diffusion layer and the second conductivity type diffusion layer are configured to be connected to a gate region of a logic cell constituting the integrated circuit through a lowermost metal wiring. The integrated circuit layout method according to claim 2. The first conductivity type diffusion layer is provided adjacent to the first power supply region in parallel,
3. The integrated circuit layout method according to claim 2, wherein the second conductivity type diffusion layer is provided adjacent to and parallel to the second power supply region.

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