CN215527725U - Chip mechanism and bridge stack - Google Patents

Abstract

The utility model discloses a chip mechanism and a bridge stack, and relates to the technical field of rectifier bridges. The chip mechanism comprises an electrode assembly, a first insulating piece and a second insulating piece, wherein the electrode assembly comprises a first electrode layer and a second electrode layer, the first electrode layer is attached to the second electrode layer, the first insulating piece penetrates through the first electrode layer and extends into the second electrode layer, and the first insulating piece divides the first electrode layer into a first pole and a second pole which are independent of each other; the second insulating part is attached to the first insulating part and the first electrode layer, and an orthographic projection of the second insulating part towards the first insulating part covers the first insulating part. The utility model solves the technical problems of larger individual difference of the existing chip mechanism and poorer consistency after the existing chip mechanism is integrated and packaged into a bridge stack.

Description

Chip mechanism and bridge stack

Technical Field

The utility model relates to the technical field of rectifier bridges, in particular to a chip mechanism and a bridge stack.

Background

The bridge stack is a product formed by four rectifier silicon chips in bridge connection and externally packaged by insulating plastics and mainly used for rectifying and adjusting the current direction. The existing bridge stack has certain difference of electrical parameters due to individual difference of single chip mechanisms, and the consistency of the parameters of the bridge stack is poor after the bridge stack is integrated and packaged.

SUMMERY OF THE UTILITY MODEL

In view of this, the present invention provides a chip mechanism and a bridge stack, which are used to solve the technical problems of large individual difference of the existing chip mechanism and poor consistency after integrated and packaged into a bridge stack.

A chip mechanism comprises an electrode assembly, a first insulating piece and a second insulating piece, wherein the electrode assembly comprises a first electrode layer and a second electrode layer, the first electrode layer is attached to the second electrode layer, the first insulating piece penetrates through the first electrode layer and extends into the second electrode layer, and the first insulating piece divides the first electrode layer into a first pole and a second pole which are independent of each other; the second insulating part is attached to the first insulating part and the first electrode layer, and an orthographic projection of the second insulating part towards the first insulating part covers the first insulating part.

In some embodiments of the chip architecture, the first insulator comprises a first interposer and a second interposer, the first interposer being circumferentially disposed around and through the first electrode layer; one end of the second insert is fixedly connected to one side of the first insert, and the other end of the second insert is fixedly connected to the other side of the first insert so as to be matched with the first insert to divide the first electrode layer into the first pole and the second pole.

In some embodiments of the chip mechanism, the first pole and the second pole are the same size and shape.

In some embodiments of the chip architecture, the end face of the first insulator near the second insulator is flush with the surface of the first electrode layer away from the second electrode layer.

In some embodiments of the chip mechanism, the second insulating member has a protrusion disposed on a surface thereof opposite to the first insulating member, and the protrusion is embedded in the first insulating member.

In some embodiments of the chip mechanism, the chip mechanism further comprises a first conductive layer fixedly attached to the first pole and a second conductive layer fixedly attached to the second pole.

In some embodiments of the chip mechanism, the chip mechanism further comprises a third conductive layer fixedly attached to a surface of the second electrode layer remote from the first electrode layer.

In some embodiments of the chip mechanism, the chip mechanism further includes a first pin and a second pin, one end of the first pin is fixedly connected to the first conductive layer, and the other end of the first pin extends out of the first electrode layer; one end of the second pin is fixedly connected with the second conducting layer, and the other end of the second pin extends out of the first electrode layer.

In some embodiments of the chip mechanism, the chip mechanism further includes a third pin, one end of the third pin is fixedly connected to the third conductive layer, and the other end of the third pin extends out of the second electrode layer.

A bridge stack, comprising the chip mechanisms in the above embodiments, wherein the number of the chip mechanisms is two, and the chip mechanisms are respectively a first chip and a second chip, the first electrode layer in the first chip is a positive electrode layer, and the second electrode layer is a negative electrode layer; the first electrode layer in the second chip is a negative electrode layer, and the second electrode layer is a positive electrode layer; the positive electrode layer in the first chip is arranged opposite to the negative electrode layer in the second chip.

The embodiment of the utility model has the following beneficial effects:

the chip mechanism is applied to the bridge stack, and has the effects of good consistency and high chip reliability, in particular, the chip mechanism comprises an electrode assembly, a first insulating part and a second insulating part, wherein the electrode assembly comprises a first electrode layer and a second electrode layer, the first electrode layer and the second electrode layer can be positive and negative electrodes respectively, the first insulating part penetrates through the first electrode layer and extends into the second electrode layer, the first insulating part is used for dividing the first electrode layer into two mutually independent first electrodes and second electrodes, so that the conduction between the first electrodes and the second electrodes is avoided, the second insulating part is attached to the first insulating part, the first electrodes and the second electrodes can be further insulated, the passivation effect is achieved, and the second insulating part is attached to the first insulating part and the first electrode layer in the subsequent chip processing procedures, such as a sintering procedure, and the orthographic projection of the second insulating part facing the first insulating part covers the first insulating part, so that the insulating failure caused by the shrinkage and damage of the first insulating part can be avoided, the yield and the reliability of the chip mechanism are improved, and the technical problems of large individual difference and poor consistency after the integration and packaging of the conventional chip mechanism into a bridge stack are solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a partial structure of a chip mechanism in one embodiment;

FIG. 2 is a cross-sectional schematic cross-sectional view of a portion A-A of the chip mechanism shown in FIG. 1;

FIG. 3 is a schematic diagram showing a partial structure of a chip mechanism in one embodiment;

FIG. 4 is a schematic diagram showing a partial structure of a chip mechanism in one embodiment;

FIG. 5 is a schematic diagram of a bridge stack assembly of two chip mechanisms in one embodiment.

Wherein: 1. a first electrode layer; 111. a first pole; 112. a second pole; 2. a second electrode layer; 21. an anion layer; 22. a positive ion layer; 3. a first insulating member; 31. a first insert; 32. a second insert; 4. A second insulating member; 41. a protrusion; 5. a first conductive layer; 6. a second conductive layer; 7. a first pin; 8. a second pin; 9. a third pin; 100. and (7) solder paste.

Detailed Description

To facilitate an understanding of the utility model, the utility model will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The existing bridge stack has certain difference of electrical parameters due to individual difference of single chip mechanisms, and the consistency of the parameters of the bridge stack is poor after the bridge stack is integrated and packaged.

As shown in fig. 1-2, in an embodiment of a chip mechanism, the chip mechanism includes an electrode assembly, a first insulating member 3 and a second insulating member 4, the electrode assembly includes a first electrode layer 1 and a second electrode layer 2, the first electrode layer 1 is attached to the second electrode layer 2, the first insulating member 3 penetrates through the first electrode layer 1 and extends into the second electrode layer 2, and the first insulating member 3 is used for dividing the first electrode layer 1 into a first pole 111 and a second pole 112 which are independent of each other; the second insulating member 4 is attached to the first insulating member 3 and the first electrode layer 1, and an orthogonal projection of the second insulating member 4 toward the first insulating member 3 covers the first insulating member 3.

In this embodiment, the first electrode layer 1 is divided by the first insulating member 3 to form two independent first and second poles 111 and 112, the first and second poles 111 and 112 are divided by the first insulating member 3, thereby preventing the first pole 111 and the second pole 112 from being conducted, and then the second insulating member 4 is attached on the first insulating member 3, so that the first pole 111 and the second pole 112 can be further insulated, thereby achieving the passivation effect, such as a sintering process, to avoid insulation failure caused by shrinkage and damage of the first insulating member 3, the second insulating member 3 can extend into the gap between the first insulating member 3 and the first electrode layer 1 and the second electrode layer 2, therefore, the yield and the reliability of the chip mechanism are improved, and the technical problems that the existing chip mechanism is large in individual difference and poor in consistency after being integrated and packaged into a bridge stack are solved.

In one embodiment of the chip mechanism, the first insulating member 3 includes a first insert 31 and a second insert 32, the first insert 31 is circumferentially disposed around and penetrates the first electrode layer 1 along the first face 11; the second insert 32 has one end fixedly connected to one side of the first insert 31 and the other end fixedly connected to the other side of the first insert 31 to cooperate with the first insert 31 to divide the first electrode layer 1 into the first pole 111 and the second pole 112. The first pole 111 is the same size as the second pole 112.

Specifically, in the present embodiment, the first electrode layer 1 and the second electrode layer 2 may have a rectangular plate structure, the first insert 31 has a rectangular ring structure, and four corners of the first insulating member 3 are rounded to enable smooth transition and reduce burrs. The first electrode layer 1 can be divided into an inner ring area located in the first insert 31 by the first insert 31, and the first electrode layer 1 in the inner ring can be divided into a first pole 111 and a second pole 112 by the second insulating member 4, preferably, the second insulating member 4 is a rectangular rod-shaped structure, and both ends of the second insulating member 4 are respectively fixedly connected to the middle points of the two opposite long sides of the first insulating member 3, so that the first pole 111 and the second pole 112 which are equal in size can be divided.

The chip mechanism may be a diode silicon chip, the first electrode layer 1 and the second electrode layer 2 are a P-pole layer and an N-pole layer, as shown in fig. 2, specifically, the first electrode layer 1 is a P-pole layer, the second electrode layer 2 is an N-pole layer, wherein the N-pole layer is further divided into a negative ion layer 21 and a positive ion layer 22, i.e., an N-layer and an N + layer, and a line between the negative ion layer 21 and the positive ion layer 22 does not actually exist, which is a separation line for distinguishing the N-pole layer. In another chip structure, the first electrode layer 1 is an N-pole layer, the second electrode layer 2 is a P-pole layer, and the first insulator 3 can be inserted from the second electrode layer 2 and extend into the second electrode layer 2, so it can be understood that two different chip structures can be formed by inserting the first insulator 3 from the P-pole layer and the N-pole layer, and the application thereof will be described later.

In an embodiment of the chip structure, the end surface of the first insulating member 3 close to the second insulating member 4 is flush with the surface of the first electrode layer 1 far from the second electrode layer 2.

In this embodiment, the end surface of the first insulating member 3 close to the second insulating member 4 is flush with the surface of the first electrode layer 1 far from the second electrode layer 2, so that the second insulating member 4 can be conveniently installed, and meanwhile, the situation that the whole first insulating member 3 protrudes out of the first electrode layer 1 too much to be convenient for subsequent packaging can be avoided. Specifically, the first insulating member 3 is made of glass, and is hard for passivation protection.

In an embodiment of the chip mechanism, the second insulating member 4 is provided with a protrusion 41 on a surface opposite to the first insulating member 3, and the protrusion 41 is embedded in the first insulating member 3.

In this embodiment, specifically, the second insulating member 4 may be a polyimide composite film, the body of the second insulating member 4 is a planar thin film structure, and is attached to the end surfaces of the first interposer 31 and the second interposer 32 away from the second electrode layer 2, and through holes are formed at positions corresponding to the first pole 111 and the second pole 112, so as to expose the first pole 111 and the second pole 112. The second insulating member 4 can be better fixed and positioned by providing the protrusion 41, and the position of the second insulating member 4 is prevented from being shifted. In addition, the width of the second insulating part 4 body is larger than that of the corresponding position of the first insulating part 3, so that the second insulating part 4 body can completely cover the first insulating part 3, in the subsequent sintering process, the first insulating part 3 is made of glass, the risk of shrinkage exists, the second insulating part 4 is additionally arranged, the risk caused by glass shrinkage is reduced, and the reliability of the chip mechanism is improved.

In one embodiment of the chip mechanism, as shown in fig. 3-4, the chip mechanism further comprises a first conductive layer 5 and a second conductive layer 6, the first conductive layer 5 being fixedly attached to the first pole 111 and the second conductive layer 6 being fixedly attached to the second pole 112. The chip mechanism further comprises a first pin 7 and a second pin 8, one end of the first pin 7 is fixedly connected with the first conducting layer 5, and the other end of the first pin extends out of the first conducting layer 1; one end of the second pin 8 is fixedly connected to the second conductive layer 6, and the other end extends out of the first conductive layer 1.

In this embodiment, the first conductive layer 5 and the second conductive layer 6 may be a sheet structure made of conductive metal, preferably copper, which has good heat dissipation property, and may be respectively fixed to the first pole 111 and the second pole 112 by soldering, the first pole 111 and the second pole 112 are completely divided in the above embodiment, and two P-pole surfaces can be formed, so as to realize that one chip mechanism has two PN junctions, and then the first pin 7 and the second pin 8 are respectively and fixedly connected, the first pin 7 and the second pin 8 may be respectively soldered to the first pole 111 and the second pole 112 by solder paste 100, and the electrodes are led out of the first conductive layer 1, so as to facilitate subsequent packaging, and only the pins can be exposed after packaging, and the chip mechanism is connected to a circuit by the pins for use.

In an embodiment of the chip arrangement, as shown in fig. 3-4, the chip arrangement further comprises a third conductive layer fixedly attached to the surface of the second electrode layer 2 remote from the first electrode layer 1. The chip mechanism further comprises a third pin 9, one end of the third pin 9 is fixedly connected to the third conducting layer, and the other end of the third pin extends out of the third conducting layer.

In the present embodiment, as in the above embodiments, the electrode of the second electrode layer 2 can be led out through the third conductive layer and the third pin 9, so as to facilitate the subsequent packaging and connection into a circuit. The third conductive layer may be a nickel plating layer covering the second surface 23, and the nickel plating layer may also be adhered between the first electrode layer 1 and the first conductive layer 5 and the second conductive layer 6, so that the conductive efficiency can be improved.

The utility model also discloses a bridge stack, which is shown in a combined figure 1-5 and comprises the chip mechanism in the embodiment. The number of the chip mechanisms is two, the chip mechanisms are respectively a first chip and a second chip, a first electrode layer 1 in the first chip is an anode layer, and a second electrode layer 2 is a cathode layer; the first electrode layer 1 in the second chip is a negative electrode layer, and the second electrode layer 2 is a positive electrode layer; the positive electrode layer in the first chip is arranged opposite to the negative electrode layer of the second chip.

In the above embodiment, two chip mechanisms are disclosed, in which the first insulating member 3 is inserted into the P-pole layer and the N-pole layer, and the two chip mechanisms inserted into the positive and negative pole layers are oppositely buckled to form a bridge stack, and since the two chip mechanisms share the N + layer and the P-pole layer, the single-phase rectification function can be realized by using only two silicon chips of the diode, so as to improve the utilization rate of the silicon material; and because the charge motion sharing the same diffusion region completes the unidirectional rectification, the parameter consistency of the single-term rectifier bridge stack is greatly improved.

The bridge stack combined by applying the chip mechanisms in the above embodiments has the advantages of miniaturization and high reliability.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A chip mechanism, characterized in that: the electrode assembly comprises a first electrode layer and a second electrode layer, the first electrode layer is attached to the second electrode layer, the first insulating piece penetrates through the first electrode layer and extends into the second electrode layer, and the first insulating piece divides the first electrode layer into a first pole and a second pole which are independent of each other; the second insulating part is attached to the first insulating part and the first electrode layer, and an orthographic projection of the second insulating part towards the first insulating part covers the first insulating part.

2. The chip mechanism of claim 1, wherein: the first insulating piece comprises a first inserting piece and a second inserting piece, and the first inserting piece is arranged on the first electrode layer in a circumferential mode and penetrates through the first electrode layer; one end of the second insert is fixedly connected to one side of the first insert, and the other end of the second insert is fixedly connected to the other side of the first insert so as to be matched with the first insert to divide the first electrode layer into the first pole and the second pole.

3. The chip mechanism of claim 2, wherein: the first pole and the second pole are the same in shape and size.

4. The chip mechanism of claim 3, wherein: the end face of the first insulating part, which is close to the second insulating part, is flush with the surface of the first electrode layer, which is far away from the second electrode layer.

5. The chip mechanism according to any one of claims 1 to 4, wherein: the second insulating part is provided with a bulge corresponding to the surface of the first insulating part, and the bulge is embedded in the first insulating part.

6. The chip mechanism of claim 1, wherein: the chip mechanism further includes a first conductive layer fixedly attached to the first pole and a second conductive layer fixedly attached to the second pole.

7. The chip mechanism of claim 6, wherein: the chip mechanism further comprises a third conducting layer, and the third conducting layer is fixedly attached to the surface, far away from the first electrode layer, of the second electrode layer.

8. The chip mechanism of claim 7, wherein: the chip mechanism further comprises a first pin and a second pin, wherein one end of the first pin is fixedly connected with the first conducting layer, and the other end of the first pin extends out of the first electrode layer; one end of the second pin is fixedly connected with the second conducting layer, and the other end of the second pin extends out of the first electrode layer.

9. The chip mechanism of claim 8, wherein: the chip mechanism further comprises a third pin, one end of the third pin is fixedly connected with the third conducting layer, and the other end of the third pin extends out of the second electrode layer.

10. A bridge stack, characterized by: comprising the chip set according to any one of claims 1 to 9, the number of said chip sets being two, respectively a first chip and a second chip, said first electrode layer in said first chip being a positive electrode layer and said second electrode layer being a negative electrode layer; the first electrode layer in the second chip is a negative electrode layer, and the second electrode layer is a positive electrode layer; the positive electrode layer in the first chip is arranged opposite to the negative electrode layer in the second chip.

Images