CN215496705U

CN215496705U - Overcurrent protection semiconductor MOS device

Info

Publication number: CN215496705U
Application number: CN202121807307.4U
Authority: CN
Inventors: 田伟; 廖兵
Original assignee: Suzhou Dajing Semiconductor Co ltd
Current assignee: Suzhou Dajing Semiconductor Co ltd
Priority date: 2021-08-04
Filing date: 2021-08-04
Publication date: 2022-01-11
Anticipated expiration: 2031-08-04

Abstract

The utility model discloses an overcurrent protection semiconductor MOS device, wherein an MOS chip is positioned on the upper surface of a heat-conducting ceramic wafer, the lower surface of the heat-conducting ceramic wafer is provided with a boss, the boss of the heat-conducting ceramic wafer is embedded into a hollow-out area of a copper support frame, and an epoxy packaging body is coated on the MOS chip, the copper support frame and the welding ends of a grid pin, a drain pin and a source pin respectively; at least one of the drain lead and the source lead has a low melting point metal wire in a region between the bonding end and the lead end and within the epoxy package, the low melting point metal wire having a width less than a width of the corresponding lead. The overcurrent protection semiconductor MOS device can block current in time when an MOS tube has overlarge current while improving the heat dissipation of the device, thereby improving the overall structural strength and stability of the device.

Description

Overcurrent protection semiconductor MOS device

Technical Field

The utility model relates to the technical field of semiconductor devices, in particular to an MOS device.

Background

The MOS transistor is a metal-oxide semiconductor field effect transistor, referred to as a mosfet for short, and has high input impedance, low noise, and good thermal stability, and thus is widely used in power supplies, driving circuits, and switching circuits. With the development of the market, the requirements on the safety and the reliability of the MOS are higher and higher.

Disclosure of Invention

The utility model aims to provide an over-current protection semiconductor MOS device, which can block current in time when an MOS tube has overlarge current while improving the heat dissipation of the device, thereby improving the overall structural strength and stability of the device.

In order to achieve the purpose, the utility model adopts the technical scheme that: an overcurrent protection semiconductor MOS device comprising: the MOS chip comprises an MOS chip, a copper support frame, a grid pin, a drain pin and a source pin, wherein a grid region, a drain region and a source region which are positioned on the upper surface of the MOS chip are electrically connected to respective welding ends of the grid pin, the drain pin and the source pin through a first metal wire, a second metal wire and a third metal wire respectively, and a hollow-out area is arranged on the copper support frame;

the MOS chip is positioned on the upper surface of a heat-conducting ceramic wafer, the lower surface of the heat-conducting ceramic wafer is provided with a boss, the boss of the heat-conducting ceramic wafer is embedded into the hollow area of the copper support frame, and an epoxy packaging body is coated on the MOS chip, the copper support frame and the welding ends of the grid pin, the drain pin and the source pin;

at least one of the drain lead and the source lead has a low melting point metal wire in a region between the bonding end and the lead end and within the epoxy package, the width of the low melting point metal wire being smaller than the corresponding lead width.

The further improved scheme in the technical scheme is as follows:

1. in the above scheme, the low-melting-point metal wire is a tin metal wire, a bismuth metal wire or an indium metal wire.

2. In the scheme, the shape of the hollow-out area is square.

3. In the scheme, the thickness of the heat conduction ceramic wafer is 1-2 mm.

4. In the scheme, the thickness of the boss is 1-2 mm.

Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages:

1. according to the MOS power device, at least one of the drain electrode pin and the source electrode pin is provided with the low-melting-point metal wire in the area between the welding end and the pin end and in the epoxy packaging body, the width of the low-melting-point metal wire is smaller than that of the corresponding pin, and when an over-high current occurs to the MOS tube, the low-melting-point metal wire on the drain electrode pin or the source electrode pin is fused to block the current, so that the MOS tube is prevented from exploding under the over-high current, and the safety of the MOS device is greatly improved.

2. According to the MOS power device, the MOS chip is positioned on the upper surface of the heat-conducting ceramic wafer, the lower surface of the heat-conducting ceramic wafer is provided with the boss, and the boss of the heat-conducting ceramic wafer is embedded into the hollow area of the copper support frame, so that the overall structural strength and stability of the device are improved, heat can be timely radiated, the radiating performance is improved, and the service life of the device is prolonged.

Drawings

FIG. 1 is a schematic structural diagram of an overcurrent protection semiconductor MOS device according to the utility model;

FIG. 2 is a schematic view of the cross-sectional structure A-A of FIG. 1;

FIG. 3 is a rear view of the structure of FIG. 1;

fig. 4 is a schematic diagram of the internal structure of the overcurrent protection semiconductor MOS device according to the present invention.

In the above drawings: 1. an MOS chip; 101. a gate region; 102. a drain region; 103. a source region; 2. a copper support frame; 3. a gate pin; 4. a drain lead; 5. a source lead; 61. a first metal line; 62. a second metal line; 63. a third metal line; 7. a hollow-out area; 8. a heat-conducting ceramic sheet; 9. an epoxy package; 10. a low melting point metal wire; 11. and (4) a boss.

Detailed Description

In the description of this patent, it is noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The meaning of the above terms in this patent may be specifically understood by those of ordinary skill in the art.

The utility model is further described below with reference to the following examples:

example 1: an overcurrent protection semiconductor MOS device comprising: the MOS chip comprises an MOS chip 1, a copper support frame 2, a gate lead 3, a drain lead 4 and a source lead 5, wherein a gate region 101, a drain region 102 and a source region 103 which are positioned on the upper surface of the MOS chip 1 are electrically connected to respective welding ends of the gate lead 3, the drain lead 4 and the source lead 5 through a first metal wire 61, a second metal wire 62 and a third metal wire 63 respectively, and a hollow-out region 7 is arranged on the copper support frame 2;

the MOS chip 1 is positioned on the upper surface of a heat-conducting ceramic wafer 8, the lower surface of the heat-conducting ceramic wafer 8 is provided with a raised platform 11, the raised platform 11 of the heat-conducting ceramic wafer 8 is embedded into the hollow-out area 7 of the copper support frame 2, and an epoxy packaging body 9 is coated on the welding ends of the MOS chip 1, the copper support frame 2, the grid pin 3, the drain pin 4 and the source pin 5;

at least one of the drain lead 4 and the source lead 5 has a low melting point metal wire 10 in a region between the bonding end and the lead end and within the epoxy package 9, and the width of the low melting point metal wire 10 is smaller than the corresponding lead width.

The low melting point metal wire 7 is a bismuth metal wire.

The hollow-out area 7 is square.

The thickness of the heat-conducting ceramic wafer 8 is 1.5mm, and the thickness of the boss 11 is 1.4 mm.

Example 2: an overcurrent protection semiconductor MOS device comprising: the MOS chip comprises an MOS chip 1, a copper support frame 2, a gate lead 3, a drain lead 4 and a source lead 5, wherein a gate region 101, a drain region 102 and a source region 103 which are positioned on the upper surface of the MOS chip 1 are electrically connected to respective welding ends of the gate lead 3, the drain lead 4 and the source lead 5 through a first metal wire 61, a second metal wire 62 and a third metal wire 63 respectively, and a hollow-out region 7 is arranged on the copper support frame 2;

The low melting point metal wire 7 is a tin metal wire.

The thickness of the heat-conducting ceramic wafer 8 is 1.8mm, and the thickness of the boss 11 is 1.2 mm.

When the overcurrent protection semiconductor MOS device is adopted, at least one pin of a drain electrode pin and a source electrode pin of the overcurrent protection semiconductor MOS device is provided with a low-melting-point metal wire in a region which is positioned between a welding end and a pin end and in an epoxy packaging body, the width of the low-melting-point metal wire is smaller than the width of the corresponding pin, and when an over-large current occurs to the MOS tube, the low-melting-point metal wire positioned on the drain electrode pin or the source electrode pin is fused to block the current, so that the MOS tube is prevented from being exploded under the over-large current, and the safety of the MOS device is greatly improved;

in addition, the MOS chip is positioned on the upper surface of a heat-conducting ceramic wafer, the lower surface of the heat-conducting ceramic wafer is provided with a boss, and the boss of the heat-conducting ceramic wafer is embedded into the hollow area of the copper support frame, so that the overall structural strength and stability of the device are improved, heat can be timely radiated, the radiating performance is improved, and the service life of the device is prolonged.

The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. An overcurrent protection semiconductor MOS device, characterized in that: the method comprises the following steps: the MOS chip comprises an MOS chip (1), a copper support frame (2), a gate pin (3), a drain pin (4) and a source pin (5), wherein a gate region (101), a drain region (102) and a source region (103) which are positioned on the upper surface of the MOS chip (1) are electrically connected to respective welding ends of the gate pin (3), the drain pin (4) and the source pin (5) through a first metal wire (61), a second metal wire (62) and a third metal wire (63), and a hollow-out region (7) is formed in the copper support frame (2);

the MOS chip (1) is positioned on the upper surface of a heat-conducting ceramic wafer (8), the lower surface of the heat-conducting ceramic wafer (8) is provided with a raised platform (11), the raised platform (11) of the heat-conducting ceramic wafer (8) is embedded into the hollow-out area (7) of the copper support frame (2), and an epoxy packaging body (9) is coated on the welding ends of the MOS chip (1), the copper support frame (2), the grid pin (3), the drain pin (4) and the source pin (5);

at least one of the drain lead (4) and the source lead (5) has a low melting point metal wire (10) in a region between the bonding end and the lead end and within the epoxy package (9), and the width of the low melting point metal wire (10) is smaller than the corresponding lead width.

2. The overcurrent protection semiconductor MOS device as set forth in claim 1, wherein: the low-melting-point metal wire (10) is a tin metal wire, a bismuth metal wire or an indium metal wire.

3. The overcurrent protection semiconductor MOS device as set forth in claim 1, wherein: the shape of the hollow-out area (7) is square.

4. The overcurrent protection semiconductor MOS device as set forth in claim 1, wherein: the thickness of the heat conduction ceramic wafer (8) is 1-2 mm.

5. The overcurrent protection semiconductor MOS device as set forth in claim 1, wherein: the thickness of the boss (11) is 1-2 mm.