CN215265523U - Drive circuit of Demux display screen - Google Patents
Drive circuit of Demux display screen Download PDFInfo
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- CN215265523U CN215265523U CN202120416826.1U CN202120416826U CN215265523U CN 215265523 U CN215265523 U CN 215265523U CN 202120416826 U CN202120416826 U CN 202120416826U CN 215265523 U CN215265523 U CN 215265523U
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Abstract
The utility model relates to a Demux display screen drive circuit technical field, in particular to Demux display screen drive circuit, including transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8 and transistor T9, transistor T1's grid connects first Demux control line, transistor T2's grid connects third Demux control line, transistor T4's grid connects second Demux control line, transistor T5's grid connects fourth Demux control line, transistor T7's grid connects third Demux control line, transistor T8's grid connects first Demux control line, can improve the level quasi-position of Demux display screen drive circuit's control end like this, improve Demux display screen drive circuit's drive power, thereby solve the picture that causes because of Demux drive power decline and show the inequality.
Description
Technical Field
The utility model relates to a Demux display screen drive circuit technical field, in particular to Demux display screen drive circuit.
Background
The display screen adopting the Demux (demultiplexing) driving technology has the characteristic of narrow frame, so the display screen is widely applied. However, as the usage time increases, the driving force of the Demux circuit decreases, causing display unevenness, thereby affecting the display effect.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve is: the drive circuit of the Demux display screen is used for improving the drive force of the Demux circuit and solving the problem of poor display caused by reduction of the drive force of the Demux, so that the service life of a product is prolonged.
In order to solve the technical problem, the utility model discloses a technical scheme be:
a Demux display screen driving circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor Cr, a capacitor Cg and a capacitor Cb, wherein a gate of the transistor T1 is connected with a first Demux control line, a source of the transistor T1 is respectively and electrically connected with one end of the capacitor Cr, a drain of the transistor T2 and a gate of the transistor T3, the other end of the capacitor Cr is connected with a second Demux control line, a gate of the transistor T2 is connected with a third Demux control line, a gate of the transistor T4 is connected with the second Demux control line, a source of the transistor T4 is respectively and electrically connected with one end of the capacitor Cg, a drain of the transistor T5 and a gate of the transistor T6, a gate of the transistor T5 is connected with a fourth Demux control line, the other end of the capacitor Cg 2, and the third gate of the transistor Cg 7 is connected with the third Demux control line, the source of the transistor T7 is electrically connected to one end of the capacitor Cb, the drain of the transistor T8, and the gate of the transistor T9, respectively, the other end of the capacitor Cb is connected to a fourth Demux control line, the gate of the transistor T8 is connected to the first Demux control line, the source of the transistor T3 is electrically connected to the source of the transistor T6 and the source of the transistor T9, respectively, and the source of the transistor T3 is connected to the source of the transistor T6 and the source of the transistor T9, respectively, through the same source line.
The beneficial effects of the utility model reside in that:
the grid of the transistor T1 is connected with the first Demux control line, the other end of the capacitor Cr is connected with the second Demux control line, the grid of the transistor T2 is connected with the third Demux control line, the grid of the transistor T4 is connected with the second Demux control line, the grid of the transistor T5 is connected with the fourth Demux control line, the other end of the capacitor Cg is connected with the third Demux control line, the grid of the transistor T7 is connected with the third Demux control line, the other end of the capacitor Cb is connected with the fourth Demux control line, and the grid of the transistor T8 is connected with the first Demux control line.
Drawings
Fig. 1 is a schematic structural diagram of a Demux display screen driving circuit according to the present invention;
fig. 2 is a timing waveform diagram of a drive circuit of a Demux display screen according to the present invention.
Detailed Description
In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, the present invention provides a technical solution:
a Demux display screen driving circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor Cr, a capacitor Cg and a capacitor Cb, wherein a gate of the transistor T1 is connected with a first Demux control line, a source of the transistor T1 is respectively and electrically connected with one end of the capacitor Cr, a drain of the transistor T2 and a gate of the transistor T3, the other end of the capacitor Cr is connected with a second Demux control line, a gate of the transistor T2 is connected with a third Demux control line, a gate of the transistor T4 is connected with the second Demux control line, a source of the transistor T4 is respectively and electrically connected with one end of the capacitor Cg, a drain of the transistor T5 and a gate of the transistor T6, a gate of the transistor T5 is connected with a fourth Demux control line, the other end of the capacitor Cg 2, and the third gate of the transistor Cg 7 is connected with the third Demux control line, the source of the transistor T7 is electrically connected to one end of the capacitor Cb, the drain of the transistor T8, and the gate of the transistor T9, respectively, the other end of the capacitor Cb is connected to a fourth Demux control line, the gate of the transistor T8 is connected to the first Demux control line, the source of the transistor T3 is electrically connected to the source of the transistor T6 and the source of the transistor T9, respectively, and the source of the transistor T3 is connected to the source of the transistor T6 and the source of the transistor T9, respectively, through the same source line.
From the above description, the beneficial effects of the present invention are:
the grid of the transistor T1 is connected with the first Demux control line, the other end of the capacitor Cr is connected with the second Demux control line, the grid of the transistor T2 is connected with the third Demux control line, the grid of the transistor T4 is connected with the second Demux control line, the grid of the transistor T5 is connected with the fourth Demux control line, the other end of the capacitor Cg is connected with the third Demux control line, the grid of the transistor T7 is connected with the third Demux control line, the other end of the capacitor Cb is connected with the fourth Demux control line, and the grid of the transistor T8 is connected with the first Demux control line.
Further, the drain of the transistor T3 is connected to the first data trace, the drain of the transistor T6 is connected to the second data trace, and the drain of the transistor T9 is connected to the third data trace.
Further, the drain of the transistor T1, the drain of the transistor T4 and the drain of the transistor T7 are all connected to the positive electrode of the power supply.
Further, the source electrode of the transistor T2, the source electrode of the transistor T5 and the source electrode of the transistor T8 are all connected to the negative pole of the power supply.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T9 are all N-channel MOS transistors.
From the above description, the driving force of the Demux circuit can be further improved by the N-channel MOS transistor.
Referring to fig. 1 and fig. 2, a first embodiment of the present invention is:
referring to fig. 1, a Demux display screen driving circuit includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor Cr, a capacitor Cg, and a capacitor Cb, wherein a gate of the transistor T1 is connected to a first Demux control line, a source of the transistor T1 is electrically connected to one end of the capacitor Cr, a drain of the transistor T2, and a gate of the transistor T3, another end of the capacitor Cr is connected to a second Demux control line, a gate of the transistor T2 is connected to a third Demux control line, a gate of the transistor T4 is connected to the second Demux control line, a source of the transistor T4 is electrically connected to one end of the capacitor Cg, a drain of the transistor T5, and a gate of the transistor T6, a gate of the transistor T5 is connected to a fourth Demux control line, another end of the capacitor Cg is connected to the third Demux control line, and a gate of the transistor T7, the source of the transistor T7 is electrically connected to one end of the capacitor Cb, the drain of the transistor T8, and the gate of the transistor T9, respectively, the other end of the capacitor Cb is connected to a fourth Demux control line, the gate of the transistor T8 is connected to the first Demux control line, the source of the transistor T3 is electrically connected to the source of the transistor T6 and the source of the transistor T9, respectively, and the source of the transistor T3 is connected to the source of the transistor T6 and the source of the transistor T9, respectively, through the same source line.
The drain of the transistor T3 is connected to the first data trace, the drain of the transistor T6 is connected to the second data trace, and the drain of the transistor T9 is connected to the third data trace.
The drain electrode of the transistor T1, the drain electrode of the transistor T4 and the drain electrode of the transistor T7 are all connected with the anode of the power supply.
The source electrode of the transistor T2, the source electrode of the transistor T5 and the source electrode of the transistor T8 are all connected with the cathode of the power supply.
The transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8 and the transistor T9 are all N-channel MOS transistors.
The drive circuit of the Demux display screen designed by the scheme comprises 9 TFTs (Thin Film transistors) and 3 capacitors, and the voltages of VGH and VGL are respectively high level and low level. There are four sets of control line signals, Demux _ K (i.e., the first Demux control line), Demux _ R (i.e., the second Demux control line), Demux _ G (i.e., the third Demux control line), and Demux _ B (i.e., the fourth Demux control line), and the timing relationships are detailed in fig. 2. In this embodiment, only the signal of the nth Sn is described, and the rest of the source lines (gate lines) are the same.
The drive process of the drive circuit of the Demux display screen is as follows:
(Note: the following Demux (n-1), Demux (n), and Demux (n +1) represent only the timing relationships of the Demux waveforms, and in fact their signals originate from the same Demux control line.)
At time T1, Demux _ k (n) is at high level, at which time transistor T1 is in on state, the voltage at R1 is VGH, and transistor T3 is in on state; the transistor T8 is in an on state, and the voltage at the point B1 is VGL;
at time T2, Demux _ R (n) is high, and both Demux _ K and Demux _ G are turned off, so that the potential at point R1 rises due to the coupling of the capacitor Cr at point R1, the driving force of the transistor T3 rises, and D (n-1) transmits data through the transistor T3; meanwhile, since Demux _ r (n) is at a high level, the transistor T4 is in a conducting state, the voltage at the point G1 is VGH, and the transistor T6 is in a conducting state;
at time T3, Demux _ G (n) is high, and since Demux _ B and Demux _ R are both off, the potential at point G1 rises due to the coupling effect of capacitor Cg at point G1, the driving force of transistor T6 rises, and d (n) data is transmitted through transistor T6; meanwhile, since Demux _ g (n) is at a high level, the transistor T2 is turned on, and the potential at the point R1 is pulled down to VGL; the transistor T7 is in an on state, the potential at the point B1 is VGH, and the transistor T9 is in an on state;
at time T4, Demux _ B (n) is high, and since Demux _ K and Demux _ G are both off, the potential at point B1 rises due to the coupling of capacitor Cb at point B1, the driving force of transistor T9 rises, and D (n +1) transmits data through transistor T9; meanwhile, since Demux _ b (n) is at a high level, the transistor T5 is turned on, and the potential at the point G1 is pulled down to VGL;
at time T5, Demux _ K (n +1) is high, at which time transistor T1 is turned on, the voltage at R1 is VGH, and transistor T3 is turned on; the transistor T8 is in an on state, and the voltage at the point B1 is VGL; (same as at time T1);
the state at time T6 is the same as the state at time T2.
It is worth noting that when Demux _ K is turned on, the gate wire is in a closed state and data transmission data is 0V, so as to optimize the display effect of the display screen and effectively avoid abnormal image display caused by wrong data transmission.
To sum up, the utility model provides a pair of Demux display screen drive circuit, through the grid with transistor T1 connect first Demux control line, another termination second Demux control line of electric capacity Cr, transistor T2's grid connects third Demux control line, transistor T4's grid connects second Demux control line, transistor T5's grid connects fourth Demux control line, another termination third Demux control line of electric capacity Cg, transistor T7's grid connects third Demux control line, another termination fourth Demux control line of electric capacity Cb, transistor T8's grid connects first Demux control line, can improve the level of Demux display screen drive circuit's control end like this, improve Demux display screen drive circuit's drive power, thereby can solve the picture that causes because of the decline of Demux drive power and show the inequality, and then promote the display effect of display screen.
The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.
Claims (5)
1. A Demux display screen driving circuit is characterized by comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor Cr, a capacitor Cg and a capacitor Cb, wherein a gate of the transistor T1 is connected with a first Demux control line, a source of the transistor T1 is respectively and electrically connected with one end of the capacitor Cr, a drain of the transistor T2 and a gate of the transistor T3, the other end of the capacitor Cr is connected with a second Demux control line, a gate of the transistor T2 is connected with a third Demux control line, a gate of the transistor T4 is connected with the second Demux control line, a source of the transistor T4 is respectively and electrically connected with one end of the capacitor Cg, a drain of the transistor T5 and a gate of the transistor T6, a gate of the transistor T5 is connected with a fourth Demux control line, the other end of the capacitor Cg is connected with a third Demux control line, and a gate of the transistor T7, the source of the transistor T7 is electrically connected to one end of the capacitor Cb, the drain of the transistor T8, and the gate of the transistor T9, respectively, the other end of the capacitor Cb is connected to a fourth Demux control line, the gate of the transistor T8 is connected to the first Demux control line, the source of the transistor T3 is electrically connected to the source of the transistor T6 and the source of the transistor T9, respectively, and the source of the transistor T3 is connected to the source of the transistor T6 and the source of the transistor T9, respectively, through the same source line.
2. The Demux display screen driving circuit according to claim 1, wherein the drain of the transistor T3 is connected to the first data trace, the drain of the transistor T6 is connected to the second data trace, and the drain of the transistor T9 is connected to the third data trace.
3. The Demux display screen driving circuit of claim 1, wherein the drain of the transistor T1, the drain of the transistor T4, and the drain of the transistor T7 are all connected to the positive electrode of the power supply.
4. The Demux display screen driving circuit of claim 1, wherein the source of the transistor T2, the source of the transistor T5, and the source of the transistor T8 are all connected to the negative terminal of the power supply.
5. The Demux display screen driving circuit of claim 1, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T9 are all N-channel MOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120416826.1U CN215265523U (en) | 2021-02-25 | 2021-02-25 | Drive circuit of Demux display screen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120416826.1U CN215265523U (en) | 2021-02-25 | 2021-02-25 | Drive circuit of Demux display screen |
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| Publication Number | Publication Date |
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| CN215265523U true CN215265523U (en) | 2021-12-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202120416826.1U Active CN215265523U (en) | 2021-02-25 | 2021-02-25 | Drive circuit of Demux display screen |
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| CN (1) | CN215265523U (en) |
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- 2021-02-25 CN CN202120416826.1U patent/CN215265523U/en active Active
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