TWI754523B - Driiving circuit - Google Patents

Abstract

A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the third transistor is electrically coupled to a second terminal of the first transistor, a second terminal of the third transistor is electrically coupled to a gate terminal of the first transistor, and a gate terminal of the third transistor is configured to receive a first control signal. A first terminal of the fourth transistor is electrically coupled to the gate terminal of the first transistor, a second terminal of the fourth transistor is electrically coupled to the second system voltage terminal, and a gate terminal of the fourth transistor is configured to receive a second control signal. A first terminal of the first capacitance is electrically coupled to the gate terminal of the first transistor.

Description

Drive circuit

This case is about a drive circuit, especially a voltage-compensated drive circuit.

Generally speaking, the driving circuit uses an internal compensation method to compensate the threshold voltage of the driving circuit. However, with the increase of the number of pixels in the vertical direction of the display panel and the reduction of the horizontal scanning time, the traditional method of internally compensating the threshold voltage may cause the problem of insufficient charging rate of the driving circuit.

The present disclosure provides a driving circuit including a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a voltage regulator circuit. The first transistor, the second transistor and the light-emitting element are electrically connected in series between the first system voltage terminal and the second system voltage terminal. The first terminal of the third transistor is electrically coupled to the second terminal of the first transistor, the second terminal of the third transistor is electrically coupled to the gate terminal of the first transistor, and the gate terminal of the third transistor is used for A first control signal is received. The first terminal of the fourth transistor is electrically coupled to the gate terminal of the first transistor, the second terminal of the fourth transistor is electrically coupled to the second system voltage terminal, and the gate terminal of the fourth transistor is used for receiving the second system voltage terminal. control signal. The first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. The voltage regulator circuit is electrically coupled to the second end of the first capacitor.

To sum up, the driving circuit of the present disclosure compensates the threshold voltage of the first transistor according to the first control signal.

The following examples are described in detail in conjunction with the accompanying drawings, but the provided examples are not intended to limit the scope of the present disclosure, and the description of the structure and operation is not intended to limit its execution order. The structure and the resulting device with equal efficacy are all within the scope of the present disclosure. For ease of understanding, the same or similar elements in the following description will be described with the same symbols.

The terms used throughout the specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, in the content disclosed herein and in the specific content.

In addition, the terms "comprising", "including", "having", "containing" and the like used in this document are all open-ended terms, ie, meaning "including but not limited to".

In this document, when an element is referred to as being "coupled" or "connected", it may be referred to as "electrically coupled" or "electrically connected". "Coupled" or "connected" may also be used to indicate the cooperative operation or interaction between two or more elements. In addition, although terms such as "first", "second", . . . are used herein to describe different elements, the terms are only used to distinguish elements or operations described by the same technical terms.

In the current display panel technology, compared with splicing a plurality of display panels to form a display, a display made of a single panel (an integrally formed panel) can reduce the influence of splicing dark streaks. However, under the condition of the same resolution, a display panel with a larger size will have more columns of pixels. In this case, if the time of each frame of the display is still set to a fixed value, the scan time of each column of a single panel (ie, a larger display panel) or the time of writing data (eg, 3.8µs) will be Much smaller than the scan time or writing time (eg, 7.7µs) of each column of a spliced display panel (that is, multiple smaller-sized display panels), so if the traditional method of writing and compensating at the same time is used The operation mode (eg, simultaneously writing the data voltage and compensating for the threshold voltage of the driving circuit) applied to a display made of a single panel may cause insufficient charging rate, or cause the data voltage to be unable to be written normally.

Please refer to FIG. 1. FIG. 1 is a functional block diagram of a driving circuit 100 according to an embodiment of the disclosure. As shown in FIG. 1 , the driving circuit 100 includes a light emitting element L1 , a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a first capacitor C1 and a voltage regulator circuit 110 .

The first transistor T1, the second transistor T2 and the light emitting element L1 are electrically connected in series between the first system voltage terminal VDD and the second system voltage terminal VSS.

The transistors respectively have a first terminal, a second terminal and a gate terminal. When the first terminal of one of the transistors is the drain terminal (source terminal), the second terminal of the transistor is the source terminal (drain terminal). In addition, the capacitors also have a first end and a second end, respectively. The transistors in this disclosure are exemplified by P-type metal oxide semiconductor field effect transistor switches. In another embodiment, those skilled in the art can replace the transistors in the present disclosure with N-type MOSFET switches, C-type MOSFET switches, or other similar ones. Switching elements, and adjusting the system voltage, control signal data signal correspondingly, can also achieve the same function as the embodiment of the present disclosure.

In detail, the first terminal of the first transistor T1 is electrically coupled to the first system voltage terminal VDD, the second terminal of the first transistor T1 is electrically coupled to the first terminal of the second transistor T2, and the first power The gate terminal of the crystal T1 is electrically coupled to the first terminal of the first capacitor C1. The first end of the second transistor T2 is electrically coupled to the second end of the first transistor T1, the second end of the second transistor T2 is electrically coupled to the first end of the light-emitting element L1, and the second end of the second transistor T2 is electrically coupled to the first end of the light-emitting element L1. The gate terminal is used for receiving the fourth control signal EM(n). The first terminal of the light-emitting element L1 is electrically coupled to the second terminal of the second transistor T2, and the second terminal of the light-emitting element L1 is electrically coupled to the second system voltage terminal VSS.

The first terminal of the third transistor T3 is electrically coupled to the second terminal of the first transistor T1, the second terminal of the third transistor T3 is electrically coupled to the gate terminal of the first transistor T1, and the third transistor T3 The gate terminal of the is used for receiving the first control signal Cs(n). The first terminal of the fourth transistor T4 is electrically coupled to the second terminal of the third transistor T3 and the gate terminal of the first transistor T1, and the second terminal of the fourth transistor T4 is electrically coupled to the first system voltage terminal The second terminal of the VSS and the light-emitting element L1, and the gate terminal of the fourth transistor T4 are used for receiving the second control signal Cs(n-1). The first terminal of the first capacitor C1 is electrically coupled to the gate terminal of the first transistor T1, the second terminal of the third transistor T3 and the first terminal of the fourth transistor T4, and the second terminal of the first capacitor C1 is electrically coupled to the gate terminal of the first transistor T1. Sexually coupled to the voltage regulator circuit 110 .

Please also refer to FIG. 2. FIG. 2 is a circuit structure diagram of the driving circuit 100 according to an embodiment of the disclosure. The driving circuit 100 shown in FIG. 2 includes a voltage-stabilizing circuit 110a, and the voltage-stabilizing circuit 110a shown in FIG. 2 is one of the embodiments for realizing the voltage-stabilizing circuit 110 shown in FIG. 1 . As shown in FIG. 2, the voltage regulator circuit 110a includes a second capacitor C2 and a fifth transistor T5.

In detail, the first terminal of the second capacitor C2 is electrically coupled to the first system voltage terminal VDD, and the second terminal of the second capacitor C2 is electrically coupled to the second terminal of the first capacitor C1. The first end of the fifth transistor T5 is electrically coupled to the second end of the second capacitor C2 and the second end of the first capacitor C1, the second end of the fifth transistor T5 is used for receiving the reference voltage Vref, and the fifth The gate terminal of the crystal T5 is used for receiving the first control signal CS(n).

The driving circuit 100 further includes a seventh transistor T7. The first end of the seventh transistor T7 is used for receiving the data signal D(n), and the second end of the seventh transistor T7 is electrically coupled to the second end of the second capacitor C2, the second end of the first capacitor C1 and The first terminal of the fifth transistor T5 and the gate terminal of the seventh transistor T7 are used for receiving the third control signal WS(n).

FIG. 3 is a timing diagram of control signals of the driving circuit 100 in FIG. 2 according to an embodiment. As shown in FIG. 3 , one display period in the control sequence of the driving circuit 100 can be divided into two main periods, which are the setting period BP and the light-emitting period EP, respectively. The setting period BP is a non-light-emitting period, and the light-emitting period EP is a light-emitting period that the drive circuit 100 can occupy in one display period. In addition, the setting period BP can be divided into three periods, which are a reset period P1, a compensation period P2, and a writing period P3, respectively. It should be particularly noted that the time lengths of the periods in FIG. 2 are only used as examples, and are not used to limit the present disclosure.

Specifically, the first control signal CS(n) has a first logic level (eg, a low logic level) during the reset period P1; the first control signal CS(n) has a first logic level during the compensation period P2 and the writing period P3 The second logic level (eg, high logic prevails). The second control signal CS(n-1) has a low logic level during the compensation period P2; the second control signal CS(n-1) has a high logic level during the reset period P1 and the writing period P3. The third control signal WS(n) has a low logic level during the writing period P3; the third control signal WS(n) has a high logic level during the reset period P1 and the writing period P2. The first control signal CS(n), the second control signal CS(n-1) and the third control signal WS(n) have a high logic level during the light-emitting period EP. In addition, the fourth control signal EM(n) has a high logic level during the setting period BP; the fourth control signal EM(n) has a low logic level during the light-emitting period EP.

During the reset period P1, the second control signal CS(n-1) is at a low logic level, so the fourth transistor T4 is turned on. On the other hand, the first control signal CS(n), the third control signal WS(n) and the fourth control signal EM(n) are at high logic levels, so the second transistor T2, the third transistor T3, the The five transistors T5 and the seventh transistor T7 are turned off.

Specifically, during the reset period P1, since the fourth transistor T4 is turned on, a current path CP1 is formed from the second system voltage terminal VSS through the fourth transistor T4 to the first terminal of the first capacitor C1, so that the second system voltage The potential of the terminal VSS is transmitted to the first terminal of the first capacitor C1 via the fourth transistor T4, and the potential of the gate terminal of the first transistor T1 (the first terminal of the first capacitor C1) is affected by the voltage of the second system voltage terminal VSS. When the potential is pulled down to a low logic level, the first transistor T1 is turned on.

Then, in the compensation period P2, the first control signal CS(n) is at a low logic level, so the third transistor T3 and the fifth transistor T5 are turned on. On the other hand, when the second control signal CS(n-1), the third control signal WS(n) and the fourth control signal EM(n) are at high logic levels, the first transistor T1, the second transistor T2, The fourth transistor T4 and the seventh transistor T7 are turned off.

Specifically, at the beginning of the compensation period P2, since the potential of the gate terminal of the first transistor T1 (the first terminal of the first capacitor C1) is still at a low logic level, the first transistor T1 is turned on. In addition, since the first transistor T1 and the third transistor T3 are turned on, a current path CP2 is formed from the first system voltage terminal VDD through the first transistor T1 and the third transistor T3 to the gate terminal of the first transistor T1, so that the current path CP2 is formed. The potential of the first system voltage terminal VDD is transmitted to the gate terminal of the first transistor T1 through the first transistor T1 and the third transistor T3 until the gate terminal of the first transistor T1 and the source terminal (the first terminal) are crossed. When the voltage is equal to the threshold voltage of the first transistor T1, the first transistor T1 is turned off, thereby performing the threshold voltage compensation of the first transistor T1.

Moreover, during the compensation period P2, since the fifth transistor T5 is turned on, the reference voltage Vref is transmitted to the second end of the first capacitor C1 through the fifth transistor T5.

Then, in the writing period P3, the third control signal WS(n) is at a low logic level, so the seventh transistor T7 is turned on. On the other hand, when the first control signal CS(n), the second control signal CS(n-1) and the fourth control signal EM(n) are at high logic levels, the first transistor T1, the second transistor T2, The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off.

During the writing period P3, since the seventh transistor T7 is turned on, a current path CP3 is formed through the seventh transistor T7 to the second end of the first capacitor C1 to form a current path CP3, so that the data signal D(n) passes through the seventh transistor T7 is transmitted to the second terminal of the first capacitor C1 and is transmitted to the gate terminal of the first transistor T1 through capacitive coupling, thereby writing the data signal D(n) into the driving circuit 100 .

It should be noted that the driving circuit 100 compensates the threshold voltage of the first transistor T1 and the write data signal D(n) according to the first control signal CS(n) and the third control signal WS(n), respectively. Therefore, the compensation period P2 and the writing period P3 of the driving circuit 100 can operate independently. In addition, the time length of the first control signal CS(n) and the third control signal WS(n) at the low level can be adjusted according to the circuit load. In some embodiments, the first control signal CS(n), the second control signal CS(n-1), the third control signal WS(n) and the fourth control signal EM(n) are each at a low logic level The length of time can be one time unit (eg, 3.8µs). In other embodiments, the first control signal CS(n), the second control signal CS(n-1), the third control signal WS(n) and the fourth control signal EM(n) are each at a low logic level The length of time can be two time units (for example, 2*3.8µs).

In some other embodiments, the driving circuit that performs writing and internal compensation at the same time compensates the threshold voltage of the driving transistor according to the data signal. In this case, if the current operating sequence of the driving circuit has a pre-charge The setting may be written into the data signal provided to the pre-driver circuit at a higher gray level, and the drive transistor is turned off by compensating for the threshold voltage by the wrong data signal, and cannot be written into the current driver circuit. The lower grayscale data signal causes the wrong data signal to be written. In some other embodiments, the driving circuit that performs writing and internal compensation simultaneously controls the driving transistor to compensate the threshold voltage and write the data signal according to the current-stage control signal and the previous-stage control signal having a partially overlapping period. In such a situation, the charging rate of the driving circuit may be insufficient, resulting in uneven display (mura) of pixels in adjacent columns in the display screen.

Therefore, under the circuit structure of the driving circuit 100 disclosed in the present disclosure, the data signal Data is written into the driving circuit 100 through capacitive coupling during the writing period P3, and the threshold voltage of the transistor does not need to be compensated internally by the data signal, which can avoid writing The effect of entering wrong data signals (for example, the data signals of the pre-drive). And in a display period, the time of the second control signal CS(n-1) (previous stage control signal) and the first control signal CS(n) (current stage control signal) at the low logic level are not overlapping. The period, that is, the reset period P1 and the compensation period P2 do not overlap. In addition, the time when the third control signal WS(n) is at a low logic level is also at a low level with the second control signal CS(n-1) previous control signal and the first control signal CS(n) (current control signal) The times of the logic levels do not overlap, that is, the writing period P3 does not overlap the compensation period P2. Therefore, the driving circuit 100 can extend the writing period P3 in advance according to the requirements of the product, and the data signal D(n) will also be correctly written into the driving circuit 100, so as to reserve enough time for the data signal D(n). n) Writing, thereby increasing the uniformity of the display and the charging rate of the display.

In detail, as shown in FIG. 3 , the data lines Sig respectively provide data signals D(n-3) to D(n+1) to the driving circuits of different columns. The driving circuit 100 is used for receiving the data signal D(n), and the time point when the third control signal WS(n) is switched from a high logic level to a low logic level can be advanced before the data signal D(n), so as to receive data through The signal D(n-1) is precharged, and the time point when the third control signal WS(n) is switched from the low logic level to the high logic level (that is, the time point when the seventh transistor T7 is turned off) needs to be During the period of receiving the data signal D(n), the data signal D(n) is written into the driving circuit 100 through capacitive coupling. It should be noted that the data signals D(n-3)~D(n+1) of the data line Sig shown in FIG. 3 are only examples, and this case is not limited to this.

During the light-emitting period EP, the first control signal CS(n), the second control signal CS(n-1) and the third control signal WS(n) are at high logic levels, so the first transistor T1 and the third transistor are T3, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off. On the other hand, the fourth control signal EM(n) is at a low logic level, so that the second transistor T2 is turned on.

During the light-emitting period EP, since the second transistor T2 is turned on, the driving current D1 flows from the first system voltage terminal VDD through the first transistor T1, the second transistor T2, the light-emitting element L1 to the second system voltage terminal VSS. In addition, the magnitude of the driving current D1 depends on the potential of the gate terminal of the first transistor T1. Thereby, the gray scale of the light emitting element L1 in the driving circuit 100 is controlled according to the data signal D(n) provided in the writing period P3.

It is worth noting that the fourth control signal EM(n) shown in FIG. 3 is at a low logic level during the light-emitting period EP (light-emitting period), whereby the light-emitting period EP in one frame continuously emits light. In some embodiments, the fourth control signal EM(n) can be alternately switched between a high logic level and a low logic level during the light-emitting period EP (light-emitting period), whereby the light-emitting period EP in one frame achieves multiple Pulse (multi-impulse) to support adaptive synchronization technology (eg, G-SYNC), and achieve power saving performance.

In some embodiments, the time length of the fourth control signal EM(n) at the high logic level in the setting period BP may be eight time units (eg, 8*3.8 µs).

In another embodiment of the present disclosure, the effect of the embodiment shown in FIG. 2 can also be achieved, please refer to FIG. 4 . FIG. 4 is a circuit structure diagram of the driving circuit 100 according to an embodiment of the disclosure. The driving circuit 100 shown in FIG. 4 includes a voltage-stabilizing circuit 110b, and the voltage-stabilizing circuit 110b shown in FIG. 4 is another embodiment for realizing the voltage-stabilizing circuit 110a shown in FIG. 1 . Compared with the voltage-stabilizing circuit 110a in the driving circuit 100 in FIG. 2 including the second capacitor C2 and the fifth transistor T5, the voltage-stabilizing circuit 110b in the driving circuit 100 in FIG. 4 includes the second capacitor C2, the Five transistors T5 and a sixth transistor T6.

Structurally, the first end of the sixth transistor T6 is electrically coupled to the first end of the fifth transistor T5, the second end of the sixth transistor T6 is electrically coupled to the second end of the fifth transistor T5, The gate terminal of the sixth transistor T6 is used for receiving the second control signal CS(n-1), and the gate terminal of the sixth transistor T6 is electrically coupled to the gate terminal of the fourth transistor T4.

It should be noted that, in this embodiment, the sixth transistor T6 is turned on during the setting period P1 according to the second control signal CS(n-1), so that the reference voltage Vref is transmitted to the first capacitor C1 through the sixth transistor T6 the second end of the first capacitor C1 to stabilize the potential of the second end of the first capacitor C1. Other detailed connection relationships and operation methods of the driving circuit 100 in FIG. 4 are substantially the same as the driving circuit 100 in the previous embodiment in FIG. 2 , and will not be repeated here.

In another embodiment of the present disclosure, the effect of the embodiment shown in FIG. 2 can also be achieved, please refer to FIG. 5 . FIG. 5 is a circuit structure diagram of a driving circuit 200 according to an embodiment of the disclosure. The driving circuit 200 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8, a voltage regulator circuit 210, a first capacitor C1 and Light-emitting element L1. The voltage regulator circuit 210 includes a fifth transistor T5, a sixth transistor T6 and a second capacitor C2.

Compared with the driving circuit 100 in FIG. 4 , the driving circuit 200 in FIG. 5 further includes an eighth transistor T8 . In addition, the timing of the control signal of the driving circuit 200 may also be implemented by the driving circuit 100 in the timing chart shown in FIG. 3 .

Structurally, the first end of the eighth transistor T8 is electrically coupled to the second end of the second capacitor C2, the first end of the fifth transistor T5, and the first end of the sixth transistor T6, and the eighth transistor The second terminal of T8 is electrically coupled to the second terminal of the second transistor T2 and the first terminal of the light emitting element L1 , and the gate terminal of the eighth transistor T8 is used for receiving the test signal Test. Therefore, before the light-emitting element L1 is installed, there will be a current path from the first system voltage terminal VDD, the first transistor T1, the second transistor T2, the eighth transistor T8, and the fifth transistor T5 to the reference voltage Vref , or to the data signal D(n) via the seventh transistor T7 for detection. Other detailed connection relationships and operation methods of the driving circuit 200 in FIG. 5 are substantially the same as the driving circuit 100 in the previous embodiment in FIG. 4 , and will not be repeated here.

In another embodiment of the present disclosure, the effect of the embodiment shown in FIG. 1 can also be achieved, please refer to FIG. 6 . FIG. 6 is a circuit structure diagram of a driving circuit 300 according to an embodiment of the disclosure. The driving circuit 300 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a seventh transistor T7, a ninth transistor T9, a tenth transistor T10, and a voltage regulator circuit 310 , the first capacitor C1 and the light-emitting element L1. The voltage regulator circuit 310 includes a fifth transistor T5, a sixth transistor T6 and a second capacitor C2.

Compared with the driving circuit 100 in FIG. 4 , the driving circuit 300 in FIG. 6 further includes a ninth transistor T9 and a tenth transistor T10 . In addition, the timing of the control signals of the driving circuit 300 may also be implemented by the driving circuit 100 in the timing chart shown in FIG. 3 .

Structurally, the first terminal of the ninth transistor T9 is electrically coupled to the first system voltage terminal VDD, the second terminal of the ninth transistor T9 is electrically coupled to the first terminal of the first transistor T1, and the ninth transistor T9 is electrically coupled to the first terminal of the first transistor T1. The gate terminal of the crystal T9 is used for receiving the fourth control signal EM(n). The second end of the first transistor T1 is electrically coupled to the first end of the second transistor T2. The second terminal of the second transistor T2 is electrically coupled to the first terminal of the light emitting element L1 , and the second terminal of the light emitting element L1 is electrically coupled to the second system voltage terminal VSS.

The first terminal of the tenth transistor T10 is electrically coupled to the first system voltage terminal VDD and the first terminal of the ninth transistor T9, and the second terminal of the tenth transistor T10 is electrically coupled to the first terminal of the first transistor T1. One terminal and the second terminal of the ninth transistor T9, and the gate terminal of the tenth transistor T10 are used for receiving the first control signal CS(n).

Compared with the driving circuit 100 shown in FIG. 4 , the driving circuit 300 shown in FIG. 6 adds a ninth transistor T9 and a tenth transistor T10 to prevent the driving circuit 300 from deteriorating greatly. Other detailed connection relationships and operation methods of the driving circuit 300 in FIG. 6 are substantially the same as the driving circuit 100 in the previous embodiment in FIG. 4 , and will not be repeated here.

In another embodiment of the present disclosure, the effect of the embodiment shown in FIG. 2 can also be achieved, please refer to FIG. 7 . FIG. 7 is a circuit structure diagram of a driving circuit 400 according to an embodiment of the disclosure. The driving circuit 400 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a seventh transistor T7, a tenth transistor T10, a voltage regulator circuit 410, a first capacitor C1 and Light-emitting element L1. The voltage regulator circuit 410 includes a fifth transistor T5, a sixth transistor T6 and a second capacitor C2.

Compared with the driving circuit 300 in FIG. 6 , the driving circuit 400 in FIG. 7 does not have the ninth transistor T9 . In addition, the timing of the control signals of the driving circuit 300 may also be implemented by the driving circuit 100 in the timing chart shown in FIG. 3 .

Structurally, the first terminal of the tenth transistor T10 is electrically coupled to the first system voltage terminal VDD and the first terminal of the light emitting element L1, and the second terminal of the tenth transistor T10 is electrically coupled to the first transistor T1 The first end of the light emitting element L1 and the second end of the light emitting element L1, the gate end of the tenth transistor T10 is used for receiving the first control signal CS(n). The second end of the first transistor T1 is electrically coupled to the first end of the second transistor T2. The second terminal of the second transistor T2 is electrically coupled to the second system voltage terminal VSS. During the compensation period P2, the tenth transistor T10 is turned on according to the first control signal CS(n) to form a current path CP4 from the first system voltage terminal VDD through the tenth transistor T10 to the first terminal of the first transistor T1 , so that the potential of the first system voltage terminal VDD is transmitted to the first terminal of the first transistor T1 through the tenth transistor T10 for detection. Other detailed connection relationships and operation methods of the driving circuit 400 in FIG. 7 are substantially the same as the driving circuit 100 in the previous embodiment in FIG. 4 , and will not be repeated here.

To sum up, the compensation period P2 of the driving circuits 100 , 200 , 300 and 400 of the present disclosure may not overlap the writing period P3 , so the time length of the writing period P3 can be increased in the setting of the operation timing to ensure the driving circuit 100 , 200, 300 and 400 have sufficient pre-charge time, thereby increasing the uniformity of the display screen.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection disclosed shall be determined by the scope of the appended patent application.

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the descriptions of the appended symbols are as follows: 100,200,300,400: Driver circuit 110, 110a, 110b, 210, 310, 410: Voltage Regulator Circuits T1: first transistor T2: Second transistor T3: The third transistor T4: Fourth transistor T5: Fifth transistor T6: sixth transistor T7: seventh transistor T8: Eighth transistor T9: ninth transistor T10: Tenth transistor L1: Light-emitting element C1: first capacitor C2: second capacitor VDD: the first system voltage terminal VSS: The second system voltage terminal CS(n): The first control signal CS(n-1): The second control signal WS(n): The third control signal EM(n): the fourth control signal Test: Test signal Vref: reference voltage D(n): data signal CP1, CP2, CP3, CP4: Current paths

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows: FIG. 1 is a functional block diagram of a driving circuit according to an embodiment of the disclosure. FIG. 2 is a circuit structure diagram of a driving circuit according to an embodiment of the disclosure. FIG. 3 is a timing diagram of control signals of the driving circuit in FIG. 2 according to an embodiment. FIG. 4 is a circuit structure diagram of a driving circuit according to an embodiment of the disclosure. FIG. 5 is a circuit structure diagram of a driving circuit according to an embodiment of the disclosure. FIG. 6 is a circuit structure diagram of a driving circuit according to an embodiment of the disclosure. FIG. 7 is a circuit structure diagram of a driving circuit according to an embodiment of the disclosure.

Domestic storage information (please note in the order of storage institution, date and number) without Foreign deposit information (please note in the order of deposit country, institution, date and number) without

100: Drive circuit

110: Voltage regulator circuit

T1: first transistor

T2: Second transistor

T3: The third transistor

T4: Fourth transistor

T7: seventh transistor

L1: Light-emitting element

C1: first capacitor

VDD first system voltage terminal

VSS: The second system voltage terminal

CS(n): The first control signal

CS(n-1): The second control signal

WS(n): The third control signal

EM(n): the fourth control signal

Vref: reference voltage

D(n): data signal

Claims (10)

A driving circuit, comprising: a light-emitting element; a first transistor; a second transistor, wherein the first transistor, the second transistor and the light-emitting element are electrically connected in series with a first system voltage terminal and a Between the second system voltage terminals; a third transistor, the first terminal of which is electrically coupled to the second terminal of the first transistor, and the second terminal of which is electrically coupled to the gate terminal of the first transistor, the The gate terminal is used for receiving a first control signal; a fourth transistor, the first terminal of which is electrically coupled to the gate terminal of the first transistor, and the second terminal of which is electrically coupled to the second system voltage terminal, the The gate terminal is used for receiving a second control signal; a first capacitor, the first terminal of which is electrically coupled to the gate terminal of the first transistor; a voltage regulator circuit, which is electrically coupled to the second terminal of the first capacitor ; and a seventh transistor, the first end of which is used to receive a data signal, the second end of which is electrically coupled to the second end of the first capacitor, and the gate end of which is used to receive a third control signal. The driving circuit of claim 1, wherein the voltage regulator circuit comprises: a second capacitor, the first terminal of which is electrically coupled to the first system voltage terminal, and the second terminal of which is electrically coupled to the first capacitor the second end; and A fifth transistor, the first terminal of which is electrically coupled to the second terminal of the second capacitor, the second terminal of which is used for receiving a reference voltage, and the gate terminal of which is used for receiving the first control signal. The driving circuit of claim 2, wherein the driving circuit operates in a reset period and a compensation period in sequence, wherein: during the reset period, the second control signal is at a first logic level to turn on the a fourth transistor, so that the potential of the second system voltage terminal is transmitted to the first end of the first capacitor through the fourth transistor and turns on the first transistor, and the first control signal is at a second logic level to turn off the third transistor and the fifth transistor; and during the compensation period, the first control signal is at the first logic level to turn on the third transistor and the fifth transistor, so that the reference The voltage is transmitted to the second terminal of the first capacitor through the fifth transistor, and the potential of the first system voltage terminal is transmitted to the gate terminal of the first transistor through the first transistor and the third transistor, and The second control signal turns off the fourth transistor at the second logic level. The driving circuit of claim 2, wherein the voltage regulator circuit further comprises: a sixth transistor, the first terminal of which is electrically coupled to the first terminal of the fifth transistor, and the second terminal of which is electrically coupled to The gate terminal of the second terminal of the fifth transistor is used for receiving the second control signal. The driving circuit of claim 2, wherein the driving circuit operates in a reset period and a compensation period in sequence, wherein: during the reset period, the second control signal is at a first logic level to turn on the The fourth transistor and the sixth transistor make the potential of the second system voltage terminal transfer to the first end of the first capacitor through the fourth transistor and turn on the first transistor, and the reference voltage passes through the sixth transistor The electric hall is transmitted to the second end of the first capacitor, and the first control signal is at a second logic level to turn off the third transistor and the fifth transistor; and during the compensation period, the first control signal A control signal turns on the third transistor and the fifth transistor at the first logic level, so that the reference voltage is transmitted to the second end of the first capacitor through the fifth transistor, and the first system The potential of the voltage terminal is transmitted to the gate terminal of the first transistor through the first transistor and the third transistor, and the second control signal is at the second logic level to turn off the fourth transistor and the first transistor Six transistors. The driving circuit of claim 2, wherein during a writing period, the third control signal is at the first logic level to turn on the seventh transistor, so that the data signal is transmitted to the seventh transistor through the seventh transistor The second end of the first capacitor, and the first control signal and the second control signal are at the second logic level to turn off the third transistor, the fourth transistor and the fifth transistor. The driving circuit of claim 1, wherein the first terminal of the first transistor is electrically coupled to the first system voltage terminal, and the second terminal of the first transistor is electrically coupled to the second terminal of the second transistor The first end, wherein the second end of the second transistor is electrically coupled to the first end of the light-emitting element, the gate end of the second transistor is used for receiving a fourth control signal, wherein the second end of the light-emitting element The terminal is electrically coupled to the second system voltage terminal. The driving circuit of claim 7, further comprising: an eighth transistor, the first terminal of which is electrically coupled to the second terminal of the first capacitor, and the second terminal of which is electrically coupled to the second terminal of the second transistor The second end, the gate terminal of which is used for receiving a test signal. The driving circuit of claim 1, further comprising: a ninth transistor, the first terminal of which is electrically coupled to the first system voltage terminal, and the second terminal of which is electrically coupled to the first terminal of the first transistor a terminal, the gate terminal of which is used for receiving a fourth control signal; and a tenth transistor, the first terminal of which is electrically coupled to the first terminal of the ninth transistor, and the second terminal of which is electrically coupled to the ninth transistor The second end of the transistor, the gate end of which is used for receiving the first control signal, wherein the second end of the first transistor is electrically coupled to the first end of the second transistor, wherein the second transistor The second terminal of the light-emitting element is electrically coupled to the first terminal of the light-emitting element, the gate terminal of the second transistor is used to receive a fourth control signal, and the second terminal of the light-emitting element is electrically coupled to the second system voltage end. The driving circuit of claim 1, further comprising: a tenth transistor, the first terminal of which is electrically coupled to the first system voltage terminal, and the second terminal of which is electrically coupled to the first terminal of the first transistor terminal, the gate terminal of which is used for receiving the first control signal, wherein the first terminal of the light-emitting element is electrically coupled to the first terminal of the tenth transistor, and the second terminal of the light-emitting element is electrically coupled to the first terminal of the tenth transistor. A first terminal of a transistor, a second terminal of the first transistor is electrically coupled to the first terminal of the second transistor, and a second terminal of the second transistor is electrically coupled to the second system voltage terminal , the gate terminal of the second transistor is used for receiving a fourth control signal.

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