CN215265522U - GIP circuit suitable for high-resolution display screen - Google Patents
GIP circuit suitable for high-resolution display screen Download PDFInfo
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- CN215265522U CN215265522U CN202120416769.7U CN202120416769U CN215265522U CN 215265522 U CN215265522 U CN 215265522U CN 202120416769 U CN202120416769 U CN 202120416769U CN 215265522 U CN215265522 U CN 215265522U
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Abstract
The utility model relates to a GIP circuit technical field, in particular to GIP circuit suitable for high resolution display screen, including transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9 and electric capacity C1, the source of transistor T1 respectively with the grid of transistor T6, the drain-source resistance of transistor T7, the source-source resistance of transistor T4, the grid of transistor T5 and electric capacity C1's one end electricity are connected, can improve the charging voltage of key node Q point (be the common terminal department of the source of transistor T1 and the drain-source resistance of transistor T7) in the GIP circuit like this, thereby improve the charge-discharge ability of display screen GIP circuit, be particularly useful for on the display screen of high resolution.
Description
Technical Field
The utility model relates to a GIP circuit technical field, in particular to GIP circuit suitable for high resolution display screen.
Background
With the continuous development of the information-oriented society, the demand of people for high-resolution display screens is continuously increased, and higher resolution under the same size generally represents a more exquisite display picture. However, the higher resolution means less charging and discharging time for the display screen, and higher requirements are put on the circuit design of the display screen.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve is: the GIP circuit is suitable for a high-resolution display screen, is used for improving the charge and discharge capacity of the GIP circuit of the display screen, and is particularly suitable for the high-resolution display screen.
In order to solve the technical problem, the utility model discloses a technical scheme be:
a GIP circuit suitable for a high-resolution display screen comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4 and a capacitor C4, wherein a gate of the transistor T4 is electrically connected with a gate of the transistor T4, a gate of the transistor T4 and a gate of the transistor T4 are connected with a first gate line, a source of the transistor T4 is electrically connected with the gate of the transistor T4, a drain of the transistor T4, a source of the transistor T4 is electrically connected with a source of the transistor T4, a drain of the transistor T4, a gate of the transistor T4, a source of the transistor T4 and a gate of the transistor T4, a source of the transistor T4 is electrically connected with the drain of the transistor T4, a source of the transistor T4 is electrically connected with the other end of the capacitor C4, a drain of the transistor T4 and a drain of the transistor T4 are electrically connected with the transistor T4 and a drain of the transistor T4, The other end of the capacitor C1 and the drain of the transistor T9 are both connected to the second gate trace, the gate of the transistor T3 is electrically connected to the gate of the transistor T4, the gate of the transistor T3 and the gate of the transistor T4 are both connected to the third gate trace, the source of the transistor T6 is electrically connected to the source of the transistor T7 and the source of the transistor T9, respectively, and the gate of the transistor T8 is electrically connected to the drain of the transistor T8.
The beneficial effects of the utility model reside in that:
by electrically connecting the gate of the transistor T1 with the gate of the transistor T2, and electrically connecting the gate of the transistor T1 and the gate of the transistor T2 to the first gate trace, respectively connecting the source of the transistor T1 with the gate of the transistor T6, electrically connecting the drain of the transistor T7, the source of the transistor T4, the gate of the transistor T5 and one end of the capacitor C1, electrically connecting the source of the transistor T5 with the other end of the capacitor C1 and the drain of the transistor T9, electrically connecting the source of the transistor T5, the other end of the capacitor C1 and the drain of the transistor T9 to the second gate trace, electrically connecting the gate of the transistor T3 with the gate of the transistor T4, and electrically connecting the gate of the transistor T3 and the gate of the transistor T4, the charging and discharging voltage at the critical node Q point (i.e. the source of the transistor T1 and the drain of the transistor T7) in the GIP circuit can be increased, thereby increasing the capability of the display panel GIP circuit, the method is particularly suitable for high-resolution display screens.
Drawings
Fig. 1 is a schematic structural diagram of a GIP circuit suitable for a high-resolution display screen according to the present invention;
fig. 2 is a timing waveform diagram of a GIP circuit suitable for a high resolution display according to the present invention.
Detailed Description
In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, the present invention provides a technical solution:
a GIP circuit suitable for a high-resolution display screen comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4 and a capacitor C4, wherein a gate of the transistor T4 is electrically connected with a gate of the transistor T4, a gate of the transistor T4 and a gate of the transistor T4 are connected with a first gate line, a source of the transistor T4 is electrically connected with the gate of the transistor T4, a drain of the transistor T4, a source of the transistor T4 is electrically connected with a source of the transistor T4, a drain of the transistor T4, a gate of the transistor T4, a source of the transistor T4 and a gate of the transistor T4, a source of the transistor T4 is electrically connected with the drain of the transistor T4, a source of the transistor T4 is electrically connected with the other end of the capacitor C4, a drain of the transistor T4 and a drain of the transistor T4 are electrically connected with the transistor T4 and a drain of the transistor T4, The other end of the capacitor C1 and the drain of the transistor T9 are both connected to the second gate trace, the gate of the transistor T3 is electrically connected to the gate of the transistor T4, the gate of the transistor T3 and the gate of the transistor T4 are both connected to the third gate trace, the source of the transistor T6 is electrically connected to the source of the transistor T7 and the source of the transistor T9, respectively, and the gate of the transistor T8 is electrically connected to the drain of the transistor T8.
From the above description, the beneficial effects of the present invention are:
by electrically connecting the gate of the transistor T1 with the gate of the transistor T2, and electrically connecting the gate of the transistor T1 and the gate of the transistor T2 to the first gate trace, respectively connecting the source of the transistor T1 with the gate of the transistor T6, electrically connecting the drain of the transistor T7, the source of the transistor T4, the gate of the transistor T5 and one end of the capacitor C1, electrically connecting the source of the transistor T5 with the other end of the capacitor C1 and the drain of the transistor T9, electrically connecting the source of the transistor T5, the other end of the capacitor C1 and the drain of the transistor T9 to the second gate trace, electrically connecting the gate of the transistor T3 with the gate of the transistor T4, and electrically connecting the gate of the transistor T3 and the gate of the transistor T4, the charging and discharging voltage at the critical node Q point (i.e. the source of the transistor T1 and the drain of the transistor T7) in the GIP circuit can be increased, thereby increasing the capability of the display panel GIP circuit, the method is particularly suitable for high-resolution display screens.
Further, the gate of the transistor T8, the drain of the transistor T8, and the drain of the transistor T5 are all connected to the clock signal.
Further, the drain of the transistor T2, the drain of the transistor T3, the source of the transistor T6, the source of the transistor T7 and the source of the transistor T9 are all connected to the negative pole of the power supply.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T9 are all N-channel MOS transistors.
From the above description, the output waveform of the GIP circuit can be further stabilized by the MOS transistor of the N channel, so that the cost for improving the GIP process is saved, and the display effect of the display screen is optimized.
Referring to fig. 1 and fig. 2, a first embodiment of the present invention is:
referring to fig. 1, a GIP circuit suitable for a high resolution display screen includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, and a capacitor C4, wherein a gate of the transistor T4 is electrically connected to a gate of the transistor T4 and the gate of the transistor T4 are both connected to a first gate trace, a source of the transistor T4 is electrically connected to the gate of the transistor T4, a drain of the transistor T4, a source of the transistor T4 is electrically connected to the drain of the transistor T4, the gate of the transistor T4, the source of the transistor T4 and one end of the transistor T4, the source of the transistor T4 is electrically connected to the drain of the transistor T4 and the drain of the transistor T4, and the source of the transistor T4 are electrically connected to the drain of the transistor T4 and the other end of the transistor T4 and the drain of the transistor T4 and the capacitor C4 are electrically connected to the drain of the transistor T4 and the drain of the other end of the transistor T4 and the capacitor C4 are electrically connected to the drain of the transistor T4 The other end of the capacitor C1 and the drain of the transistor T9 are both connected to the second gate trace, the gate of the transistor T3 is electrically connected to the gate of the transistor T4, the gate of the transistor T3 and the gate of the transistor T4 are both connected to the third gate trace, the source of the transistor T6 is electrically connected to the source of the transistor T7 and the source of the transistor T9, respectively, and the gate of the transistor T8 is electrically connected to the drain of the transistor T8.
The gate of the transistor T8, the drain of the transistor T8 and the drain of the transistor T5 are all connected to a clock signal.
The drain electrode of the transistor T2, the drain electrode of the transistor T3, the source electrode of the transistor T6, the source electrode of the transistor T7 and the source electrode of the transistor T9 are all connected with the negative pole of the power supply.
The transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8 and the transistor T9 are all N-channel MOS transistors.
Each stage of GIP circuit has 9 TFTs, 1 capacitor C1, FW and VGH are DC high voltage, and BW and VGL are DC low voltage. In this embodiment, the high potential of ck (n) is VGH potential, and the low potential thereof is VGL potential. The scheme makes the charging capability of the point Q stronger through two TFTs of a transistor T2 and a transistor T3, which is very important for a high-resolution display screen with short charging time.
The driving process of the GIP circuit is described below (please analyze with reference to fig. 2):
at time T1, Vg (n-4) is high (Vg (n-4) is G (n-4) in fig. 1), the transistor T1 and the transistor T2 are turned on, the transistor T1 gives the high potential of FW to the point Q, and the transistor T2 gives the low potential of VGL to the point P. It should be particularly mentioned here that, since the charging time of the high-resolution display screen is short, the charging of the point Q at this stage is particularly important, here, the TFT of the transistor T2 is introduced, so that the point P is pulled down to the VGL potential at time T1, if the TFT is not present, during the charging process of the point Q, the potential of the point P is still maintained at the VGH of the previous stage, the point Q is pulled down by the action of the transistor T7, and thus the charging capability of the point Q is reduced, the voltage of the point Q is reduced, and the display effect is affected.
At time T2, CK (n) changes from low to high, and the potential at point Q rises due to the presence of coupling capacitor C1, at which time G (n) receives the high potential of CK (n) through the action of transistor T5, and G (n) outputs the high potential.
At time T3, ck (n) changes from high to low, and the potential at point Q drops due to the presence of coupling capacitor C1, at which time g (n) receives low potential of ck (n) through the action of transistor T5, and g (n) outputs low potential.
At time T4, Vg (n +4) is high (Vg (n +4) is G (n +4) in fig. 1), the transistor T3 and the transistor T4 are turned on, and the Q point and the P point are pulled down to VGL level, respectively.
At time T5, CK (n) is high, transistor T8 is turned on, point P is high, transistor T9 is turned on, and G (n) is pulled down to VGL level by transistor T9.
According to the scheme, the charging voltage of the Q point of the key node in the GIP circuit is improved, so that the charging and discharging capacity of the GIP circuit of the display screen is improved, and the GIP circuit is particularly suitable for the display screen with high resolution.
In summary, the present invention provides a GIP circuit suitable for high resolution display screen, wherein the gate of the transistor T1 is electrically connected to the gate of the transistor T2, the gate of the transistor T1 and the gate of the transistor T2 are all connected to the first gate trace, the source of the transistor T1 is respectively electrically connected to the gate of the transistor T6, the drain of the transistor T7, the source of the transistor T4, the gate of the transistor T5 and one end of the capacitor C1, the source of the transistor T5 is respectively electrically connected to the other end of the capacitor C1 and the drain of the transistor T9, the source of the transistor T5, the other end of the capacitor C1 and the drain of the transistor T9 are all connected to the second gate trace, the gate of the transistor T3 is electrically connected to the gate of the transistor T4, the gate of the transistor T3 and the gate of the transistor T4 are all connected to the third gate trace, so as to increase the voltage at the Q point of the critical node (i.e, the source of the transistor T1 and the common terminal of the transistor T7) in the GIP circuit, therefore, the charge and discharge capacity of the display screen GIP circuit is improved, and the display screen GIP circuit is particularly suitable for high-resolution display screens.
The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.
Claims (4)
1. A GIP circuit suitable for a high-resolution display screen is characterized by comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4 and a capacitor C4, wherein a gate of the transistor T4 is electrically connected with a gate of the transistor T4, a gate of the transistor T4 and a gate of the transistor T4 are connected with a first gate line, a source of the transistor T4 is electrically connected with the gate of the transistor T4, a drain of the transistor T4, a source of the transistor T4, a drain of the transistor T4 and one end of the capacitor C4, a drain of the transistor T4 is electrically connected with the drain of the transistor T4, a gate of the transistor T4, a source of the transistor T4 is electrically connected with the drain of the transistor T4 and a drain of the transistor T4, and the other end of the transistor T4 is electrically connected with the drain of the transistor T4 and the drain of the capacitor C4 and the transistor T4 The other end of the capacitor C1 and the drain of the transistor T9 are both connected to the second gate trace, the gate of the transistor T3 is electrically connected to the gate of the transistor T4, the gate of the transistor T3 and the gate of the transistor T4 are both connected to the third gate trace, the source of the transistor T6 is electrically connected to the source of the transistor T7 and the source of the transistor T9, respectively, and the gate of the transistor T8 is electrically connected to the drain of the transistor T8.
2. The GIP circuit for a high resolution display screen according to claim 1, wherein the gate of the transistor T8, the drain of the transistor T8 and the drain of the transistor T5 are all connected to a clock signal.
3. The GIP circuit for the high resolution display screen according to claim 1, wherein the drain of the transistor T2, the drain of the transistor T3, the source of the transistor T6, the source of the transistor T7 and the source of the transistor T9 are all connected to the negative pole of the power supply.
4. The GIP circuit suitable for a high resolution display screen of claim 1, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8 and the transistor T9 are all N-channel MOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120416769.7U CN215265522U (en) | 2021-02-25 | 2021-02-25 | GIP circuit suitable for high-resolution display screen |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120416769.7U CN215265522U (en) | 2021-02-25 | 2021-02-25 | GIP circuit suitable for high-resolution display screen |
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| Publication Number | Publication Date |
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| CN215265522U true CN215265522U (en) | 2021-12-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112885282A (en) * | 2021-02-25 | 2021-06-01 | 福建华佳彩有限公司 | GIP circuit suitable for high-resolution display screen and control method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112885282A (en) * | 2021-02-25 | 2021-06-01 | 福建华佳彩有限公司 | GIP circuit suitable for high-resolution display screen and control method thereof |
| CN112885282B (en) * | 2021-02-25 | 2024-04-05 | 福建华佳彩有限公司 | GIP circuit suitable for high-resolution display screen and control method thereof |
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