CN215117190U - Clock error measuring device and digital clock - Google Patents
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- CN215117190U CN215117190U CN202121409867.4U CN202121409867U CN215117190U CN 215117190 U CN215117190 U CN 215117190U CN 202121409867 U CN202121409867 U CN 202121409867U CN 215117190 U CN215117190 U CN 215117190U
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Abstract
The application provides a clock error measuring device and a digital clock, and belongs to the field of clock error measurement. The clock error measuring device comprises a GPS receiver, a digital clock and a counter, wherein the GPS receiver is used for acquiring a GPS second pulse signal from a GPS satellite and outputting the GPS second pulse signal; the digital clock is used for outputting a reference pulse per second signal; the counter is electrically connected with the digital clock and the GPS receiver respectively, and is used for receiving the GPS second pulse signal and the reference second pulse signal and obtaining the clock error based on the GPS second pulse signal and the reference second pulse signal. In the scheme, a GPS receiver is used for acquiring and outputting a GPS second pulse signal, a digital clock is used for outputting a reference second pulse signal, and then a counter is used for obtaining a clock error based on the GPS second pulse signal and the reference second pulse signal. The device composed of the GPS receiver, the digital clock and the counter can realize the measurement of the clock error, thereby greatly reducing the cost of measuring the clock error.
Description
Technical Field
The application relates to the technical field of clock difference measurement, in particular to a clock difference measuring device and a digital clock.
Background
In the technical field of radio astronomy, in order to observe a more accurate frequency signal of a celestial body in space, a high-precision clock error processing device needs to be built to correct time information of the celestial body to be measured. At present, the old clock error measuring device is difficult to meet the requirements of practical application, and the high-precision clock error measuring device is often complex in structure and high in cost.
SUMMERY OF THE UTILITY MODEL
The utility model provides a clock error measuring device, digital clock for solve the current high problem of equipment cost that is used for the layer to measure the clock error.
In a first aspect, the present application provides a clock difference measuring apparatus, including a GPS (Global Positioning System) receiver, a digital clock, and a counter, where the GPS receiver is configured to acquire a GPS second pulse signal from a GPS satellite and output the GPS second pulse signal; the digital clock is used for outputting a reference pulse per second signal; the counter is electrically connected with the digital clock and the GPS receiver respectively, and is used for receiving the GPS pulse-per-second signal and the reference pulse-per-second signal and obtaining clock error based on the GPS pulse-per-second signal and the reference pulse-per-second signal.
In the embodiment of the application, a GPS receiver is used for acquiring and outputting a GPS pulse per second signal, a digital clock is used for outputting a reference pulse per second signal, a counter is used for receiving the GPS pulse per second signal and the reference pulse per second signal, and clock offset is obtained based on the GPS pulse per second signal and the reference pulse per second signal. The device composed of the GPS receiver, the digital clock and the counter can realize the measurement of the clock error, thereby greatly reducing the cost of measuring the clock error.
With reference to the technical solution provided by the first aspect, in some possible implementations, the digital clock includes a digital clock body and a phase-locked frequency division module. The digital clock body is used for driving the phase-locking frequency division module; the phase-locked frequency division module is arranged on the digital clock body, is respectively electrically connected with the counter and the digital clock body, and is used for receiving a reference local oscillator sent by a reference clock under the driving of the digital clock body, obtaining the reference pulse-per-second signal based on the reference local oscillator and outputting the reference pulse-per-second signal.
In the embodiment of the application, the digital clock is electrically connected with the reference clock, and the phase-locked frequency division module is arranged in the counter, so that the purposes of receiving the reference local oscillator sent by the reference clock and obtaining the reference pulse-per-second signal based on the reference local oscillator are achieved, the accurate reference pulse-per-second signal is provided for the subsequent clock error calculation, and the accuracy of the finally obtained clock error is further improved.
In combination with the technical solution provided by the first aspect, in some possible implementation manners, the digital clock further includes a signal delay module, the phase-locked frequency division module is electrically connected to the counter through the signal delay module, the signal delay module is electrically connected to the digital clock body, and the signal delay module is configured to perform phase delay correction on the reference pulse-per-second signal output by the phase-locked frequency division module, and output the corrected reference pulse-per-second signal.
In the embodiment of the application, the signal delay module is arranged on the digital clock, so that the phase delay correction of the reference pulse per second signal can be realized, and the correction of the clock error is further realized. Through the signal delay module, the clock difference can be adjusted, so that the obtained clock difference is more accurate.
In combination with the technical solution provided by the first aspect, in some possible implementation manners, the GPS receiver is further configured to receive Time information transmitted by a GPS satellite and output the Time information, the clock difference measuring apparatus further includes an NTP (Network Time Protocol), the NTP module is electrically connected to the GPS receiver, the NTP module is disposed on the digital clock body, and the NTP module is configured to receive the Time information and synchronize the Time information to an electronic device in communication connection with the NTP module.
In the embodiment of the application, the NTP module is used for receiving the time information output by the GPS receiver and coming from the GPS satellite, and after receiving the time information, the NTP module distributes the time information to other equipment and unifies the time of different equipment, so that the obtained clock difference is wider in application range, a plurality of clock difference measuring devices are not required to be arranged, and the cost is further reduced.
With reference to the technical solution provided by the first aspect, in some possible implementation manners, the clock difference measuring device further includes a monitoring unit, the monitoring unit is electrically connected to the counter, and the monitoring unit is configured to determine whether the clock difference obtained by the counter is accurate.
In the embodiment of the application, the clock difference measuring device is further provided with the monitoring unit, the clock difference is monitored through the monitoring unit, whether the clock difference output by the counter is accurate or not is judged, and then a user is helped to judge whether the clock difference meets the use requirement or not, so that the user experience is improved.
In some possible implementation manners, the monitoring unit is further electrically connected to the digital clock, and the monitoring unit is further configured to control the digital clock to adjust the output reference pulse-per-second signal when the clock difference of the counter is not accurate, so as to adjust the clock difference output by the counter.
In the embodiment of the application, the monitoring unit is electrically connected with the digital clock, and when the monitoring unit judges that the clock difference output by the counter is not accurate enough, the digital clock is controlled to adjust the reference pulse per second signal, so that the clock difference is adjusted. The clock difference calibration is realized through the scheme, so that the obtained clock difference signal is more accurate, and the requirement of actual use can be met.
With reference to the technical solution provided by the first aspect, in some possible implementation manners, the monitoring unit is specifically configured to determine whether a clock difference currently output by the counter is within a preset clock difference threshold range, calculate a root mean square of all clock differences obtained by the counter within a preset time length when the clock difference currently output by the counter is within the preset clock difference threshold range, and determine whether the root mean square is within the preset root mean square threshold range; and if the clock offset currently output by the counter is not in the preset clock offset threshold range or the root mean square is not in the preset root mean square threshold range, judging that the clock offset currently output by the counter is inaccurate.
In the embodiment of the application, whether the clock difference currently output by the counter is within a preset clock difference threshold range is judged through the monitoring unit, when the clock difference currently output by the counter is within the preset clock difference threshold range, the root mean square of all clock differences obtained by the counter within a preset time length is calculated, and whether the root mean square is within the preset root mean square threshold range is judged; and if the clock error currently output by the counter is not in the preset clock error threshold range or the root mean square is not in the preset root mean square threshold range, judging that the clock error currently output by the counter is not accurate. According to the scheme, the single clock skew is judged through the preset clock skew threshold range, after the judgment is passed, the root mean square of all the clock skews within the preset time length is judged based on the preset root mean square threshold range, the obtained clock skews are judged in two aspects, and the judgment precision is improved.
In a second aspect, the present application provides a digital clock, including a digital clock body and a phase-locked frequency-dividing module, where the digital clock body is used to drive the phase-locked frequency-dividing module; the phase-locked frequency division module is arranged on the digital clock body, is respectively electrically connected with the counter and the digital clock body, and is used for receiving a reference local oscillator sent by a reference clock under the driving of the digital clock body, obtaining a reference pulse per second signal based on the reference local oscillator and outputting the reference pulse per second signal.
In combination with the technical solution provided by the second aspect, in some possible implementation manners, the digital clock further includes a signal delay module, the phase-locked frequency division module is electrically connected to the counter through the signal delay module, the signal delay module is electrically connected to the digital clock body, and the signal delay module is configured to perform phase delay correction on the reference pulse-per-second signal output by the phase-locked frequency division module, and output the corrected reference pulse-per-second signal.
In combination with the technical solution provided by the second aspect, in some possible implementation manners, the digital clock further includes an NTP module, the NTP module is disposed on the digital clock body, the NTP module is electrically connected to the digital clock body, and the NTP module is configured to receive time information transmitted by a GPS receiver and synchronize the time information to an electronic device communicatively connected to the NTP module.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a block diagram of a clock skew measuring apparatus according to an embodiment of the present disclosure;
fig. 2 is a block diagram of another clock difference measuring apparatus according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of a digital clock according to an embodiment of the present application;
fig. 4 is a block diagram of another digital clock according to an embodiment of the present application.
Icon: 10-clock difference measuring means; 100-a GPS receiver; 200-a digital clock; 210-digital clock body; 220-phase-locked frequency division module; 230-a signal delay module; 240-NTP module; 300-a counter; 400-monitoring unit.
Detailed Description
In the description of the present application, it should be noted that the terms "inside", "outside", "upper", "lower", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally laid out when products of the application are used, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred devices or elements must have specific orientations, be constructed in specific orientations, and be operated, and thus, should not be construed as limiting the present application.
In the description of the present application, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements.
The technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a clock error measuring device 10 according to an embodiment of the present disclosure, which includes a GPS receiver 100, a digital clock 200, and a counter 300.
The GPS receiver (Global Positioning System) 100 is configured to acquire a GPS second pulse signal from a GPS satellite and output the GPS second pulse signal. The digital clock 200 is used to output a reference pulse-per-second signal. The counter 300 is electrically connected to the digital clock 200 and the GPS receiver 100, respectively, and the counter 300 is configured to receive the GPS second pulse signal and the reference second pulse signal and obtain a clock difference based on the GPS second pulse signal and the reference second pulse signal.
In one embodiment, the counter 300 includes at least two signal input interfaces and a processor, the two signal input interfaces are respectively used for receiving the GPS pulse-per-second signal and the reference pulse-per-second signal, and the processor calculates a difference between nearest adjacent rising edges of the GPS pulse-per-second signal and the reference pulse-per-second signal to obtain a clock offset.
The processor may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
In one embodiment, the digital clock 200 includes a digital clock body 210 and a phase-locked frequency-dividing module 220, the phase-locked frequency-dividing module 220 is disposed on the digital clock body 210, and the digital clock body 210 is configured to supply power to the phase-locked frequency-dividing module 220, that is, to provide a voltage required for the operation of the phase-locked frequency-dividing module 220, and to drive the phase-locked frequency-dividing module 220. The phase-locked frequency division module 220 is electrically connected to the counter 300 and the digital clock body 210, and is driven by the digital clock body 210 to receive a reference local oscillator sent by a reference clock, obtain a reference pulse per second signal based on the reference local oscillator, and output the reference pulse per second signal.
In one embodiment, the digital clock body 210 includes a housing and a main board, and the phase-locked frequency division module 220 may be disposed on the main board of the digital clock 200 and electrically connected to the main body of the digital clock 200. The phase-locked frequency division module 220 is powered by the motherboard, and the phase-locked frequency division module 220 responds to the driving signal to work when receiving the driving signal sent by the digital clock 200 main body. It should be noted that the phase-locked frequency division module 220 may be electrically connected to a motherboard in the digital clock body 210 through a communication interface on the digital clock body 210, and receive a driving signal sent by the motherboard through the communication interface.
The phase-locked frequency division module 220 divides the obtained reference local oscillator, uses the divided Pulse Per Second (1pps, 1Pulse Per Second) signal as a reference Pulse Per Second signal, and outputs the reference Pulse Per Second signal, and provides the divided modulated signals with other frequencies (such as 50 hz, 100 hz, 500 hz, etc., without limitation) to the observation terminal for use. In one embodiment, a knob is provided on the digital clock 200, and the modulation signals of other frequencies are adjusted by the knob and output to the observation terminal.
Wherein, the reference clock may be a hydrogen atomic clock.
Optionally, the phase-locked frequency dividing module 220 may be any type of phase-locked frequency dividing module 220, and specific parameters of the phase-locked frequency dividing module 220 may be determined according to actual requirements, for example, the phase-locked frequency dividing module 220 may be a phase-locked frequency dividing module 220 having a frequency input range of 5MHz and 10MHz, a pulse output range of 0.1 pps-1 Mpps, and a pulse amplitude greater than 2.5V. The above examples are merely for ease of understanding the present solution and should not be taken as limiting the present application.
In one embodiment, the digital clock 200 further includes a signal delay module 230, where the signal delay module 230 is disposed on the digital clock body 210, and is electrically connected to the phase-locked frequency dividing module 220, the counter 300, and the digital clock body 210, respectively, for performing phase correction on the reference pulse-per-second signal output by the phase-locked frequency dividing module 220, and outputting the corrected reference pulse-per-second signal. The signal delay amount of the reference pulse-per-second signal output by the phase-locked frequency division module 220 can be adjusted according to actual needs through the signal delay module 230.
In one embodiment, the signal delay module 230 may be disposed on a main board of the digital clock 200 and electrically connected to the main board of the digital clock 200, and the main board supplies power to the signal delay module 230, that is, supplies a voltage required for operation to the signal delay module 230, and when receiving a driving signal sent by the main body of the digital clock 200, the signal delay module 230 operates in response to the driving signal. It should be noted that the signal delay module 230 may be electrically connected to a motherboard in the digital clock body 210 through a communication interface on the digital clock body 210, and receive a driving signal sent by the motherboard through the communication interface.
The signal delay module 230 may adjust a phase of the input reference pulse-per-second signal, and transmit the phase-adjusted reference pulse-per-second signal to the counter 300, so as to adjust the clock difference. The signal delay module 230 may adjust the phase of the reference pulse-per-second signal according to actual requirements, and may advance or delay the time of the rising edge of the reference pulse-per-second signal, for example, may advance or delay the rising edge by 1 microsecond. The example of 1 microsecond is merely for ease of understanding the present solution and should not be taken as limiting the present application.
Optionally, the signal delay module 230 may be any type of signal delay module 230, and specific parameters thereof may be determined according to actual requirements.
In one embodiment, the clock difference measuring apparatus 10 further includes an NTP (Network Time Protocol) module 240, where the NTP module 240 is electrically connected to the GPS receiver 100 and the digital clock body 210, respectively, the GPS receiver 100 is further configured to receive Time information transmitted by a GPS satellite and output the Time information to the NTP module 240, and after receiving the Time information, the NTP module 240 synchronizes the Time information to an electronic device in communication connection with the NTP module 240.
The electronic device may be an electronic device included in the clock difference measuring apparatus 10 itself, or may be other electronic devices, such as a computer and a mobile phone, which are connected to the NTP module 240 in the clock difference measuring apparatus 10 in a communication manner. The time information may be an IRIG (range Instrumentation Group, united states range instrument Group) time code transmitted by the GPS satellites.
Optionally, the NTP module 240 may be disposed on the main body of the digital clock 200, and the NTP module 240 is powered by the main body of the digital clock 200 and is driven to operate. In one embodiment, the NTP module 240 may be disposed on the motherboard of the digital clock 200 and electrically connected to the motherboard of the digital clock 200. The NTP module 240 is powered through the motherboard. It should be noted that the NTP module 240 may be electrically connected to the motherboard in the digital clock body 210 through a communication interface on the digital clock body 210.
In one embodiment, the clock difference measuring apparatus 10 further includes a monitoring unit 400, and the monitoring unit 400 is electrically connected to the counter 300 and is configured to determine whether the clock difference obtained by the counter 300 is accurate.
Optionally, the process of determining whether the clock difference obtained by the counter 300 is accurate by the monitoring unit 400 may be to first determine whether the currently output clock difference of the counter 300 is within a preset clock difference threshold range, calculate a root mean square of all clock differences obtained by the counter 300 within a preset time length when the currently output clock difference of the counter 300 is within the preset clock difference threshold range, and then determine whether the root mean square is within the preset root mean square threshold range. If the currently output clock offset of the counter 300 is not within the preset clock offset threshold range or the root mean square is not within the preset root mean square threshold range, it is determined that the currently output clock offset of the counter 300 is not accurate. If the currently output clock offset of the counter 300 is within the preset clock offset threshold range and the root mean square is within the preset root mean square threshold range, it is determined that the currently output clock offset of the counter 300 is accurate.
The preset clock difference threshold range may be an average value of all clock difference data acquired every day as an accuracy reference, and a certain value floating above and below the average value may be a fixed value, for example, 1 microsecond, 2 microseconds, and the like, or a percentage of the average value, for example, 1%, 2%, 3%, and the like, as a final preset clock difference threshold range. Alternatively, an average value of the clock difference data determined to be accurate among the clock difference data collected every day may be used as the accuracy reference. The above examples are merely for ease of understanding the present solution and should not be taken as limiting the present application.
The preset root-mean-square threshold range may be a root-mean-square of all clock error data acquired every day as an accuracy reference, a certain value may float above and below the root-mean-square as a final preset root-mean-square threshold range, and the certain value may be a fixed value, such as 1 microsecond, 2 microseconds, and the like, or a percentage of the root-mean-square, such as 1%, 2%, 3%, and the like. Alternatively, the root mean square of the clock skew data determined to be accurate from the clock skew data collected every day may be used as the accuracy reference. The above examples are merely for ease of understanding the present solution and should not be taken as limiting the present application.
In one embodiment, the monitoring unit 400 is further electrically connected to the digital clock 200, and is configured to control the digital clock 200 to adjust the output reference pulse-per-second signal when the clock difference obtained by the counter 300 is not accurate, so as to adjust the clock difference output by the counter 300.
Optionally, the monitoring unit 400 may be electrically connected to the signal delay module 230 in the digital clock 200, and when the clock difference obtained by the counter 300 is not accurate, the signal delay module 230 in the digital clock 200 is controlled to perform delay adjustment on the phase of the reference pulse-per-second signal output by the phase-locked frequency division module 220, and the signal delay module 230 outputs the reference pulse-per-second signal after phase adjustment.
For easy understanding, please refer to fig. 2, fig. 2 is a clock difference measuring apparatus 10 provided in an embodiment of the present application, in which the clock difference measuring apparatus 10 includes a GPS receiver 100, a digital clock 200, a counter 300, and a monitoring unit 400.
The GPS receiver 100 is electrically connected to the counter 300 and the NTP module 240 within the digital clock 200, respectively, to transmit the GPS second pulse signal acquired from the GPS satellite to the counter 300 and to transmit the IRIG time code acquired from the GPS satellite to the NTP module 240, so that the NTP module 240 can synchronize the IRIG time code to an electronic device communicatively connected to the NTP module 240.
The counter 300 is electrically connected to the GPS receiver 100, the signal delay module 230 in the digital clock 200, and the monitoring unit 400, respectively, and the counter 300 calculates a clock offset based on the GPS second pulse signal sent by the GPS receiver 100 and the reference second pulse signal sent by the signal delay module 230, and sends the calculated clock offset to the monitoring unit 400, so that the monitoring unit 400 determines whether the clock offset is accurate.
The monitoring unit 400 is further electrically connected to the signal delay module 230 in the digital clock 200, so as to control the signal delay module 230 to adjust the phase of the reference pulse-per-second signal sent by the phase-locked frequency division module 220 when the clock difference obtained by the counter 300 is determined to be inaccurate, thereby making the obtained clock difference more accurate.
In the scheme, the signal delay amount of the reference pulse-per-second signal output by the digital clock 200 can be adjusted, so that the clock error obtained by the counter 300 is changed, meanwhile, the clock error output by the counter 300 is measured in real time through the monitoring unit 400, and when the preset condition is not met, the signal delay amount of the reference pulse-per-second signal is adjusted again, so that the obtained clock error meets the use requirement. Through the scheme, the recording and measuring automation level of the clock error is improved, and the cost for measuring the clock error and the workload of a user are greatly reduced.
The specific structure of the clock difference measuring device 10 and the functions of the different structures are described above for clarity and are not described herein again.
Referring to fig. 3, fig. 3 is a block diagram of a digital clock 200 according to an embodiment of the present disclosure, which includes a digital clock body 210 and a phase-locked frequency-dividing module 220.
The phase-locked frequency-dividing module 220 is disposed on the digital clock body 210, and the digital clock body 210 is configured to supply power to the phase-locked frequency-dividing module 220 and drive the phase-locked frequency-dividing module 220. The phase-locked frequency division module 220 is electrically connected to the counter 300, and is configured to receive a reference local oscillator sent by a reference clock, obtain a reference pulse per second signal based on the reference local oscillator, and output the reference pulse per second signal.
The specific structure of the digital clock 200 and the functions of the different structures are described in detail above, and are not described herein again.
Referring to fig. 4, fig. 4 is a block diagram of a digital clock 200 according to an embodiment of the present disclosure, which includes a digital clock body 210, a phase-locked frequency divider module 220, a signal delay module 230, and an NTP module 240.
The digital clock body 210 is electrically connected to the phase-locked frequency-dividing module 220, the signal delay module 230, and the NTP module 240, respectively, and the phase-locked frequency-dividing module 220 is electrically connected to the signal delay module 230.
The specific structure of the digital clock 200 and the functions of the different structures are described in detail above, and are not described herein again.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A clock skew measuring apparatus, comprising:
the GPS receiver is used for acquiring a GPS second pulse signal from a GPS satellite and outputting the GPS second pulse signal;
a digital clock for outputting a reference pulse-per-second signal;
and the counter is electrically connected with the digital clock and the GPS receiver respectively, and is used for receiving the GPS pulse-per-second signal and the reference pulse-per-second signal and obtaining clock error based on the GPS pulse-per-second signal and the reference pulse-per-second signal.
2. The clock difference measuring apparatus according to claim 1, wherein the digital clock comprises:
the digital clock body is used for driving the phase-locked frequency division module;
the phase-locked frequency division module is arranged on the digital clock body, the phase-locked frequency division module is respectively electrically connected with the counter and the digital clock body, and the phase-locked frequency division module is used for receiving a reference local oscillator sent by a reference clock under the drive of the digital clock body, obtaining the reference pulse-per-second signal based on the reference local oscillator and outputting the reference pulse-per-second signal.
3. The clock difference measuring apparatus according to claim 2, wherein the digital clock further comprises:
the phase-locked frequency division module is electrically connected with the counter through the signal delay module, the signal delay module is electrically connected with the digital clock body, and the signal delay module is used for performing phase delay correction on the reference pulse per second signal output by the phase-locked frequency division module and outputting the corrected reference pulse per second signal.
4. The clock error measurement device of claim 1, wherein the GPS receiver is further configured to receive time information from GPS satellites and output the time information, and further comprising:
and the NTP module is electrically connected with the GPS receiver and used for receiving the time information and synchronizing the time information to an electronic device in communication connection with the NTP module.
5. The clock difference measuring apparatus according to claim 1, further comprising:
and the monitoring unit is electrically connected with the counter and is used for judging whether the clock error obtained by the counter is accurate or not.
6. The clock difference measuring device according to claim 5, wherein the monitoring unit is further electrically connected to the digital clock, and the monitoring unit is further configured to control the digital clock to adjust the output reference pulse per second signal when the clock difference obtained by the counter is not accurate, so as to adjust the clock difference output by the counter.
7. The clock difference measuring device according to claim 5, wherein the monitoring unit is specifically configured to determine whether the clock difference currently output by the counter is within a preset clock difference threshold range, calculate a root mean square of all clock differences obtained by the counter within a preset time length when the clock difference currently output by the counter is within the preset clock difference threshold range, and determine whether the root mean square is within a preset root mean square threshold range; and if the clock offset currently output by the counter is not in the preset clock offset threshold range or the root mean square is not in the preset root mean square threshold range, judging that the clock offset currently output by the counter is inaccurate.
8. A digital clock, comprising:
the digital clock body is used for driving the phase-locked frequency division module;
the phase-locked frequency division module is arranged on the digital clock body, the phase-locked frequency division module is respectively electrically connected with the counter and the digital clock body, and the phase-locked frequency division module is used for receiving a reference local oscillator sent by a reference clock under the drive of the digital clock body, obtaining a reference pulse per second signal based on the reference local oscillator and outputting the reference pulse per second signal.
9. The digital clock of claim 8, further comprising:
the phase-locked frequency division module is electrically connected with the counter through the signal delay module, the signal delay module is electrically connected with the digital clock body, and the signal delay module is used for performing phase delay correction on the reference pulse per second signal output by the phase-locked frequency division module and outputting the corrected reference pulse per second signal.
10. The digital clock of claim 8, further comprising:
the NTP module is arranged on the digital clock body and electrically connected with the digital clock body, and is used for receiving time information transmitted by the GPS receiver and synchronizing the time information to an electronic device in communication connection with the NTP module.
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| CN202121409867.4U CN215117190U (en) | 2021-06-24 | 2021-06-24 | Clock error measuring device and digital clock |
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| CN202121409867.4U CN215117190U (en) | 2021-06-24 | 2021-06-24 | Clock error measuring device and digital clock |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115189796A (en) * | 2022-09-08 | 2022-10-14 | 广州世炬网络科技有限公司 | Equipment master clock synchronization method and device based on IEEE1588 protocol |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115189796A (en) * | 2022-09-08 | 2022-10-14 | 广州世炬网络科技有限公司 | Equipment master clock synchronization method and device based on IEEE1588 protocol |
| CN115189796B (en) * | 2022-09-08 | 2022-12-06 | 广州世炬网络科技有限公司 | Equipment master clock synchronization method and device based on IEEE1588 protocol |
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