CN209949115U - Multi-clock source integrated network time system card - Google Patents

Abstract

The utility model discloses a many clock sources synthesize network time system card, including the FPGA chip, its characterized in that, the FPGA chip is connected with clock source interface and PCI-e interface respectively, the clock source interface includes one or more in antenna interface, IRIG-B sign indicating number input interface, 1PPS signal input interface and the TOD sign indicating number input interface, the antenna interface passes through satellite signal receiver and connects the FPGA chip, IRIG-B sign indicating number input interface 1PPS signal input interface with TOD sign indicating number input interface respectively connects through the driver that corresponds the FPGA chip. The method can be used for time calibration of network communication equipment, supports various clock source coding formats, and ensures the time unification among multiple equipment in different places.

Description

Multi-clock source integrated network time system card

Technical Field

The utility model relates to a network time system card technical field particularly, relates to a network time system card is synthesized to many clock sources.

Background

In many high-speed network applications, for example: industries such as electric power, communication, video, industrial control and the like need to transmit a large number of parameters related to time, and the requirement on time precision is higher and higher along with the technical progress. Meanwhile, the deployment range and the region of the communication equipment are wider and wider, and the time of the whole communication system is required to be uniform. Around the demand for uniform time and high precision time, many enterprises and individuals have developed time-keeping devices or time-keeping cards to meet the demand for uniform time.

Common time synchronization techniques (abbreviated as "time service" or "time calibration") include: short-wave time service, long-wave time service, network time service and satellite time service. The satellite time service has the advantages of high precision, wide coverage range, all-time, all-weather and the like, and is widely applied. And receiving the navigation signal and resolving high-precision time information, so that the equipment which provides high-precision time service by IRIG-B code, TOD code, NTP protocol and serial port output is the time service terminal.

Most of time system equipment and time system cards only need to support satellite time service, and accurate high-precision clocks can be obtained. However, in practical applications, the situation is much more complicated, and in many cases, satellite signals are weak or even completely cannot be received, or sometimes the external antenna is not provided. In these cases, satellite timing is problematic and it is difficult to provide a clock that is stable over time.

In addition, there are other time service options selected by some industries, such as: the mobile communication industry commonly uses 1PPS + TOD code mode to perform clock synchronization. China Mobile communication corporation sets out the enterprise standard QB-B-016-.

The TOD code information baud rate defaults to 9600 without parity, 1 start bit (indicated by low level), 1 stop bit (indicated by high level), idle frame is high level, 8 data bits. The TOD information starts to be transmitted 1ms after the rising edge of 1PPS and is transmitted within 500 ms. The frequency of TOD protocol message transmission is 1 time per second.

For a 1PPS second pulse, a rising edge is used as an on-time edge, the rising time is less than 50ns, the pulse width is 20ms ~ 200ms, TOD information is transmitted in an RS-422 level or RS-232 level mode, and a physical connector adopts RJ45 or DB9 TOD information to express time values of more than seconds through a mode of combining GPS time cycle number and second number in the GPS time cycle.

In other occasions, the time service terminal adopts an IRIG-B code format, and codes the time of year, month, day, hour, minute and second to provide the equipment with calibration time. The interface of IRIG-B Direct Current (DC) codes generally adopts an RS-422 interface. And the interface of the IRIG-B Alternating Current (AC) code adopts a balanced interface. The synchronization precision of the IRIG-B (DC) code can reach dozens of nanoseconds, and the synchronization precision of the IRIG-B (AC) code is generally 10-20 us (microseconds).

Therefore, the problems encountered in the practical application of the existing timing device are as follows:

1) in order to save hardware cost, the common time correction device only adopts one time correction mode. The most common technology is GPS satellite or Beidou satellite timing technology, and the application in most scenes can be met. This timing method (time service technique) has a weak point, and an outdoor antenna must be connected. In some closed environments, or in situations where the satellite signal is weak, it is difficult to ensure continuous timing in this manner. In addition, there is a more general configuration in which a time-master device is provided in the server room to output the time signal to the outside, so as to provide a uniform time reference for other devices. The time format can be IRIG-B code coding format or TOD code coding format. This requires multiple types of cards to accommodate different clock sources. In actual work, due to different conditions all over the country, the types of clock sources are inconsistent, and if various time correction cards or time correction devices are equipped, troubles are brought to device management, and field configuration and maintenance are not facilitated.

2) The problem of clock sharing. Usually, the timing card is only responsible for providing a clock for the local computer, and does not consider external output. If a plurality of devices need accurate timing, a satellite antenna signal amplifier and a distributor are needed, so that the complexity of the devices and wiring is increased, and timing errors are caused.

An effective solution to the problems in the related art has not been proposed yet.

SUMMERY OF THE UTILITY MODEL

To the above-mentioned technical problem among the correlation technique, the utility model provides a many clock sources integrated network time system card can be used to network communication equipment's time calibration, supports multiple clock source coding format, has guaranteed the unity of time between a plurality of equipment strange land.

In order to achieve the technical purpose, the technical scheme of the utility model is realized as follows:

the utility model provides a multi-clock source synthesizes network time system card, includes the FPGA chip, its characterized in that, the FPGA chip is connected with clock source interface and PCI-e interface respectively, the clock source interface includes one or more in antenna interface, IRIG-B sign indicating number input interface, 1PPS signal input interface and the TOD sign indicating number input interface, the antenna interface passes through satellite signal receiver and connects the FPGA chip, IRIG-B sign indicating number input interface, 1PPS signal input interface with the TOD sign indicating number input interface respectively through corresponding driver connection the FPGA chip.

Furthermore, the PCI-e interface is provided with a golden finger which is respectively connected with a power supply and an upper computer.

Furthermore, the FPGA chip is also respectively connected with a constant-temperature crystal oscillator module and a voltage-controlled DAC fine-tuning module.

Furthermore, the FPGA chip is also connected with a common crystal oscillator module.

Furthermore, the FPGA chip is also connected with a Flash memory.

Further, the satellite signal receiver is a GPS receiver or a beidou receiver.

Furthermore, the clock source interface further comprises an IRIG-B code output interface, a 1PPS signal output interface and a TOD code output interface, and the IRIG-B code output interface, the 1PPS signal output interface and the TOD code output interface are respectively connected with the FPGA chip through corresponding drivers.

Further, the IRIG-B code input interface, the 1PPS signal input interface, the TOD code input interface, the IRIG-B code output interface, the 1PPS signal output interface, and the TOD code output interface are all disposed on the SCSI connector.

Further, the driver is an RS422 driver, a TTL driver, or an RS232 driver.

The utility model has the advantages that: the clock with various clock source coding formats such as IRIG-B codes, TOD codes, Beidou/GPS time codes and the like can be received, unified time is obtained through FPGA fusion, a constant-temperature crystal oscillator is adopted to obtain stable oscillation frequency, the constant-temperature crystal oscillator is finely adjusted through a voltage-controlled DAC fine adjustment module, the accuracy of the crystal oscillator frequency is further improved, the device is suitable for various high-precision network communication occasions, one card has multiple functions, and the types of equipment are reduced; clock data in various formats can be output, including IRIG-B code output, TOD code output, 1PPS signal output and the like, and clock sources can be provided for other terminal equipment through various output functions; when the external clock source is absent, the self-defense time error is controlled within 1 day and 10 microseconds.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a circuit block diagram of a multi-clock source integrated network clock system card according to an embodiment of the present invention;

fig. 2 is a circuit diagram of a satellite signal receiver according to an embodiment of the present invention;

fig. 3 is a circuit diagram of an RS422 driver connected to an IRIG-B code input interface according to an embodiment of the present invention;

fig. 4 is a circuit diagram of a TTL driver according to an embodiment of the present invention;

fig. 5 is a circuit diagram of a driver connected to a TOD code input interface according to an embodiment of the present invention;

fig. 6 is a circuit diagram of an RS-422 driver connected to an IRIG-B code output interface according to an embodiment of the present invention;

fig. 7 is a circuit diagram of a driver connected to the TOD code output interface according to an embodiment of the present invention;

fig. 8 is a circuit diagram of a constant temperature crystal oscillator module according to an embodiment of the present invention;

fig. 9 is a circuit diagram of a voltage controlled DAC trim module according to an embodiment of the present invention;

fig. 10 is a first circuit diagram of an FPGA chip according to an embodiment of the present invention;

FIG. 11 is a circuit diagram of an FPGA chip according to an embodiment of the present invention

Fig. 12 is a third circuit diagram of an FPGA chip according to an embodiment of the present invention;

fig. 13 is a circuit diagram of a PCI-e interface according to an embodiment of the present invention;

fig. 14 is a circuit diagram of a power supply according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art all belong to the protection scope of the present invention.

As shown in fig. 1-14, according to the embodiment of the utility model provides a network time system card is synthesized to many clock sources, including the FPGA chip, its characterized in that, the FPGA chip is connected with clock source interface and PCI-e interface respectively, the clock source interface includes one or more in antenna interface, IRIG-B sign indicating number input interface, 1PPS signal input interface and the TOD sign indicating number input interface, the antenna interface passes through satellite signal receiver and connects the FPGA chip, IRIG-B sign indicating number input interface 1PPS signal input interface with TOD sign indicating number input interface respectively connects the FPGA chip through the driver that corresponds.

In an embodiment of the present invention, the PCI-e interface has a golden finger thereon, and the golden finger is connected to the power supply and the upper computer respectively.

In an embodiment of the present invention, the FPGA chip is further connected to the constant temperature crystal oscillator module and the voltage controlled DAC trimming module, respectively.

In a specific embodiment of the present invention, the FPGA chip is further connected to a common crystal oscillator module.

In a specific embodiment of the present invention, the FPGA chip is further connected to a Flash memory.

In a specific embodiment of the present invention, the satellite signal receiver is a GPS receiver or a beidou receiver.

In a specific embodiment of the utility model, the clock source interface still includes IRIG-B sign indicating number output interface, 1PPS signal output interface and TOD sign indicating number output interface, IRIG-B sign indicating number output interface 1PPS signal output interface with TOD sign indicating number output interface respectively connects through the driver that corresponds the FPGA chip.

In a specific embodiment of the present invention, the IRIG-B code input interface the 1PPS signal input interface the TOD code input interface the IRIG-B code output interface the 1PPS signal output interface and the TOD code output interface are all disposed on the SCSI connector.

In a specific embodiment of the present invention, the driver is an RS422 driver, a TTL driver, or an RS232 driver.

For the convenience of understanding the above technical solutions of the present invention, the above technical solutions of the present invention will be described in detail through specific use modes.

The multi-clock source integrated network time system card (abbreviated as network time system card) supports multiple clock sources in circuit design to the current situation in the existing high-speed communication. The hardware of the system card in network time is formed into a block diagram, referring to fig. 1, and the interface part is sequentially from top to bottom:

1) the antenna interface (namely MCX) is used for being connected with an antenna, and the antenna signal is processed by a GPS/Beidou receiver (namely the GPS receiver or the Beidou receiver) to obtain the geographical position information and the absolute clock information. Because the clock on the satellite is an atomic clock and is calibrated by the ground station, the accuracy of the clock transmitted by the satellite is very high. The circuit diagram of the GPS/Beidou receiver is shown in the attached figure 2. The MCX interface signal GNSS _ ANT is input to the 11 th pin of the chip U15, and the chip U15 is processed and then output to the FPGA chip through the TXD pin and the SDA pin. The GPS/Beidou receiver uses a T303 type receiver produced by Thai fighting microelectronics.

2) And an IRIG-B code input interface, wherein the IRIG-B code direct current DC level is an RS-422 level, and the IRIG-B code direct current DC level is accessed to an FPGA chip through the processing of an RS-422 driver. The circuit diagram of the RS422 driver connected with the IRIG-B code input interface is shown in figure 3. External IRIG-B code signals RS-422_ IN0 and RS-422_ IN1 input through the IRIG-B code input interface are converted into standard signals after being processed by the chip U3 and output to the FPGA chip.

3) And the 1PPS signal input interface is connected with the FPGA chip through the TTL driver, and the 1PPS signal level is a TTL level. The circuit diagram of the TTL driver is seen in fig. 4. And the external 1PPS signal input through the 1PPS signal input interface is output to the FPGA after passing through the chip U7. Chip U7 supports bidirectional 8-way drive, and more signal interfaces are reserved for the interface card.

4) And the TOD code signal level is RS-232 level or RS-422 level, and is accessed to the FPGA after being processed by the RS-232 driver or the RS-422 driver. The circuit diagram of the driver connected to the TOD code input interface is shown in fig. 5. If the external TOD code signal input by the TOD code input interface is in an RS-232 level, the external TOD code signal is processed by the chip U9 and output to the FPGA chip, and if the external TOD code signal is in an RS-422 level, the external TOD code signal is processed by the chip U6 and output to the FPGA chip.

After the signals are accessed to the FPGA chip, the FPGA chip respectively decodes the signals to obtain timing data of various clock sources.

If more than two clock sources are configured at a certain node, the FPGA chip can fuse signals of various clock sources and back up the signals mutually.

In principle, the GPS/beidou satellite time, IRIG-B code time, and TOD code time are all transmissions of UTC time (UTC is coordinated universal time, also called universal time, universal standard time, and english abbreviation of international coordinated time), absolute time values should be consistent, and errors between each other do not exceed 1 second. The GPS satellite/Beidou satellite clock signal and the IRIG-B code clock signal are provided with second starting signals, and accurate second starting signals can be obtained through detection by using an FPGA chip; the level change of the 1PPS signal occurs once per second, and is considered as a second start signal, and the level change can be detected.

The absolute time of the three clock sources has the same second value, and the second starting signals may be different, namely, the second starting signals are earlier and later, but the intervals of the second signals are the same and are constant to be one second. According to the two characteristics, after comparison, the FPGA chip takes a clock source with higher stability as a main clock source, and simultaneously takes another clock source as a reference signal, so that fusion and mutual backup of a plurality of clock source signals can be realized.

The network time unified card supports the output of multiple clock source formats, has solved the clock sharing problem. When only one satellite antenna is provided, the satellite antenna can be connected to a network time synchronization card, and after the network time synchronization card accurately corrects time, a clock source signal with various formats is output externally. The following formats may be supported:

1) and (3) outputting an IRIG-B code format, encoding the absolute time according to the B code format by an FPGA chip, adding a second starting signal subjected to signal fusion, converting by an RS-422 driver, and outputting a Direct Current (DC) level signal through an IRIG-B code output interface. The circuit diagram of the RS-422 driver connected with the IRIG-B code output interface is shown in figure 6. The IRIG-B code signal level transmitted by the FPGA chip is converted into RS-422 level after being processed by the chip U8 and is output to external equipment through an IRIG-B code output interface.

2) And (4) outputting the TOD code format, wherein the absolute time is coded by the FPGA chip according to the TOD code format, and is converted into two level signals by an RS-232 driver and an RS-422 driver and then is output through a TOD code output interface. Referring to fig. 7, the TOD signal is processed to RS-232 level by the chip U9 and output to the external device through the TOD code output interface, and is processed to RS-422 level by the chip U10 and output to the external device through the TOD code output interface.

3) 1PPS signal output and level signal output of other frequencies, at the second boundary of absolute time, a high level is output by an FPGA chip and is used as a second starting signal, the width of the high level lasts for more than 20ms, and then the low level is recovered. If the number of high levels per second is once, it is a 1PPS signal. It is also possible to set an arbitrary frequency, i.e., to set the number of high levels. The 1PPS signal output is realized through a TTL driver, the circuit diagram of the TTL driver is shown in figure 4, and the 1PPS signal output by the FPGA chip or the level signal with other frequency is output to external equipment through a 1PPS signal output interface after being processed by a chip U7.

The network time system card still have constant temperature crystal oscillator module and voltage-controlled DAC fine setting module.

The constant-temperature crystal oscillator module adopts an SFN2-MS4RB-10M type constant-temperature crystal oscillator module produced by Beijing upper frequency electronics to output a high-performance 10MHz clock signal and provide a frequency reference for the system. The constant-temperature crystal oscillator module comprises a common crystal oscillator module and a temperature control circuit, and the influence of temperature change on the crystal oscillator frequency is avoided. The FPGA chip obtains millisecond, microsecond and nanosecond values below the second value through counting crystal oscillator signals. The circuit diagram of the constant temperature crystal oscillator module is shown in figure 8.

The clock period for 10MHz is 100 nanoseconds and the count value per second is theoretically 1000 tens of thousands. In practice, it is difficult to reach the theoretical value for industrial manufacturing reasons. The utility model discloses a periodic second initial signal of outside clock source calculates the error of counter, then finely tunes the frequency of crystal oscillator through voltage-controlled DAC fine setting module (be digital fine setting circuit promptly), approaches the theoretical value to reduce the error. The circuit diagram of the voltage controlled DAC trim module is shown in fig. 9.

The core component of system card during network be the FPGA chip, it has chooseed for use compound denier microelectronics FMK50 series FPGA chip. The circuit diagram of the FPGA chip is seen in fig. 10-12.

The FPGA chip can calculate a timing error according to the second starting signal and the counter value, convert the timing error into a fine tuning value of the voltage-controlled DAC fine tuning module and output the fine tuning value, and control the digital-analog conversion circuit to perform fine tuning on the crystal oscillator frequency.

The FPGA chip is connected with a PCI-e bus slot of an upper computer (namely a computer) for the computer through a PCI-e interface, nanosecond-level high-precision clock data can be provided for various application programs in the computer, and the computer sets running parameters of a system card during network through the PCI-e bus.

The network time system card realizes the communication and data exchange with the upper computer through a PCI-e interface and a PCI-e bus. When the computer needs to inquire the current absolute time, an inquiry command is sent to the FPGA chip through the PCI-e bus, and the FPGA chip feeds back the current absolute time second value and the counter value to the computer. Due to the fast speed of the PCI-e bus, the time delay of data transmission between buses can be controlled within 1 microsecond. A circuit diagram of the PCI-e interface is shown in fig. 13.

The power supply is used for supplying power to the network time system card, and the circuit diagram of the power supply is shown in figure 14.

The network time unification card still possess function of keeping watch on, when external clock source all became invalid, rely on the constant temperature crystal oscillator of self to keep the clock value of longer time. Due to the lack of fine tuning of the external signal by the crystal oscillator frequency, cumulative errors can occur. Partial errors are adjusted through a temperature control circuit, and the self-defense time error is controlled within 1 day and 10 microseconds. When in the time keeping state, the IRIG-B code signal and the TOD code signal can still be output.

When the multi-clock source integrated network time system card is used specifically, the PCI-e interface of the multi-clock source integrated network time system card is inserted into a PCI-e bus slot of a computer, and is connected with various external clock sources through an SCSI connector, so that nanosecond-level high-precision clocks can be provided for various application programs of the computer, and time unification under various application environments is realized.

The network time system card has the following characteristics:

1) various clock source coding formats such as IRIG-B codes, TOD codes, Beidou/GPS time codes and the like are supported;

2) the unified time is obtained through FPGA synthesis, and signal fusion is realized and is backup;

3) a constant-temperature crystal oscillator module is adopted to obtain stable oscillation frequency;

4) the constant-temperature crystal oscillator module is finely adjusted through the voltage-controlled DAC fine adjustment module, so that the accuracy of the crystal oscillator frequency can be improved;

5) the time output format is flexible, and IRIG-B code output, TOD code output, 1PPS signal output and the like are supported;

6) the time precision reaches 100 nanoseconds;

7) the system is communicated with a computer through a PCI-e bus interface to realize upper computer control and network communication time service;

8) when the external clock source is absent, the self-defense time error is controlled within 1 day and 10 microseconds.

In conclusion, with the help of the technical scheme of the utility model, can receive multiple clock source coding format clocks such as IRIG-B sign indicating number, TOD sign indicating number, big dipper GPS time code, obtain the uniform time through FPGA fusion, adopt constant temperature crystal oscillator to obtain stable oscillation frequency, finely tune constant temperature crystal oscillator through voltage-controlled DAC fine setting module, further improve the accuracy of crystal oscillator frequency, be fit for various high accuracy network communication occasions, one calorie is multi-functional, has reduced the equipment kind; clock data in various formats can be output, including IRIG-B code output, TOD code output, 1PPS signal output and the like, and clock sources can be provided for other terminal equipment through various output functions; when the external clock source is absent, the self-defense time error is controlled within 1 day and 10 microseconds.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. The utility model provides a multi-clock source synthesizes network time system card, includes the FPGA chip, its characterized in that, the FPGA chip is connected with clock source interface and PCI-e interface respectively, the clock source interface includes one or more in antenna interface, IRIG-B sign indicating number input interface, 1PPS signal input interface and the TOD sign indicating number input interface, the antenna interface passes through satellite signal receiver and connects the FPGA chip, IRIG-B sign indicating number input interface, 1PPS signal input interface with the TOD sign indicating number input interface respectively through corresponding driver connection the FPGA chip.

2. The multi-clock source integrated network time system card of claim 1, wherein a golden finger is provided on the PCI-e interface, and the golden finger is respectively connected to a power supply and an upper computer.

3. The multi-clock-source integrated network time system card of claim 1, wherein the FPGA chip is further connected with a constant temperature crystal oscillator module and a voltage controlled DAC trimming module, respectively.

4. The multi-clock source integrated network clock system card of claim 1, wherein the FPGA chip is further connected to a common crystal module.

5. The multi-clock-source integrated network timing card according to claim 1, wherein the FPGA chip is further connected with a Flash memory.

6. The multi-clock source integrated network time system card of claim 1, wherein the satellite signal receiver is a GPS receiver or a beidou receiver.

7. The multi-clock source integrated network time system card of claim 1, wherein the clock source interface further comprises an IRIG-B code output interface, a 1PPS signal output interface, and a TOD code output interface, and the IRIG-B code output interface, the 1PPS signal output interface, and the TOD code output interface are each connected to the FPGA chip through a corresponding driver.

8. The multi-clock source integrated network time system card of claim 7, wherein the IRIG-B code input interface, the 1PPS signal input interface, the TOD code input interface, the IRIG-B code output interface, the 1PPS signal output interface, and the TOD code output interface are all disposed on the SCSI connector.

9. The multi-clock source integrated network time system card of claim 7, wherein the driver is an RS422 driver, a TTL driver, or an RS232 driver.

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