CN215069952U - Stable-characteristic field effect transistor - Google Patents

Abstract

The utility model provides a field effect transistor with stable characteristics, which comprises an insulation packaging body, wherein an MOS (metal oxide semiconductor) chip, a first current conducting plate, a second current conducting plate and a third current conducting plate are arranged in the insulation packaging body, and the bottom of the first current conducting plate is connected with a ceramic backing plate; a first sealing plate is fixed on the first current conducting plate, a second sealing plate is fixed on the second current conducting plate, and a third sealing plate is fixed on the third current conducting plate; first current conducting plate one end is fixed with first electrically conductive foot, second current conducting plate one end is fixed with second electrically conductive foot, third current conducting plate one end is fixed with third electrically conductive foot, first electrically conductive foot is equipped with first welding through-hole, there is first spacing ring first electrically conductive foot's bottom, second electrically conductive foot is equipped with second welding through-hole, there is the second spacing ring second electrically conductive foot's bottom, third electrically conductive foot is equipped with third welding through-hole, there is the third spacing ring third electrically conductive foot's bottom. The utility model discloses can avoid steam infiltration influence work, and can improve whole heat dispersion, the working property is stable.

Description

Stable-characteristic field effect transistor

Technical Field

The utility model relates to a field effect transistor specifically discloses a stable characteristic's field effect transistor.

Background

The field effect transistor is also called as field effect transistor, belongs to a voltage control type semiconductor device, and has the advantages of high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, wide safe working area and the like.

The common field effect transistor is manufactured by using an MOS (metal oxide semiconductor) chip external pin and injection molding packaging, after the common field effect transistor is welded and installed on a PCB (printed Circuit Board), external water vapor easily reaches the MOS chip along a gap between the pin and an insulating packaging body to influence the work of the common field effect transistor, the heat dissipation performance of the overall structure is poor, and the working characteristics of the field effect transistor in the prior art are easily influenced by the outside.

SUMMERY OF THE UTILITY MODEL

Therefore, it is necessary to provide a field effect transistor with stable characteristics for solving the problems in the prior art, which can effectively avoid the influence of water vapor permeation in the external environment, and has good heat dissipation performance and stable working characteristics in the overall structure.

In order to solve the prior art problem, the utility model discloses a field effect transistor with stable characteristics, including the insulation packaging body, be equipped with the MOS chip in the insulation packaging body, still be equipped with first current conducting plate, second current conducting plate and third current conducting plate in the insulation packaging body, the bottom electrode of MOS chip welds on first current conducting plate, two electrodes in the top of MOS chip are connected with first wire and second wire respectively, the one end that the MOS chip was kept away from to first wire is connected with the second current conducting plate, the one end that the MOS chip was kept away from to the second wire is connected with the third current conducting plate, the bottom of first current conducting plate is connected with the ceramic backing plate, the bottom surface of ceramic backing plate is located the bottom surface below of the insulation packaging body;

a first sealing plate parallel to the side wall of the insulating packaging body is fixed on the periphery of the first current conducting plate, a second sealing plate parallel to the side wall of the insulating packaging body is fixed on the periphery of the second current conducting plate, and a third sealing plate parallel to the side wall of the insulating packaging body is fixed on the periphery of the third current conducting plate;

a first conductive pin is fixed at one end, away from the MOS chip, of the first conductive plate, a second conductive pin is fixed at one end, away from the MOS chip, of the second conductive plate, a third conductive pin is fixed at one end, away from the MOS chip, of the third conductive plate, the first conductive pin, the second conductive pin and the third conductive pin are all located outside the insulating packaging body, a first welding through hole is formed in the first conductive pin, a first limiting ring is fixed at the bottom of the first conductive pin and surrounds the bottom of the first welding through hole, a second welding through hole is formed in the second conductive pin, a second limiting ring is fixed at the bottom of the second conductive pin and surrounds the bottom of the second welding through hole, a third welding through hole is formed in the third conductive pin, a third limiting ring is fixed at the bottom of the third conductive pin and surrounds the bottom of the third welding through hole, the bottom surface and the bottom surface of the first limiting ring, The bottom surface of the second limiting ring, the bottom surface of the third limiting ring and the bottom surface of the ceramic base plate are coplanar.

Furthermore, the first conducting plate comprises a bearing main body and a narrow strip, the MOS tube chip is positioned on the bearing main body, and the first sealing plate is fixed on the periphery of the narrow strip.

Further, the first sealing plate, the second sealing plate and the third sealing plate are all aluminum plates.

Furthermore, the first welding through hole, the second welding through hole and the third welding through hole are all in a convex structure.

Furthermore, the first limiting ring, the second limiting ring and the third limiting ring are all heat-conducting silica gel rings.

The utility model has the advantages that: the utility model discloses a field effect transistor that characteristic is stable, the counterpoint of welded mounting on the PCB board and welding operation are convenient, mounting structure is reliable and stable, the spacing ring can be ensured not to take place the short circuit between each electrically conductive foot, the closing plate can effectively avoid the normal work that the vapor infiltration in the external environment influences the MOS chip, and the ceramic backing plate not only can improve overall structure's heat dispersion with external environment direct contact, can also cooperate three electrically conductive foot to ensure to install the position reliable and stable of field effect transistor behind the PCB board, field effect transistor operating characteristic is stable, be difficult for receiving external influence.

Drawings

Fig. 1 is a schematic view of the three-dimensional structure of the hidden insulating package of the present invention.

Fig. 2 is a schematic top view of the present invention.

Fig. 3 is a schematic cross-sectional view along a-a' in fig. 2.

The reference signs are: the semiconductor package comprises an insulating package body 10, a ceramic pad 11, a MOS chip 20, a first lead 21, a second lead 22, a first conductive plate 30, a bearing body 301, a narrowing strip 302, a first sealing plate 31, a second conductive plate 40, a second sealing plate 41, a third conductive plate 50, a third sealing plate 51, a first conductive pin 60, a first welding through hole 61, a first limiting ring 62, a second conductive pin 70, a second welding through hole 71, a second limiting ring 72, a third conductive pin 80, a third welding through hole 81 and a third limiting ring 82.

Detailed Description

For further understanding of the features and technical means of the present invention, as well as the specific objects and functions attained by the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.

Refer to fig. 1 to 3.

The embodiment of the utility model discloses a field effect transistor with stable characteristics, which comprises an insulation packaging body 10, a MOS chip 20 is arranged in the insulation packaging body 10, a first conductive plate 30, a second conductive plate 40 and a third conductive plate 50 which are parallel to the top wall of the insulation packaging body 10 are also arranged in the insulation packaging body 10, preferably, the second conductive plate 40 and the third conductive plate 50 are arranged at two opposite sides of the first conductive plate 30, the bottom electrode of the MOS chip 20 is welded on the first conductive plate 30, two electrodes at the top of the MOS chip 20 are respectively connected with a first lead 21 and a second lead 22, one end of the first lead 21 far away from the MOS chip 20 is connected with the second conductive plate 40, one end of the second lead 22 far away from the MOS chip 20 is connected with the third conductive plate 50, the bottom of the first conductive plate 30 is connected with a ceramic base plate 11, the bottom surface of the ceramic base plate 11 is arranged below the bottom surface of the insulation packaging body 10, the ceramic backing plate 11 protrudes out of the insulating packaging body 10 and is in direct contact with the external environment, so that the heat of the MOS chip 20 can be efficiently and quickly guided to the external environment, the heat dissipation performance of the whole structure can be effectively improved, and the stability of the working characteristic of the whole structure is ensured;

a first sealing plate 31 parallel to the side wall of the insulating package 10 is fixed around the first conductive plate 30, a second sealing plate 41 parallel to the side wall of the insulating package 10 is fixed around the second conductive plate 40, a third sealing plate 51 parallel to the side wall of the insulating package 10 is fixed around the third conductive plate 50, the first sealing plate 31, the second sealing plate 41 and the third sealing plate 51 are parallel to each other and all located in the insulating package 10, and water vapor can be effectively prevented from entering from a gap between the conductive plate and the insulating package 10 and contacting with the MOS chip 20, so that the sealing and waterproof performance of the whole structure is improved;

a first conductive pin 60 is fixed at one end of the first conductive plate 30 far away from the MOS chip 20, a second conductive pin 70 is fixed at one end of the second conductive plate 40 far away from the MOS chip 20, a third conductive pin 80 is fixed at one end of the third conductive plate 50 far away from the MOS chip 20, the first conductive pin 60, the second conductive pin 70 and the third conductive pin 80 are all located outside the insulating package 10, a first welding through hole 61 penetrating through the upper and lower surfaces is formed in the first conductive pin 60, a first limit ring 62 is fixed at the bottom of the first conductive pin 60, the first limit ring 62 surrounds the periphery of the bottom end of the first welding through hole 61, a second welding through hole 71 penetrating through the upper and lower surfaces is formed in the second conductive pin 70, a second limit ring 72 is fixed at the bottom of the second conductive pin 70, the second limit ring 72 surrounds the periphery of the bottom end of the second welding through hole 71, a third welding through hole 81 penetrating through the upper and lower surfaces is formed in the third conductive pin 80, the bottom of the third conductive pin 80 is fixed with a third limiting ring 82, the third limiting ring 82 surrounds around the bottom of the third welding through hole 81, the first welding through hole 61, the top surfaces of the second welding through hole 71 and the third welding through hole 81 are all led to the external environment, the limiting ring can effectively limit the position of a welding material when being installed on a PCB, the welding through hole can effectively and conveniently inject the welding material to realize the connection between the conductive pin and a PCB pad, the bottom surface of the first limiting ring 62, the bottom surface of the second limiting ring 72, the bottom surface of the third limiting ring 82 and the bottom surface of the ceramic backing plate 11 are coplanar, and the stability of the structural position when being installed on the PCB can be effectively ensured.

The utility model discloses when the application is installed in the PCB board, aim at each pad with three electrically conductive foot, and exert certain pressure and ensure that the spacing ring can effectively compress tightly on the pad surface, counterpoint reliably, and pour into the welding material that possesses mobility such as tin cream into the welding through-hole from the top, convenient operation, the spacing ring that is compressed tightly can effectively restrict the position of the welding material who comes from welding through-hole on it, thereby avoid welding material overflow to all around and lead to the fact the short circuit to take place between each electrically conductive foot, the mounting structure is reliable and stable, can effectively ensure the performance of field effect transistor; can effectively avoid steam to get into the inside of insulating packaging body 10 through the closing plate, and when guaranteeing that three current conducting plate obtains effectual parcel protection, ceramic backing plate 11 can improve the stability of structure when installing in the PCB board, and ceramic backing plate 11 can also effectively improve heat dispersion to effectively reduce the influence that field effect transistor during operation received, can ensure that overall structure's operating characteristic is stable.

In the present embodiment, the first conductive plate 30 includes a carrier body 301 and a narrowing strip 302, the MOS chip 20 is located on the carrier body 301, and the first sealing plate 31 is fixed around the narrowing strip 302, so that the material consumption can be effectively reduced, and at the same time, the MOS chip 20 can have a good carrier base.

In this embodiment, the first sealing plate 31, the second sealing plate 41 and the third sealing plate 51 are all made of aluminum plates, and the aluminum plates have good heat conduction and shielding performance, so that the stable and reliable operating characteristics of the fet can be further ensured.

In this embodiment, the first welding through hole 61, the second welding through hole 71 and the third welding through hole 81 are all in a convex structure, so that the contact area between the welding material in the welding through holes and the external environment can be effectively reduced, and the reliability of the whole structure can be effectively improved.

In this embodiment, the first, second, and third position-limiting rings 62, 72, and 82 are all heat-conducting silica gel rings, which can improve the sealing and flow-blocking performance of the position-limiting rings during pressing installation, and can also effectively improve the heat dissipation performance of the overall structure after installation, and further ensure the stable operating characteristics of the fet.

The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims (5)

1. A field effect transistor with stable characteristics comprises an insulation package body (10), wherein an MOS chip (20) is arranged in the insulation package body (10), and is characterized in that a first conductive plate (30), a second conductive plate (40) and a third conductive plate (50) are further arranged in the insulation package body (10), bottom electrodes of the MOS chip (20) are welded on the first conductive plate (30), two top electrodes of the MOS chip (20) are respectively connected with a first lead (21) and a second lead (22), one end, far away from the MOS chip (20), of the first lead (21) is connected with the second conductive plate (40), one end, far away from the MOS chip (20), of the second lead (22) is connected with the third conductive plate (50), the bottom of the first conductive plate (30) is connected with a ceramic backing plate (11), the bottom surface of the ceramic backing plate (11) is positioned below the bottom surface of the insulating packaging body (10);

a first sealing plate (31) parallel to the side wall of the insulating package body (10) is fixed on the periphery of the first conductive plate (30), a second sealing plate (41) parallel to the side wall of the insulating package body (10) is fixed on the periphery of the second conductive plate (40), and a third sealing plate (51) parallel to the side wall of the insulating package body (10) is fixed on the periphery of the third conductive plate (50);

a first conducting pin (60) is fixed at one end of the first conducting plate (30) far away from the MOS chip (20), a second conducting pin (70) is fixed at one end of the second conducting plate (40) far away from the MOS chip (20), a third conducting pin (80) is fixed at one end of the third conducting plate (50) far away from the MOS chip (20), the first conducting pin (60), the second conducting pin (70) and the third conducting pin (80) are all located outside the insulating packaging body (10), a first welding through hole (61) is formed in the first conducting pin (60), a first limiting ring (62) is fixed at the bottom of the first conducting pin (60), the first limiting ring (62) surrounds the periphery of the bottom end of the first welding through hole (61), a second welding through hole (71) is formed in the second conducting pin (70), and a second limiting ring (72) is fixed at the bottom of the second conducting pin (70), the second spacing ring (72) surround in the bottom of second welding through-hole (71) is all around, be equipped with third welding through-hole (81) in the third electrically conductive foot (80), the bottom of third electrically conductive foot (80) is fixed with third spacing ring (82), third spacing ring (82) surround in the bottom of third welding through-hole (81) is all around, the bottom surface of first spacing ring (62), the bottom surface of second spacing ring (72), the bottom surface of third spacing ring (82) with the bottom surface coplane of ceramic backing plate (11).

2. A fet as claimed in claim 1, wherein the first conductive plate (30) comprises a carrier body (301) and a constriction (302), the MOS chip (20) being located on the carrier body (301), the first sealing plate (31) being secured around the constriction (302).

3. A fet according to claim 1, wherein the first (31), second (41) and third (51) sealing plates are aluminium plates.

4. A stable characteristic fet according to claim 1, wherein the first solder through-hole (61), the second solder through-hole (71) and the third solder through-hole (81) are all of a zigzag structure.

5. The fet of claim 1, wherein the first stop collar (62), the second stop collar (72), and the third stop collar (82) are thermally conductive silicone rings.

Images