CN214898402U - High-power SMD MOS pipe packaging structure - Google Patents
High-power SMD MOS pipe packaging structure Download PDFInfo
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- CN214898402U CN214898402U CN202120925903.6U CN202120925903U CN214898402U CN 214898402 U CN214898402 U CN 214898402U CN 202120925903 U CN202120925903 U CN 202120925903U CN 214898402 U CN214898402 U CN 214898402U
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Abstract
The utility model provides a high-power SMD MOS pipe packaging structure, the insulating packaging is internal to be equipped with MOS tube chip, ceramic lid, first conductive pin, second conductive pin and third conductive pin, the ceramic lid includes the roof, is fixed with the separation sand grip on the roof, is equipped with the first wiring hole of stepping down and the second wiring hole of stepping down that are located the relative both sides of separation sand grip in the roof, the roof bottom is fixed with the curb plate, one side that the MOS tube chip was kept away from to the curb plate is fixed with radiating fin; the first conductive pin comprises a first conductive flat plate and a first conductive vertical plate, and the second conductive pin comprises a second conductive flat plate and a second conductive vertical plate; the separating convex strip is positioned between the first conductive flat plate and the second conductive flat plate, a first conductive hole is formed in the first conductive flat plate, and a second conductive hole is formed in the second conductive flat plate. The utility model discloses can effectively improve heat dispersion, can adapt to high-power work, can effectively avoid the condition of opening circuit to take place, overall structure is reliable firm.
Description
Technical Field
The utility model relates to a MOS pipe specifically discloses a powerful SMD MOS pipe packaging structure.
Background
The MOS transistor is an abbreviation of MOSFET, is called a metal-oxide semiconductor field effect transistor and comprises a grid electrode, a source electrode and a drain electrode, and in most cases, the performance of the device cannot be influenced even if two regions of the drain electrode and the source electrode are exchanged.
The manufacturing method of the surface mount type MOS tube packaging structure is characterized in that three electrodes of an MOS tube chip are connected to three flat pins through leads respectively, and then the three electrodes are packaged into a plastic body to form the surface mount type MOS tube packaging structure, the lead connection structure inside the surface mount type MOS tube packaging structure is easy to generate stress in the injection molding and packaging process, the problems of circuit breaking and the like are easily formed, and the surface mount type structure is poor in heat dissipation performance when the high-power work is performed.
SUMMERY OF THE UTILITY MODEL
Therefore, it is necessary to provide a high-power surface mount type MOS transistor packaging structure, which has good heat dissipation performance, can adapt to the work in a high-power environment, and has a reliable and firm overall structure, in order to solve the problems in the prior art.
In order to solve the prior art problem, the utility model discloses a powerful SMD MOS pipe packaging structure, including the insulating packaging body, be equipped with the MOS chip in the insulating packaging body, ceramic cover, first conductive pin, second conductive pin and third conductive pin, ceramic cover includes the roof, be fixed with the separation sand grip on the roof, be equipped with the first wiring hole of stepping down and the second wiring hole of stepping down that are located the relative both sides of separation sand grip in the roof, at least two edges of roof bottom are fixed with the curb plate, the curb plate surrounds outside the MOS chip, one side that every curb plate kept away from the MOS chip all is fixed with a plurality of radiating fin, first wiring hole of stepping down and second wiring hole are located two electrodes at the top of MOS chip respectively;
the first conductive pin comprises a first conductive flat plate and a first conductive vertical plate, the first conductive vertical plate is fixed on one side, away from the MOS chip, of the first conductive flat plate, the second conductive pin comprises a second conductive flat plate and a second conductive vertical plate, the second conductive vertical plate is fixed on one side, away from the MOS chip, of the second conductive flat plate, the third conductive pin comprises a third conductive flat plate and a third conductive vertical plate, and the third conductive vertical plate is fixed on one side, away from the MOS chip, of the third conductive flat plate;
the first conductive flat plate and the second conductive flat plate are both positioned on the top plate, the separation convex strip is positioned between the first conductive flat plate and the second conductive flat plate, a first conductive hole connected to the top of the first wiring yielding hole is formed in the first conductive flat plate, a second conductive hole connected to the top of the second wiring yielding hole is formed in the second conductive flat plate, a first conductive body is arranged in the first conductive hole and the first wiring yielding hole, a second conductive body is arranged in the second conductive hole and the second wiring yielding hole, the first conductive body is connected with one electrode at the top of the first conductive flat plate and the top of the MOS chip, the second conductive body is connected with the other electrode at the top of the second conductive flat plate and the top of the MOS chip, and the bottom electrode of the MOS chip is connected to the third conductive flat plate.
Further, one side of the side plate close to the MOS tube chip is covered with an anti-collision layer.
Furthermore, one side of the first conductive vertical plate, which is close to the MOS chip, is covered with a first insulating layer, and one side of the second conductive vertical plate, which is close to the MOS chip, is covered with a second insulating layer.
Furthermore, a first welding foot plate is fixed on one side, away from the MOS chip, of the first conductive vertical plate, a second welding foot plate is fixed on one side, away from the MOS chip, of the second conductive vertical plate, and a third welding foot plate is fixed on one side, away from the MOS chip, of the third conductive vertical plate.
Furthermore, one side of the first welding foot plate, which is far away from the first conductive vertical plate, is provided with a first yielding groove, one side of the second welding foot plate, which is far away from the second conductive vertical plate, is provided with a second yielding groove, and one side of the third welding foot plate, which is far away from the third conductive vertical plate, is provided with a third yielding groove.
The utility model has the advantages that: the utility model discloses a powerful SMD MOS pipe packaging structure, the setting possesses the ceramic lid structure that special wall heat dispersion ability, not only can effectively improve the heat dispersion of MOS chip, overall structure can adapt to the work of high-power environment, and the electric conductor of being wrapped up in the electrically conductive hole and the wiring hole of stepping down is hardly influenced by stress when encapsulating of moulding plastics, can effectively improve inside electrically conductive structure's reliability, the condition that can effectively avoid opening circuit takes place, overall structure is reliable and firm, furthermore, the setting of separating the sand grip can avoid two electrically conductive dull and stereotyped contact short circuits, can make things convenient for going on of electrically conductive dull and stereotyped counterpoint operation, radiating fin approaches the heat dispersion that can further improve overall structure, can also compensate the defect that the smooth adhesive force in ceramic lid surface is low, overall structure's stability can be ensured.
Drawings
Fig. 1 is a schematic view of the internal structure of the present invention.
Fig. 2 is the utility model discloses split structure schematic diagram behind the hidden insulating packaging body.
The reference signs are: the package comprises an insulating package body 10, a MOS chip 20, a first conductor 21, a second conductor 22, a ceramic cover 30, a top plate 31, a first wiring yielding hole 311, a second wiring yielding hole 312, a partition convex strip 32, a side plate 33, a heat dissipation fin 34, an anti-collision layer 341, a first conductive pin 40, a first conductive flat plate 41, a first conductive hole 411, a first conductive vertical plate 42, a first insulating layer 421, a first solder plate 43, a first yielding groove 431, a second conductive pin 50, a second conductive flat plate 51, a second conductive hole 511, a second conductive vertical plate 52, a second insulating layer 521, a second solder plate 53, a second yielding groove 531, a third conductive pin 60, a third conductive flat plate 61, a third conductive vertical plate 62, a third solder plate 63, and a third yielding groove 631.
Detailed Description
For further understanding of the features and technical means of the present invention, as well as the specific objects and functions attained by the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
Refer to fig. 1 and 2.
The embodiment of the utility model discloses a powerful SMD MOS pipe packaging structure, including insulating packaging body 10, be equipped with MOS chip 20 in insulating packaging body 10, ceramic lid 30, first conductive pin 40, second conductive pin 50 and third conductive pin 60, MOS chip 20 is located third conductive pin 60, ceramic lid 30 is located MOS chip 20, first conductive pin 40 and second conductive pin 50 are located the relative both sides of third conductive pin 60 respectively, ceramic lid 30 includes roof 31, be fixed with on roof 31 and separate sand grip 32, be equipped with in the roof 31 and be located the first wiring hole of stepping down 311 and the second wiring hole of stepping down 312 of separating sand grip 32 relative both sides, at least two edges of roof 31 bottom are fixed with curb plate 33, preferably, two at least curb plates 33 distribute in the relative both edges of roof 31, curb plate 33 centers on outside the side of MOS chip 20, a plurality of radiating fins 34 are fixed on one side of each side plate 33, which is far away from the MOS chip 20, the top plate 31, the separating convex strip 32, the side plate 33 and the radiating fins 34 are all of ceramic structures, and have good radiating performance and insulating performance, preferably, the top plate 31, the separating convex strip 32, the side plate 33 and the radiating fins 34 are of an integrally formed structure, and the first wiring abdicating hole 311 and the second wiring abdicating hole 312 are respectively located on two electrodes at the top of the MOS chip 20;
the first conductive pin 40 includes a first conductive flat plate 41 and a first conductive riser 42 which are integrally formed, the first conductive riser 42 is fixed to the bottom of the first conductive flat plate 41 on the side away from the MOS chip 20, the second conductive pin 50 includes a second conductive flat plate 51 and a second conductive riser 52 which are integrally formed, the second conductive riser 52 is fixed to the bottom of the second conductive flat plate 51 on the side away from the MOS chip 20, the third conductive pin 60 includes a third conductive flat plate 61 and a third conductive riser 62 which are integrally formed, the third conductive riser 62 is fixed to the bottom of the third conductive flat plate 61 on the side away from the MOS chip 20, and the bottoms of the first conductive riser 42, the second conductive riser 52 and the third conductive riser 62 all protrude below the bottom of the insulating package 10, so that the MOS can be effectively connected with external structures such as a PCB;
the first conductive plate 41 and the second conductive plate 51 are both located on the top plate 31, the separation protruding strip 32 is located between the first conductive plate 41 and the second conductive plate 51, a first conductive hole 411 connected to the top of the first wire receding hole 311 is formed in the first conductive plate 41, a second conductive hole 511 connected to the top of the second wire receding hole 312 is formed in the second conductive plate 51, a first conductive body 21 is arranged in the first conductive hole 411 and the first wire receding hole 311, a second conductive body 22 is arranged in the second conductive hole 511 and the second wire receding hole 312, preferably, the first conductive body 21 and the second conductive body 22 may be both solder conductive bodies, the first conductive body 21 is connected to the first conductive plate 41 and one electrode on the top of the MOS chip 20, the second conductive body 22 is connected to the second conductive plate 51 and the other electrode on the top of the MOS chip 20, and the bottom electrode of the MOS chip 20 is connected to the third conductive plate 61 through a conductive material such as solder.
When the utility model is manufactured, the bottom electrode of the MOS chip 20 is welded on the third conductive flat plate 61, then the ceramic cover 30 is placed on the MOS chip 20, the two side plates 33 are limited on the two sides of the MOS chip 20 to realize alignment, and the first wiring abdicating hole 311 and the second wiring abdicating hole 312 are respectively aligned with the two electrodes on the top of the MOS chip 20; then, the first conductive plate 41 and the second conductive plate 51 are aligned to the two opposite sides of the partition rib 32, respectively, and are placed on the top plate 31, the first conductive hole 411 is aligned to the first wiring relief hole 311, and the second conductive hole 511 is aligned to the second wiring relief hole 312; a first conductor 21 for connecting the first conductive plate and one electrode on the top of the MOS chip 20 is formed by injecting a conductive material such as solder into the first conductive hole 411, and a second conductor 22 for connecting the second conductive plate and the other electrode on the top of the MOS chip 20 is formed by injecting a conductive material such as solder into the second conductive hole 511; and finally, placing the components with the internal conductive connection into an injection mold for injection molding and packaging to obtain the reliable insulating packaging body 10.
In the utility model, the ceramic cover 30 is coated outside the MOS chip 20, which can effectively improve the heat dissipation performance of the MOS chip 20 during operation and avoid the influence on the working performance of the MOS chip 20 due to heat accumulation; the first conductive flat plate 41 and the second conductive flat plate 51 are attached to the top plate 31 and are respectively conducted with two electrodes at the top of the MOS chip through the first conductor 21 and the second conductor 22, the connection between the electrodes and the conductive pins of the MOS chip 20 is not needed to be realized by using leads, the conductors wrapped in the conductive holes and the wiring yielding holes are hardly affected by stress during injection molding and packaging, and the reliability of an internal conductive wiring structure can be effectively improved; the separation convex strips 32 can effectively avoid short circuit between two conductive flat plates, effectively simplify the alignment operation, improve the manufacturing efficiency and reduce the manufacturing difficulty; radiating fin 34 can further improve the heat dispersion of MOS chip 20, and because ceramic lid 30 surface is smooth, and is hanged down by the adhesive force, radiating fin 34 protrudes the stability of the structure between ceramic lid 30 and insulating packaging body 10 can effectively be improved to the effect of screens to effectively improve overall structure's fastness.
In this embodiment, a side of the side plate 33 close to the MOS chip 20 is covered with the anti-collision layer 341, and the anti-collision layer 341 can effectively avoid the side plate 33 from damaging the MOS chip 20, and preferably, the anti-collision layer 341 is a thermal conductive silica gel layer, has good elasticity, thermal conductivity and insulation property, and can effectively ensure the heat dissipation performance of the MOS chip 20.
In this embodiment, a first insulating layer 421 covers a side of the first conductive riser 42 close to the MOS chip 20, and a second insulating layer 521 covers a side of the second conductive riser 52 close to the MOS chip 20, so that the conductive riser can be effectively prevented from short-circuiting the upper and lower electrodes of the MOS chip 20 by the first insulating layer 421 and the second insulating layer 521.
In this embodiment, a first bonding pad 43 is fixed on a side of the first conductive riser 42 away from the MOS chip 20, a second bonding pad 53 is fixed on a side of the second conductive riser 52 away from the MOS chip 20, a third bonding pad 63 is fixed on a side of the third conductive riser 62 away from the MOS chip 20, the first bonding pad 43, the second bonding pad 53, and the third bonding pad 63 are all located below the insulating package 10, the first bonding pad 43 and the second bonding pad 53 are located on the same side of the MOS chip 20, and the third bonding pad 63 is located on the other side of the MOS chip 20, so that a sufficient distance can be formed between the bonding pads, and short circuit can be avoided when the bonding pads are welded to a PCB.
Based on the above embodiment, the first stepping down groove 431 is formed in the side, away from the first conductive vertical plate 42, of the first foot welding plate 43, the second stepping down groove 531 is formed in the side, away from the second conductive vertical plate 52, of the second foot welding plate 53, the third stepping down groove 631 is formed in the side, away from the third conductive vertical plate 62, of the third foot welding plate 63, the area, to which solder paste can adhere, of the solder paste when the solder paste is welded on a PCB can be increased through the stepping down grooves, and the firmness of the welding installation structure can be effectively improved.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (5)
1. A high-power patch type MOS tube packaging structure comprises an insulating packaging body (10), and is characterized in that an MOS tube chip (20), a ceramic cover (30), a first conductive pin (40), a second conductive pin (50) and a third conductive pin (60) are arranged in the insulating packaging body (10), the ceramic cover (30) comprises a top plate (31), a separation convex strip (32) is fixed on the top plate (31), a first wiring abdicating hole (311) and a second wiring abdicating hole (312) which are positioned at two opposite sides of the separation convex strip (32) are arranged in the top plate (31), at least two edges of the bottom of the top plate (31) are fixed with side plates (33), the side plates (33) surround the MOS tube chip (20), and a plurality of radiating fins (34) are fixed on one side of each side plate (33) far away from the MOS tube chip (20), the first wiring yielding hole (311) and the second wiring yielding hole (312) are respectively positioned on the two electrodes at the top of the MOS chip (20);
the first conductive pin (40) comprises a first conductive flat plate (41) and a first conductive riser (42), the first conductive riser (42) is fixed on one side of the first conductive flat plate (41) far away from the MOS chip (20), the second conductive pin (50) comprises a second conductive flat plate (51) and a second conductive riser (52), the second conductive riser (52) is fixed on one side of the second conductive flat plate (51) far away from the MOS chip (20), the third conductive pin (60) comprises a third conductive flat plate (61) and a third conductive riser (62), and the third conductive riser (62) is fixed on one side of the third conductive flat plate (61) far away from the MOS chip (20);
the first conductive flat plate (41) and the second conductive flat plate (51) are both located on the top plate (31), the separation convex strip (32) is located between the first conductive flat plate (41) and the second conductive flat plate (51), a first conductive hole (411) connected to the top of the first wiring abdicating hole (311) is arranged in the first conductive flat plate (41), a second conductive hole (511) connected to the top of the second wiring abdicating hole (312) is arranged in the second conductive flat plate (51), a first conductive body (21) is arranged in the first conductive hole (411) and the first wiring abdicating hole (311), a second conductive body (22) is arranged in the second conductive hole (511) and the second wiring abdicating hole (312), the first conductive body (21) is connected with the first conductive flat plate (41) and an electrode at the top of the MOS chip (20), the second conductor (22) connects the second conductive plate (51) and the other electrode on the top of the MOS chip (20), and the bottom electrode of the MOS chip (20) is connected to the third conductive plate (61).
2. A high power chip-type MOS transistor package structure according to claim 1, wherein a side of the side plate (33) close to the MOS chip (20) is covered with an anti-collision layer (341).
3. A high power patch-type MOS transistor package structure according to claim 1, wherein a side of the first conductive riser (42) close to the MOS chip (20) is covered with a first insulating layer (421), and a side of the second conductive riser (52) close to the MOS chip (20) is covered with a second insulating layer (521).
4. A high power patch-type MOS transistor package structure according to claim 1, wherein a first bonding pad (43) is fixed to a side of the first conductive riser (42) away from the MOS chip (20), a second bonding pad (53) is fixed to a side of the second conductive riser (52) away from the MOS chip (20), and a third bonding pad (63) is fixed to a side of the third conductive riser (62) away from the MOS chip (20).
5. The high-power patch-type MOS tube packaging structure according to claim 4, wherein a first yielding groove (431) is formed on one side, away from the first conductive vertical plate (42), of the first solder plate (43), a second yielding groove (531) is formed on one side, away from the second conductive vertical plate (52), of the second solder plate (53), and a third yielding groove (631) is formed on one side, away from the third conductive vertical plate (62), of the third solder plate (63).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120925903.6U CN214898402U (en) | 2021-04-30 | 2021-04-30 | High-power SMD MOS pipe packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120925903.6U CN214898402U (en) | 2021-04-30 | 2021-04-30 | High-power SMD MOS pipe packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214898402U true CN214898402U (en) | 2021-11-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120925903.6U Active CN214898402U (en) | 2021-04-30 | 2021-04-30 | High-power SMD MOS pipe packaging structure |
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|---|---|
| CN (1) | CN214898402U (en) |
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2021
- 2021-04-30 CN CN202120925903.6U patent/CN214898402U/en active Active
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Effective date of registration: 20230508 Address after: No. 9, Yinpingxu Lane, Liaobu Town, Dongguan City, Guangdong Province, 523000 Patentee after: Dongguan Taifeng Radio Frequency Identification Co.,Ltd. Address before: 523430 Room 101, building 1, 76 Baiye Road, Liaobu Town, Dongguan City, Guangdong Province Patentee before: DONGGUAN ZHONGZHI ELECTRONIC TECHNOLOGY CO.,LTD. |