CN214895656U - Display chip test equipment - Google Patents

Abstract

The utility model provides a display chip test equipment relates to display chip test technical field, include: the processor is electrically connected with the display card module, the display card module is electrically connected with the image storage module, a test interface connected with the display card module is further arranged on the circuit board, when in test, the packaged display chip can be inserted into the test interface on the shell, so that the display card module can call data information pre-stored in the image storage module and then drive the packaged display chip to display a corresponding image through the display card module, the verification of the display characteristics of the packaged display chip is completed, whether the packaged display chip is qualified is judged, the normal display characteristics of the packaged display chip after leaving the factory are further ensured, and the quality of products leaving the factory is further improved. Meanwhile, when the display characteristics of the packaged display chip are tested by the display chip testing equipment, the packaged display chip can be automatically tested by matching with a testing program such as a processor and a display card module, so that the testing efficiency can be improved.

Description

Display chip test equipment

Technical Field

The utility model relates to a display chip tests technical field, particularly, relates to a display chip test equipment.

Background

After wire bonding and packaging of a finished product, an LCoS display chip firstly needs to be tested systematically to test electrical characteristics, and at present, the electrical characteristic testing method for the packaged LCoS display chip is more traditional, and needs to manually test indexes such as wire bonding on-off, power supply open short circuit and power consumption step by step and also needs to manually record test data. Meanwhile, in view of the application scenario of the packaged LCoS display chip, a preliminary test needs to be performed on the display effect of the packaged LCoS display chip. Aiming at the particularity of the packaged LCoS display chip, more test accompanying equipment is required when the display characteristic of the packaged LCoS display chip is tested at present, so that the test cost is higher and the test efficiency is lower.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a display chip test equipment to the not enough among the above-mentioned prior art to improve the current problem that test cost is higher and efficiency of software testing is lower when showing the chip test to encapsulated LcoS.

In order to achieve the above object, the embodiment of the present invention adopts the following technical solutions:

the utility model provides an aspect provides a display chip test equipment, include: the display card comprises a shell and a circuit board arranged in the shell, wherein a processor, a display card module and an image storage module are arranged on the circuit board; the processor is electrically connected with the display card module, the display card module is electrically connected with the image storage module, and the circuit board is also provided with a test interface connected with the display card module and used for plugging the packaged display chip so that the processor controls the display card module to call data information in the image storage module and then drives the packaged display chip to display images.

Optionally, the data information includes a plurality of sets of frame rate image information, and the display card module is configured to call frame rate image information matched with the instruction information according to the instruction information of the processor to drive the packaged display chip to display the image at the corresponding frame rate.

Optionally, the display card module includes a display memory module and a display driver module electrically connected to each other, the processor is electrically connected to the display memory module, the image storage module is electrically connected to the display memory module, and the display driver module is connected to the test interface.

Optionally, the display card power supply module is located in a second branch of the main power supply module, so that the main power supply module supplies power to the display card module through the display card power supply module.

Optionally, an analog-to-digital converter connected to the processor is further disposed on the circuit board, and the analog-to-digital converter is connected to the packaged display chip and is configured to collect current information of the packaged display chip.

Optionally, a current amplifier is further disposed between the analog-to-digital converter and the packaged display chip.

Optionally, the testing device further comprises a routing on-off detection module and a change-over switch, the routing on-off detection module is connected with a first contact of the change-over switch, the display card module is connected with a second contact of the change-over switch, the change-over switch is connected with the testing interface, an indicator lamp is further arranged on a connecting line of the routing on-off detection module and the first contact of the change-over switch, and the processor is electrically connected with the change-over switch and used for switching the communication state of the routing on-off detection module, the display card module and the testing interface.

Optionally, the portable electronic device further comprises a display screen, wherein the display screen is arranged on one side of the shell and is electrically connected with the processor.

Optionally, a data interface is further disposed on the circuit board, and the data interface is electrically connected to the processor.

Optionally, a communication interface is further disposed on the circuit board, and the communication interface is electrically connected to the processor.

The beneficial effects of the utility model include:

the utility model provides a display chip test equipment, include: the display card comprises a shell and a circuit board arranged in the shell, wherein a processor, a display card module and an image storage module are arranged on the circuit board; the processor is electrically connected with the display card module, the display card module is electrically connected with the image storage module, a test interface connected with the display card module is further arranged on the circuit board, when in test, the packaged display chip can be inserted into the test interface on the shell, meanwhile, the display chip test equipment is started, at the moment, the processor drives the display card module according to a test instruction and following a test program, so that the display card module can call data information pre-stored in the image storage module and then drives the packaged display chip to display a corresponding image by the display card module, the verification of the display characteristics of the packaged display chip is completed, whether the packaged display chip is qualified is judged, the normal display characteristics of the packaged display chip after leaving the factory are ensured, and the quality of the product when leaving the factory is improved. Meanwhile, when the display characteristics of the packaged display chip are tested by the display chip testing equipment, the packaged display chip can be automatically tested by matching with a testing program such as a processor and a display card module, so that the testing efficiency can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a display chip testing apparatus according to an embodiment of the present invention;

fig. 2 is a second schematic structural diagram of a display chip testing apparatus according to an embodiment of the present invention;

fig. 3 is a third schematic structural diagram of a display chip testing apparatus according to an embodiment of the present invention;

fig. 4 is a fourth schematic diagram of a display chip testing apparatus according to an embodiment of the present invention.

Icon: 01-display chip test equipment; 02-PC terminal; 110-a processor; 120-a display card module; 121-a video memory module; 122-display driving module; 130-a test interface; 140-an image storage module; 150-LCoS display chip; 161-a first contact; 162-a second contact; 170-indicator light; 180-routing on-off detection module; 210-a main power supply module; 220-a processor power module; 230-video memory power supply module; 240-display driving power supply module; 260-IC power supply module; 270-a communication interface; 280-a data interface; 290-display.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. It should be noted that, in the case of no conflict, various features in the embodiments of the present invention may be combined with each other, and the combined embodiments are still within the scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The LCoS display chip 150 is finished after the wire bonding packaging finished product is finished, firstly, the electrical characteristics are systematically tested, the display images are different in view of different application scenes of the packaged LCoS display chip 150, the electrical characteristic test should include preliminarily testing the display effect of the packaged LCoS display chip under the premise of different display images, and thus, the normal display characteristics of the packaged display chip can be ensured, and the yield of the product when leaving the factory is improved.

The embodiment of the utility model provides an aspect provides a display chip test equipment 01, as shown in FIG. 1, this equipment includes the casing, then at the inside circuit board that is provided with of this casing, integrate treater 110, display card module 120 and image storage module 140 on the circuit board, wherein, as shown in FIG. 2, treater 110 is connected with display card module 120 electricity, display card module 120 is connected with image storage module 140 electricity, still be provided with the test interface 130 of being connected with display card module 120 on the circuit board, foretell electric connection mode can be between the different modules through the metal wire on the circuit board carry out the electricity and connect. In this manner, the display test hardware in the packaged display chip test apparatus 01 is formed. To facilitate testing, the test interface 130 may also be disposed on the housing with the interface oriented toward the exterior of the housing. The packaged display chip may be an LCoS display chip 150.

During testing, the packaged display chip may be inserted into the test interface 130 on the housing, and at the same time, the display chip testing device 01 is started, at this time, the processor 110 drives the graphics card module 120 according to the test instruction following the test program, so that the graphics card module 120 can call data information pre-stored in the image storage module 140 and then drive the packaged display chip to display a corresponding image by the graphics card module 120, thereby completing verification of the display characteristics of the packaged display chip, determining whether the packaged display chip is qualified, further ensuring the normal display characteristics of the packaged display chip after leaving the factory, and further improving the quality of the product when leaving the factory. Meanwhile, when the display chip testing device 01 performs a display characteristic test on the packaged display chip, the processor 110, the graphics card module 120, and the like can be used in cooperation with a test program to perform an automated test, so that the testing efficiency can be improved.

The test command may be a button provided on the housing as shown in fig. 1, and when a test is required, the button on the housing controls the processor 110 to start the test program, or the terminal may control the processor 110 to execute the test program by issuing the test command. In addition, a Gamma value knob may be disposed on the housing and electrically connected to the processor 110, so that when the Gamma value knob is adjusted, the processor 110 may obtain a corresponding signal, and then adjust the packaged display chip to perform corresponding display, thereby detecting the display performance of the packaged display chip. A timing knob may be further provided, and the processor 110 may perform a continuous test on the packaged display chip within a certain time range through adjustment of the timing knob, so as to perform an aging test. The processor 110 may be an ARM processor 110 and the test interface 130 may be an FPC test interface 130.

Optionally, in practical use of the packaged display chip, images with different frame rates are generally required to be correspondingly displayed according to different application scenarios, so that a test of display characteristics of the packaged display chip with different frame rates is necessary. In an actual test, a plurality of sets of frame rate image information may be stored in the image storage module 140 as data information, and the plurality of sets of frame rate image information may be a plurality of sets of frame rate image information with different frame rates, or a plurality of sets of frame rate image information with different colors. In this way, the processor 110 can perform the test according to the test requirement, for example, when the packaged display chip needs to be subjected to the display test of images with different frame rates, the processor 110 may issue the first command information to the graphic card module 120 according to the test program, and at this time, the display card module 120 retrieves the first frame rate image information matched with the first instruction information according to the first instruction information, and drives the packaged display chip to display the first frame rate image, then, the processor 110 continues to send the second instruction information to the graphics card module 120, at this time, the graphics card module 120 retrieves the second frame rate image information matched with the second instruction information according to the second instruction information, and drives the packaged display chip to display the second frame rate image, the first frame rate image and the second frame rate image have different frame rates, and so on, the display of the image at the third frame rate, the display of the image at the fourth frame rate, and so on may also be performed. Therefore, the testing of the image display characteristics of the packaged display chip with different frame rates can be realized in the actual testing, so that the testing of the image display characteristics of the packaged display chip with different frame rates can be finished before delivery, and the quality of products delivered from a factory is improved.

Optionally, as shown in fig. 3, the video card module 120 may include a video memory module 121 and a display driver module 122 electrically connected to each other, wherein the processor 110 is electrically connected to the video memory module 121, the image storage module 140 is electrically connected to the video memory module 121, and the display driver module 122 is connected to the test interface 130, so that when the processor 110 sends instruction information to the video card module 120, the video memory module 121 reads data information stored in the image storage module 140 according to the instruction information, and further converts the data information into an RGB image data stream, and outputs the RGB image data stream to the display driver module 122, and then the display driver module 122 converts the RGB image data stream into a time-series image data stream, and outputs the time-series image data stream to an inserted packaged display chip through the test interface 130, so that the display chip displays a corresponding image. In the testing process, the processor 110 may be enabled to start different testing programs according to the testing instruction, for example, to test display characteristics of the packaged display chip, display characteristics of images with different frame rates, display characteristics of images with different colors, and so on, so that a plurality of testing items can be implemented by the display chip testing apparatus 01. The problem that when the traditional LCoS display chip 150 is subjected to image display tests at different frame rates, various test tool equipment is required to accompany the tests, so that the connection is complex and the cost is high is solved.

Due to the particularity of the interface protocol of the LCoS display chip 150, protocol conversion needs to be performed by the display driver module 122, and reference may be made to the following 2 embodiments:

the first scheme is as follows:

the FPGA + DDR programming design can be selected, as the source is 1080P image data, the frame rate of the image data output after FPGA processing needs to be as high as 360Hz to meet the display test requirement of the LCoS display chip 150, and the selected FPGA and DDR need to meet the high-speed requirement. The standard RGB data stream of source is received through the FPGA algorithm, and is stored in the DDR according to a certain data format, the DDR plays a role in data caching, and then the data stream of a specific format is output to the LCoS display chip 150 through the FPGA for display, the frame rate of the output image data is improved relative to the source, the image color information is converted into time sequence color, and meanwhile, the FPGA can be controlled through key operation to output display images of different frame rates.

Sequential color refers to separating three color bits of image pixels RGB into R, G, B three color frames according to image frame, and converting the conventional spatial color sequence into sequential color sequence.

Scheme II:

and an LCoS driving chip is selected for converting the image space color into time sequence color data, and the display frame rate can be changed, so that the LCoS display test requirement is met. The LCoS driver chip may configure the operating mode and the display frame rate through an interface of the ARM processor 110.

At present, most of source input of the LCoS data stream is a video output source through a PC, and then protocol conversion is performed to convert the source input into a data format supported by the LCoS display chip 150, which usually occupies a PC video interface and wastes resources compared with general test equipment. The design data source is derived from a 1080P picture in the memory, picture data is read, and the data is output according to the RGB data stream standard, and the following scheme in 2 can be referred to in a specific implementable scheme:

the first scheme is as follows:

and programming by using an FPGA (field programmable gate array), hanging a memory chip externally, and storing a plurality of groups of picture data to be tested in a memory space in advance. When the display image is tested each time, the FPGA is controlled to read the image data in the memory, protocol conversion is carried out through an algorithm, the image data is converted into an RGB888 data stream format, and meanwhile, the display of different images can be controlled to be switched randomly.

Scheme II:

the method comprises the steps of selecting an integrated video memory chip, arranging a video memory in the integrated video memory chip, wherein a displayed picture data source is also provided by a memory chip externally hung outside the chip, the memory chip can select the size of a memory according to the requirement of a test picture, and an output interface of the video memory chip can output RGB888 data stream format. And during the test process, the ARM processing module controls the video memory chip to output different image data streams.

Optionally, as shown in fig. 3, in order to implement the electrical connection of the above modules, a main power module 210, a processor power module 220 and a display card power module may be further disposed inside the casing, and when the corresponding display card module 120 includes a display memory module 121 and a display driver module 122, the display card power module may also include a display memory power module 230 and a display driver power module 240, where the main power module 210 includes a plurality of branches, for example, three branches in fig. 3, where the processor power module 220 is located in a first branch of the main power module 210, so that the main power module 210 supplies power to the processor 110 through the processor power module 220, the display memory power module 230 is located in a first sub-branch of a second branch of the main power module 210, so that the main power module 210 supplies power to the display memory module 121 through the display memory power module 230, and the display driver power module 240 is located in a second sub-branch of the main power module 210, so that the main power module 210 supplies power to the display driving module 122 through the display driving power module 240, wherein the first sub-branch, the second sub-branch and the first branch are connected in parallel. Meanwhile, a third branch can be further arranged, an IC power module 260 is arranged on the third branch, and the storage chip, the digital-to-analog converter, the LCoS display chip and the like are powered through the IC power module 260.

By providing the main power module 210, the processor power module 220, the video memory power module 230, the display driving power module 240, and the like, the input current and voltage can be converted by each power module, so that the output current and voltage to each power module is at its rated value, for example, the main power module 210 may be provided with a power interface through a housing, when an external power source is plugged into the power interface, the main power module 210 converts the current and voltage of the external input power source to the rated value, for example, 12v, and then outputs the converted current and voltage to each different branch, and when supplying power to the processor 110, the processor power module 220 can convert the current and voltage of the first branch to the rated value of the processor 110; similarly, when supplying power to the video memory module 121, the current and voltage of the first branch can be converted through the video memory power module 230, so as to satisfy the rated value of the video memory module 121. Therefore, the working requirements of each module when the rated value is different can be further met by setting the form of switching current and voltage of the power supply module, and the working stability of the power supply module is improved.

Optionally, an analog-to-digital converter connected to the processor 110 may be further disposed on the circuit board, and the analog-to-digital converter is connected to a packaged display chip (LCoS display chip) and configured to collect current information of the packaged display chip, where the collection may be only one path of current of the packaged display chip or multiple paths of current, when the processor 110 is externally connected to the display 290, the sampling result may be displayed on the display 290, and when the processor 110 is externally connected to the PC terminal 02, the data may be sent to the PC terminal 02, and the data may be classified by the PC terminal 02 and stored in the PC terminal 02. Therefore, the current information of the multi-path power supply branch of the packaged display chip can be sampled, so that the open-short circuit state on each branch can be collected, and the other function detection of the packaged display chip can be realized.

In addition, the current and voltage of each branch of the packaged display chip are sampled, so that the power consumption data of the packaged display chip can be tested.

Optionally, in order to further improve the accuracy of sampling the current of each branch of the packaged display chip, a current amplifier may be further disposed between the analog-to-digital converter and the packaged display chip, so that the sampled data may be amplified by the current amplifier, and thus, the collection of the micro current signal may be achieved. When collecting the current of the multi-path packaged display chip, a plurality of current amplifiers can be in one-to-one correspondence with each branch of the packaged display chip.

Because each path of power supply current of the LCoS display chip 150 is relatively small, the minimum value is microampere, the current sampling module can be designed by adopting a high-precision analog-to-digital converter and a high-precision current amplifier, the analog-to-digital converter has no delay increment accumulation and has multiple channels, dynamic input current errors can be eliminated by automatic cancellation of differential input current, and the sampling mode can be controlled by configuring a register through the ARM processor 110. The current amplifier selects a high-precision, low-voltage and high-side current detection amplifier, has small gain error and larger input common-mode voltage range.

The ARM processor 110 controls the analog-to-digital converter through an interface to perform configuration and data reading, and different channels can be switched to perform real-time high-precision sampling and conversion on the power supply current value of the LCoS display chip 150 through the current amplifier.

Optionally, as shown in fig. 3, the system further includes a routing on-off detection module 180 and a switch, the routing on-off detection module 180 is connected to the first contact 161 of the switch, the graphics card module 120 is connected to the second contact 162 of the switch, the switch is connected to the test interface 130, an indicator light 170 is further disposed on a connection line between the routing on-off detection module 180 and the first contact 161 of the switch, and the processor 110 is electrically connected to the switch, so that after the processor 110 receives a test instruction, the routing on-off detection module 180 and the graphics card module 120 can be started according to a sequence of the test program, for example, in an embodiment: the routing on-off detection is preferentially performed, at this time, after the processor 110 receives the test instruction, the control switch is connected with the first contact 161, and the routing on-off detection module 180 is connected with the packaged display chip through the switch and the test interface 130, so that the routing on-off state of the packaged display chip can be displayed by turning on or off the indicator lamp 170, and the routing on-off item of the packaged display chip can be tested. After the routing on-off detection item is finished, the processor 110 controls the switch to change the position, and at this time, the processor 110 is connected with the packaged display chip through the display card module 120 and the test interface 130, so as to perform subsequent display characteristic detection.

When the packaged display chip comprises a plurality of pins, a plurality of wire bonding on-off detection branches which are connected in parallel are correspondingly arranged and respectively correspond to the plurality of pins of the packaged display chip one to one, and an indicator lamp 170 is arranged on each wire bonding on-off detection branch, so that the on-off states of different wire bonding of the packaged display chip can be displayed more visually. In addition, the processor 110 can be connected with the wire bonding on-off detection module 180, so that the on-off of a plurality of wire bonds of the packaged display chip can be acquired, and the display on the display 290 or the display or the storage on the PC terminal 02 can be conveniently performed subsequently. As shown in fig. 1, the indicator light 170 may be disposed on the housing, so that an operator can visually recognize the wire bonding on/off state of the packaged display chip.

Optionally, the test device further comprises a display screen, the display screen is installed on one side of the housing, and the display screen is electrically connected with the processor 110, so that the processor 110 can display various test information and results.

Optionally, a data interface 280 is further disposed on the circuit board, and the data interface 280 is electrically connected to the processor 110, so that different test pictures can be downloaded through the data interface 280, and the data interface 280 may be a USB data interface, a lightning interface, or the like.

Optionally, a communication interface 270 may be further disposed on the circuit board, and the communication interface 270 is electrically connected to the processor 110. When communication is needed, a communication device, such as an external PC terminal 02, may be externally connected to implement data transmission and reception. The existing manual recording of test data is avoided.

The communication module is mainly used for realizing node interconnection, each display chip testing device 01 is equivalent to a node, and when a plurality of display chip testing devices 01 work simultaneously, the display chip testing devices are connected through connecting wires, and test data of the display chip testing devices 01 can be sent to an upper computer (PC end 02) to be processed simultaneously. The traditional RS232 interface does not support "node" extension, only can perform single communication, and is not suitable for the design, and according to the characteristics of the communication transmission path, the following 2 schemes may be referred to as specific implementable schemes.

The first scheme is as follows:

a CAN bus protocol is selected, the CAN bus transmits data through a pair of differential signal lines, the communication failure rate is extremely low, and meanwhile the communication rate CAN reach 1 Mbps. The CAN bus network belongs to a multi-master network, and each node determines a receiving node according to the priority when sending data at the same time, so that the problem of data interference is avoided. The bus has a reliable error processing and detecting mechanism, and can automatically retransmit when the transmitted data is damaged, so that the reliability of the data transmitted by each display chip testing device 01 can be ensured. The ARM processor 110 interface in the display chip test equipment 01 is provided with a CAN interface, data transmission CAN be achieved through an external CAN driving chip, a connecting line which is finally uploaded to an upper computer has a CAN protocol conversion function, and CAN data CAN be converted and then sent to the PC end 02.

Scheme II:

an RS485 interface is selected, an interface bus is also a pair of differential signal lines, the communication failure rate is low, the cost is low, each node is used as a slave, and when a plurality of nodes work simultaneously, test data can be uploaded to a host. The 'host' is a PC (personal computer) end 02 upper computer connected with the hardware test system, only one 'slave' can be allowed to send data to the 'host' at the same time by the RS485 bus system, when the 'host' receives the data, point-to-point reception is performed in a polling mode, each hardware test system is provided with an RS485 driving interface, the transmission distance is long, and the reliability is high.

The design can further improve the testing efficiency, and when a plurality of persons use the display chip testing equipment 01 at the same time, the 'host' can simultaneously receive, process and store the data measured by each display chip testing equipment 01.

Task management: the design uses the ARM processor 110 to run a uC/OS-II embedded operating system for multitask management. The mu C/OS-II can divide the multitask into time slices and carry out multitask operation macroscopically, and the real-time performance of each function operation is guaranteed.

A plurality of tasks are defined on a software level, and respectively comprise an analog-digital conversion task, a power consumption task, a picture display task and the like. The analog-to-digital conversion task realizes current sampling of the power supply of the LCoS display chip 150, if a power supply of a certain path is open or short-circuited, the corresponding task can be correspondingly processed, if the power supply is short-circuited, the power supply can be turned off, and if the power supply is open, corresponding prompt is carried out. The power consumption task converts the current value obtained by real-time sampling into output power consumption data which are in a decimal display format, and then the data are sent to a PC (personal computer) end 02 upper computer through a communication port. The image display task is to send an instruction to the video memory module 121 through the ARM processor 110, and different instructions can control the video memory module 121 to read data of different images, so as to output the data to the next-stage display driver chip. Mutual exclusion semaphores are used in a mu C/OS-II system to synchronize a plurality of tasks, and power consumption values output by calculation each time are guaranteed to be latest real-time sampled data results.

Interrupt management: software mainly uses a plurality of external interrupts and timer interrupts. The external interrupt mainly realizes the switching function of the keys, and the hardware test system defines a plurality of key functions, namely picture switching, frame rate switching, timing and Gamma switching. The software defines that the priority of the external interrupt is higher, and when the external interrupt is triggered, the control instruction is modified in the interrupt service program to achieve the control effect.

Timer interrupts are mainly classified into normal timer interrupts and RTC timer interrupts. The common timer interruption mainly provides short-time timing for 'key jitter elimination' to prevent error touch, and the RTC timer interruption mainly aims at the 'baking machine timing' function of a hardware test system. When the hardware test system is used for testing the preliminary display function of the LCoS display chip 150 for a long time, the RTC timer can be used for providing an accurate time-minute-second timing function.

In another embodiment, a plurality of display chip testing devices 01 may be further provided, as shown in fig. 4, the display chip testing devices 01 are connected in series as "nodes" through a communication interface 270, and are connected to the PC terminal 02, and the data is automatically classified and stored into a certain format in combination with software processing of the PC terminal 02. For example, the data to be uploaded is automatically uploaded to the designated path of the upper computer of the PC 02 via the communication interface 270, and is stored as a file with a certain format, such as a. xsl file and a. txt file. If a plurality of hardware test systems are used, each hardware test system is connected in series through the communication interface 270, each hardware test system is equivalent to 1 bus node and has a unique address, and the plurality of hardware test systems can upload data when working together. Therefore, the test of a plurality of packaged display chips is realized, and a plurality of test stations can be conveniently used at the same time.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A display chip test apparatus, comprising: the display card comprises a shell and a circuit board arranged in the shell, wherein a processor, a display card module and an image storage module are arranged on the circuit board; the processor is electrically connected with the display card module, the display card module is electrically connected with the image storage module, a test interface connected with the display card module is further arranged on the circuit board and used for inserting a packaged display chip so as to enable the processor to control the display card module to call the data information in the image storage module and then drive the packaged display chip to display images.

2. The display chip testing apparatus of claim 1, wherein the data information comprises a plurality of sets of frame rate image information, and the graphics card module is configured to retrieve frame rate image information matching the instruction information according to the instruction information of the processor to drive the packaged display chip to display a corresponding frame rate image.

3. The device for testing the display chip according to claim 1, wherein the graphics card module comprises a video memory module and a display driver module electrically connected to each other, the processor is electrically connected to the video memory module, the image storage module is electrically connected to the video memory module, and the display driver module is connected to the test interface.

4. The display chip testing device according to any one of claims 1 to 3, further comprising a main power supply module, a processor power supply module, and a graphics card power supply module, wherein the processor power supply module is located in a first branch of the main power supply module so that the main power supply module supplies power to the processor through the processor power supply module, and the graphics card power supply module is located in a second branch of the main power supply module so that the main power supply module supplies power to the graphics card module through the graphics card power supply module.

5. The display chip testing apparatus of claim 1, wherein an analog-to-digital converter connected to the processor is further disposed on the circuit board, and the analog-to-digital converter is connected to the packaged display chip and is configured to collect current information of the packaged display chip.

6. The display chip test apparatus of claim 5, wherein a current amplifier is further disposed between the analog-to-digital converter and the packaged display chip.

7. The display chip testing device of claim 1, further comprising a routing on-off detection module and a switch, wherein the routing on-off detection module is connected with a first contact of the switch, the graphics card module is connected with a second contact of the switch, the switch is connected with the testing interface, an indicator lamp is further arranged on a connecting line of the routing on-off detection module and the first contact of the switch, and the processor is electrically connected with the switch and used for switching the communication state of the routing on-off detection module and the graphics card module with the testing interface.

8. The display chip testing apparatus of claim 1, further comprising a display screen disposed at a side of the housing and electrically connected to the processor.

9. The display chip test apparatus of claim 1, wherein a data interface is further provided on the circuit board, the data interface being electrically connected to the processor.

10. The display chip test apparatus of claim 1, wherein a communication interface is further provided on the circuit board, the communication interface being electrically connected to the processor.

Images