CN212256104U - Drive accuse intergral template testing arrangement - Google Patents
Drive accuse intergral template testing arrangement Download PDFInfo
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- CN212256104U CN212256104U CN202021401048.0U CN202021401048U CN212256104U CN 212256104 U CN212256104 U CN 212256104U CN 202021401048 U CN202021401048 U CN 202021401048U CN 212256104 U CN212256104 U CN 212256104U
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Abstract
The utility model relates to a detect technical field, disclose a drive accuse intergral template testing arrangement. The utility model discloses in, drive accuse intergral template testing arrangement contains: the device comprises an upper computer, a test auxiliary board and a drive and control integrated board, wherein the test auxiliary board comprises a first single chip microcomputer and a first peripheral circuit, and the drive and control integrated board comprises a second single chip microcomputer and a second peripheral circuit; the first peripheral circuit is electrically connected with the first singlechip; the second peripheral circuit is electrically connected with the second singlechip; the upper computer is connected with the first single chip microcomputer through serial port communication; the first peripheral circuit is connected with the second peripheral circuit through a wire; the first single chip microcomputer is in communication connection with the second single chip microcomputer. Compared with the prior art, the utility model discloses a reduce serial ports use quantity, avoid driving the data interaction of accuse intergral template and host computer, realize driving the test of accuse intergral template, also saved the test cost when improving efficiency of software testing.
Description
Technical Field
The utility model relates to a detect technical field, in particular to drive accuse intergral template testing arrangement.
Background
The drive and control integrated plate refers to a single plate integrating drive and control, and is mainly applied to the field of integrated circuit product production, such as the field of air source heat pump frequency converter generation. However, the utility model discloses the people discovers that the test of driving accuse intergral template still uses traditional FCT (functional test) technique to realize at present, adopts to drive accuse intergral template promptly and test the accessory plate and realize the test with host computer communication respectively, and the communication serial ports that can lead to between driving accuse intergral template and the host computer like this sets up complicated loaded down with trivial details, causes the low problem of efficiency of software testing who drives accuse intergral template.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a drive and control integrated board testing arrangement realizes the transmission of test instruction of test accessory plate and host computer through a serial ports communication, and founds test accessory plate and drive and control integrated board principal and subordinate framework realize drive and control the test of integrated board, avoided driving and control integrated board and host computer and directly carried out the data interaction to improve the efficiency of software testing of driving and controlling integrated board.
In order to solve the above technical problem, an embodiment of the utility model provides a drive and control integrated board testing device, contains: the device comprises an upper computer, a test auxiliary plate and a driving and controlling integrated plate;
the test auxiliary board comprises a first single chip microcomputer and a first peripheral circuit, and the drive and control integrated board comprises a second single chip microcomputer and a second peripheral circuit;
the first peripheral circuit is electrically connected with the first singlechip;
the second peripheral circuit is electrically connected with the second singlechip;
the upper computer is connected with the first single chip microcomputer through serial port communication;
the first peripheral circuit is connected with the second peripheral circuit through a wire;
the first single chip microcomputer is in communication connection with the second single chip microcomputer.
The utility model discloses embodiment uses quantity through reducing the serial ports for prior art, avoids driving the data interaction of accuse intergral template and host computer, realizes driving the test of accuse intergral template, also saved the test cost when improving efficiency of software testing.
Preferably, the second peripheral circuit comprises one or any combination of the following circuits: the circuit comprises a power factor correction circuit, a pre-charging resistor circuit, a fan circuit, a pulse width modulation circuit and a self-testing item circuit.
The utility model discloses based on arbitrary one kind or several kinds of arbitrary circuit combination can ensure the follow-up comprehensive nature of driving accuse intergral template test circuit to the reliability of the test of guarantee driving accuse intergral template.
Preferably, the power factor correction circuit, the pre-charge resistor circuit, the fan circuit, and the pulse width modulation circuit are respectively connected to the first peripheral circuit by wires.
The utility model discloses based on mutual circuit can test out the test accessory plate and drive the circuit data between the accuse intergral template, ensures follow-up test accuracy and the reliability of driving the accuse intergral template.
Preferably, the power factor correction circuit, the pre-charge resistor circuit, the fan circuit, the pulse width modulation circuit and the self-test item circuit are connected in parallel.
The utility model discloses a parallel mode carries out circuit connection, has avoided the influence each other of electric current between the circuit, improves the accuracy of circuit test.
Preferably, the self-test item circuit comprises one or any combination of the following circuits:
the device comprises a temperature detection circuit, a power factor correction current detection circuit, a fault detection circuit, a mains supply detection circuit, a bus detection circuit, a current comparison circuit, a current detection circuit and a storage detection circuit.
The utility model discloses based on arbitrary one kind or several kinds of arbitrary circuit combination can ensure the comprehensiveness of follow-up self-test project circuit test to the reliability of the integrated board test of guarantee drive and control.
Preferably, the temperature detection circuit, the power factor correction current detection circuit, the fault detection circuit, the commercial power detection circuit, the bus detection circuit, the current comparison circuit, the current detection circuit and the storage detection circuit are connected in parallel.
The utility model discloses a parallel mode carries out circuit connection, has avoided the influence each other of electric current between the self-test project circuit, improves the accuracy of circuit test.
Preferably, the parameters to be tested of the self-test item circuit comprise one or any combination of the following: digital quantities, analog quantities, communication signals, and storage quantities of the memory.
Preferably, the digital quantity, the communication signal and the storage capacity of the memory read the corresponding specific numerical value in the form of a return flag bit.
Preferably, the analog quantity of the memory generates a corresponding specific numerical value by reading a voltage value.
Preferably, the baud rate of serial port communication is 115200, and the data transmission protocol is a Modbus protocol.
The utility model has the advantages that: through reducing serial ports use quantity, avoid driving the data interaction of accuse intergral template and host computer, realize driving the test of accuse intergral template, also saved the test cost when improving efficiency of software testing.
Drawings
Fig. 1 is a structural diagram of a driving and controlling integrated board testing device provided by the present invention;
fig. 2 is an implementation flowchart of the driving and controlling integrated board testing device according to the present invention;
fig. 3 is a flowchart illustrating a detailed implementation of step S2 in the method for testing a driving and controlling integrated circuit board using the driving and controlling integrated circuit board testing apparatus according to the present invention shown in fig. 2;
fig. 4 is a schematic diagram of data query of a failure point of a portion of a to-be-tested driving and controlling integrated board.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following will explain in detail each embodiment of the present invention with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the claims of the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.
The utility model relates to a drive accuse intergral template testing arrangement, the utility model discloses the core lies in realizing the test instruction transmission of test accessory plate and host computer through a serial communication, and founding test accessory plate and drive accuse intergral template principal and subordinate framework realize drive the test of accuse intergral template, avoided driving accuse intergral template and host computer and directly carried out the data interaction to improve the efficiency of software testing of driving accuse intergral template.
The implementation details of the driving and controlling integrated board test according to the embodiment of the present invention are specifically described below, and the following description is only provided for the convenience of understanding, and is not necessary for implementing the present solution. Referring to fig. 1, the structure diagram of the driving and controlling integrated board testing device provided by the present invention is shown.
Drive accuse intergral template testing arrangement includes host computer 1, test accessory plate 2, drives accuse intergral template 3.
The upper computer 1 is a computer capable of directly sending an operation instruction, and can be generally understood as a controller or a service provider. Preferably, in the utility model discloses in the host computer is the PC. Drive accuse intergral template 3 and wait to detect the board, for example, the utility model discloses in, drive accuse intergral template 3 can drive accuse intergral template for air source heat pump converter.
The utility model discloses in, host computer 1 through serial communication with 2 communication connection of test accessory plate, with to test accessory plate 2 sends test instruction, and receive the test result that test accessory plate 2 returned. The serial communication is a communication device for transmitting data between the test auxiliary board 2 and the upper computer 1 by bit through a data signal line, a ground line, a control line and the like. In an optional embodiment, the baud rate of the serial port communication is 115200, and the data transmission protocol is a Modbus protocol.
Preferably, the test auxiliary plate 2 includes: first peripheral circuit 4 and first singlechip 5(Microcontroller Unit, MCU), it includes to drive accuse intergral template 3: a second peripheral circuit 6 and a second singlechip 7. The first peripheral circuit is electrically connected with the first single chip microcomputer, the second peripheral circuit is electrically connected with the second single chip microcomputer, and power transmission and circuit data transmission are achieved based on the electrical connection. Further, the first peripheral circuit 4 in the test auxiliary board 2 and the second peripheral circuit 6 in the drive-control integrated board 3 are connected by electric wires to perform power transmission. The first single chip microcomputer 5 in the test auxiliary board 2 is in communication connection with the second single chip microcomputer 7 in the control integrated board 3 to execute data interaction.
In an optional embodiment, the wire connection mode is flat cable connection, and the communication connection mode is USART communication.
Further, the second peripheral circuit comprises one or any combination of the following circuits: a Power Factor Correction (PFC) circuit 8, a pre-charge resistor circuit 9, a fan circuit 10, a Pulse Width Modulation (PWM) circuit 11, and a self-test item circuit 12. In one optional embodiment of the present invention, the self-test item circuit 12 includes one or any combination of the following circuits: temperature detection circuitry, PFC current detection circuitry, FAULT (FAULT) detection circuitry, utility detection circuitry, bus detection circuitry, current comparison circuitry, current detection circuitry, and memory (EEPROM) detection circuitry. The PFC circuit 8, the pre-charge resistor circuit 9, the fan circuit 10, the PWM circuit 11, and the self-test item circuit 12 are electrically connected to the first peripheral circuit 4 to obtain a plurality of interactive circuits, which can be beneficial to improving the accuracy and reliability of the test result of the subsequent board to be tested based on the interactive circuits; the PFC circuit 8, the pre-charge resistance circuit 9, the fan circuit 10, the PWM circuit 11 and the self-test item circuit 12 are connected in parallel; the temperature detection circuit, the PFC current detection circuit, the FAULT detection circuit, the commercial power detection circuit, the bus detection circuit, the current comparison circuit, the current detection circuit and the EEPROM detection circuit are connected in a parallel connection mode, and are connected in the parallel connection mode, so that mutual influence of current among the circuits is avoided, and the accuracy of circuit testing is improved.
Based on any one or any combination of circuits, the comprehensiveness of a follow-up drive and control integrated board test circuit can be guaranteed, so that the reliability of the drive and control integrated board test is guaranteed, the circuits are connected in a parallel connection mode, the mutual influence of current among the circuits is avoided, and the accuracy of the circuit test is improved.
The utility model discloses in, the examination parameter that awaits measuring of self-test project circuit 12 includes: digital values, analog values, communication signals, and the storage capacity of a memory (EEPROM). The digital quantity, the communication signal and the EEPROM storage capacity read corresponding specific numerical values in a form of returning flag bits, and the analog quantity generates corresponding specific data by reading voltage values.
Preferably, in the utility model discloses in, test accessory plate 2 with the relation of driving and controlling integrated board 3 is master-slave mode architecture relation, promptly test accessory plate 2 is the mainboard for send test instruction data and judge whether carry out the data test, drive and control integrated board 3 is the slave plate, is used for receiving test instruction data and the data test of carrying out that the test accessory plate sent.
Based on principal and subordinate's mode framework relation, the utility model discloses realize driving and controlling integrated board 3 and test accessory plate 2's data interaction, avoid driving and controlling integrated board and host computer 1's data interaction to need not dispose the serial ports communication of driving and controlling integrated board 3 and host computer 1, and then can improve the efficiency of software testing of driving and controlling integrated board 3. Therefore, the utility model discloses can solve prior art upper computer 1 and drive the complicated loaded down with trivial details of serial ports communication configuration between the accuse intergral template 3, lead to driving the problem that accuse intergral template 3 efficiency of software testing is low.
Specifically, referring to the following fig. 2, the present invention provides an implementation flowchart for executing the driving and controlling integrated board test by using the driving and controlling integrated board test apparatus, including:
and S1, the first singlechip in the test auxiliary board receives a first test instruction sent by the upper computer.
Preferably, before first singlechip in the test accessory plate received the first test instruction that the host computer sent, still including establishing first singlechip in the test accessory plate with the serial ports communication of host computer, according to serial ports communication carries out the transmission of first test instruction.
Further, in another embodiment of the present invention, the transmitting of the first test instruction according to the serial port communication may include: traversing all serial port numbers in the serial port communication, and executing automatic identification of the test instruction according to a pre-compiled serial port communication automatic identification script, namely transmitting the first test instruction sent by the upper computer to an interface corresponding to a first singlechip in the test auxiliary board, and automatically identifying the test auxiliary board interface number required to be transmitted by the first test instruction through the serial port communication automatic identification script, so that matching of manual participation test instructions and the test auxiliary board interface numbers is avoided, and test cost caused by excessive manual participation in matching of the test instructions can be reduced.
In an optional embodiment, the serial communication automatic identification script is compiled by using a preset language, and the preset language is a C + + language.
And S2, the first single chip microcomputer sends the first test instruction to the drive and control integrated board, and according to the first test instruction, the second single chip microcomputer in the drive and control integrated board executes circuit test of a self-test item circuit in the drive and control integrated board to obtain a first test result.
Further, the utility model discloses another embodiment, before first singlechip will first test instruction sends to drive and control integrated board, can also include: and inquiring whether a fault point exists in at least one driving and controlling integrated plate to be tested or not so as to avoid the problem of deviation of the subsequent driving and controlling integrated plate to be tested caused by probe aging or structure deviation. Optionally, referring to fig. 4, fig. 4 is a schematic diagram of data query of a fault point of a driving and controlling integrated board to be tested, for example, in fig. 4, a minimum value of a PFC on-voltage is 14.00, a maximum value is 16.00, and a detected PFC on-voltage value is 15.00, which indicates that the PFC on-voltage of the driving and controlling integrated board to be tested is not the fault point.
In an alternative embodiment, the sending of the first test instruction is implemented according to the USART communication protocol described above.
In detail, referring to fig. 3 below, it is the utility model provides a basis according to first test instruction, drive the circuit test of controlling the project circuit of testing oneself in the integrated board of second singlechip execution in the integrated board of accuse, obtain the detailed implementation flow chart of first test result, include:
and S21, acquiring the to-be-tested parameters in the self-testing project circuit by a second singlechip in the drive and control integrated board.
As mentioned above, the parameters to be tested are digital quantity, analog quantity, communication signal and EEPROM memory.
And S22, testing the to-be-tested parameters by the second singlechip in the drive and control integrated board according to the first test instruction, and generating a first test result.
As mentioned above, the testing of the parameters to be tested includes, but is not limited to: and reading the specific numerical values of the digital quantity, the communication signal and the EEPROM storage volume and the analog quantity voltage value, and obtaining the first test result according to the read specific numerical values of the digital quantity, the communication signal and the EEPROM storage volume and the analog quantity voltage value.
And S3, according to the first test result, the first single chip microcomputer identifies whether the test of the self-test item circuit is finished.
In an optional embodiment, according to the first test result, the first single chip microcomputer queries whether an untested circuit exists or not, so that all test circuits in the self-test item circuit are ensured to complete testing, and the reliability and accuracy of the test result are ensured.
If the test is not finished, the flow returns to S2.
When the first single chip microcomputer recognizes that the self-testing project circuit test is not finished, the first single chip microcomputer sends the first test instruction to the drive and control integrated board again, and the circuit test of the self-testing project circuit is continuously executed.
And if the test is finished, S4 is executed, the first single chip microcomputer sends a second test instruction to the drive and control integrated board, and according to the second test instruction, the first single chip microcomputer executes the circuit test between the first peripheral circuit and the drive and control integrated board to obtain a second test result.
And when the first single chip microcomputer recognizes that the self-test item circuit test is finished, the test auxiliary board sends a second test instruction to the drive and control integrated board, and according to the second test instruction, the circuit test of the interaction circuit of the first peripheral circuit and the drive and control integrated board is executed to obtain a second test result.
The utility model discloses in, because the circuit connection mode of above-mentioned PFC circuit, pre-charge resistance circuit, fan circuit, PWM circuit is parallel connection, and respectively with first peripheral circuit electric connection, consequently, executing circuit test between first peripheral circuit and the drive and control integrated board, test PFC circuit, pre-charge resistance circuit, fan circuit, PWM circuit respectively promptly and first peripheral circuit's AD value.
In detail, according to the second test instruction, the first single chip executes a circuit test between the first peripheral circuit and the drive and control integrated board to obtain a second test result, including:
based on the second test instruction, the first single chip microcomputer executes circuit test of a PWM circuit and a first peripheral circuit in the drive and control integrated board to generate a first AD value;
based on the second test instruction, the first single chip microcomputer executes circuit test of a pre-charge resistor circuit and the first peripheral circuit in the drive and control integrated board to generate a second AD value;
based on the second test instruction, the first single chip microcomputer executes circuit test of the fan circuit and the first peripheral circuit in the drive and control integrated board to generate a third AD value;
based on the second test instruction, the first single chip microcomputer executes circuit test of a PFC circuit and the first peripheral circuit in the driving and controlling integrated board to generate a fourth AD value;
and the first single chip microcomputer summarizes the first AD value, the second AD value, the third AD value and the fourth AD value to obtain the second test result.
Further, the performing, by the first single chip microcomputer, a circuit test of the PWM circuit in the drive-control integrated board and the first peripheral circuit based on the second test instruction, and generating a first AD value includes:
and the first single chip microcomputer transmits the second test instruction to the PWM circuit, turns on all upper bridge arms of the transistors in the PWM circuit according to the transmitted test instruction, inquires whether the upper bridge arms in the corresponding transistors are normally turned on or not by using a handshake protocol, waits for a period of time if the upper bridge arms in the corresponding transistors are not normally turned on, skips over the circuit test of the transistors, performs the circuit test of the rest transistors in the PWM circuit, reads the voltage value of the corresponding transistors if the upper bridge arms in the corresponding transistors are normally turned on, and converts the voltage value of the transistors into a first AD value.
Further, the performing, by the first single chip microcomputer, a circuit test of the pre-charge resistor circuit in the drive-control integrated board and the first peripheral circuit based on the second test instruction, and generating a second AD value includes:
based on the second test instruction, the first single chip microcomputer connects a pre-charge resistor in parallel to the first peripheral circuit and the second peripheral circuit, reads the voltage value of the pre-charge resistor after electrifying the test auxiliary board, and converts the voltage value of the pre-charge resistor into a second AD value. It is to be noted that the current source circuit in the first peripheral circuit is a 15ma current source circuit.
Further, the performing, by the first single chip microcomputer, a circuit test of the fan circuit and the first peripheral circuit in the drive-control integrated board based on the second test instruction, and generating a third AD value includes:
based on the second test instruction, the first single chip microcomputer controls the on or off of the fan in the fan circuit, reads a corresponding fan circuit voltage value when the fan is in an on or off state, and converts the fan circuit voltage value into a third AD value.
Further, the executing, by the first single chip microcomputer, a circuit test of the PFC circuit and the first peripheral circuit in the driving and controlling integrated board based on the second test instruction, and generating a fourth AD value includes:
based on the second test instruction, the first single chip microcomputer controls the on or off of the PFC circuit, reads the voltage value of the PFC circuit corresponding to the on or off state, and converts the voltage value of the PFC circuit into a fourth AD value.
The AD value refers to a digital voltage value corresponding to the voltage value and is used for being identified by the singlechip, so that the AD value can be returned to an upper computer to help a user to identify whether the corresponding circuit has a fault or not.
And S5, the first single chip microcomputer returns the first test result and the second test result to the upper computer.
The utility model discloses in, first test result save in the buffer memory of second singlechip, second test result save with in the buffer memory of first singlechip.
In an optional embodiment, the first single chip microcomputer reads the first test result in the second single chip microcomputer, and returns the first test result and the second test result to the upper computer according to a Modbus protocol.
Further, the upper computer identifies whether the driving and controlling integrated plate has a fault after receiving a first test result and a second test result returned by the test auxiliary plate, displays the content of the fault point in a fault point popup window mode if the driving and controlling integrated plate has the fault, and puts the driving and controlling integrated plate into a warehouse if the driving and controlling integrated plate does not have the fault. Wherein the content presentation comprises: the test auxiliary board and the driving and controlling integrated board are connected with a description and the driving and controlling integrated board is connected with a device and a circuit which can be related with the driving and controlling integrated board.
The utility model discloses look over the trouble reason of driving and controlling integrated board based on fault point bullet window, can help the user to fix a position the trouble root cause rapidly, save the time and the human cost of maintenance.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (10)
1. A drive and control integrated board testing device is characterized by comprising: the device comprises an upper computer, a test auxiliary plate and a driving and controlling integrated plate;
the test auxiliary board comprises a first single chip microcomputer and a first peripheral circuit, and the drive and control integrated board comprises a second single chip microcomputer and a second peripheral circuit;
the first peripheral circuit is electrically connected with the first singlechip;
the second peripheral circuit is electrically connected with the second singlechip;
the upper computer is connected with the first single chip microcomputer through serial port communication;
the first peripheral circuit is connected with the second peripheral circuit through a wire;
the first single chip microcomputer is in communication connection with the second single chip microcomputer.
2. The device for controlling integrated board testing according to claim 1, wherein the second peripheral circuit comprises one or any combination of the following circuits:
the circuit comprises a power factor correction circuit, a pre-charging resistor circuit, a fan circuit, a pulse width modulation circuit and a self-testing item circuit.
3. The drive control integrated board test device according to claim 2, wherein the power factor correction circuit, the pre-charge resistor circuit, the fan circuit, and the pulse width modulation circuit are respectively connected to the first peripheral circuit through wires.
4. The driving and controlling integrated board testing device according to claim 2, wherein the power factor correction circuit, the pre-charge resistor circuit, the fan circuit, the pulse width modulation circuit and the self-test item circuit are connected in parallel.
5. The device for testing the control integration plate as claimed in claim 2, wherein the self-test item circuit comprises one or any combination of the following circuits:
the device comprises a temperature detection circuit, a power factor correction current detection circuit, a fault detection circuit, a mains supply detection circuit, a bus detection circuit, a current comparison circuit, a current detection circuit and a storage detection circuit.
6. The device for testing a drive-control integrated board according to claim 5, wherein the temperature detection circuit, the PFC current detection circuit, the fault detection circuit, the commercial power detection circuit, the bus detection circuit, the current comparison circuit, the current detection circuit and the storage detection circuit are connected in parallel.
7. The drive control integrated board test device according to claim 2, wherein the parameters to be tested of the self-test item circuit comprise one or a combination of any of the following: digital quantities, analog quantities, communication signals, and storage quantities of the memory.
8. The drive control integrated board test device according to claim 7, wherein the digital quantity, the communication signal and the storage capacity of the memory read corresponding specific values in the form of return flag bits.
9. The drive control integrated board test device according to claim 7, wherein the analog quantity of the memory generates a corresponding specific numerical value by reading a voltage value.
10. The integrated panel test device of claim 1, wherein the serial port communication has a baud rate of 115200 and the data transmission protocol is Modbus protocol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021401048.0U CN212256104U (en) | 2020-07-16 | 2020-07-16 | Drive accuse intergral template testing arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021401048.0U CN212256104U (en) | 2020-07-16 | 2020-07-16 | Drive accuse intergral template testing arrangement |
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| Publication Number | Publication Date |
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| CN212256104U true CN212256104U (en) | 2020-12-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202021401048.0U Active CN212256104U (en) | 2020-07-16 | 2020-07-16 | Drive accuse intergral template testing arrangement |
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| CN (1) | CN212256104U (en) |
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