CN218826147U

CN218826147U - MIPI signal transmitter

Info

Publication number: CN218826147U
Application number: CN202222947916.0U
Authority: CN
Inventors: 谭国威
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2022-11-04
Filing date: 2022-11-04
Publication date: 2023-04-07
Anticipated expiration: 2032-11-04

Abstract

The application discloses a MIPI signal transmitter. The MIPI signal transmitter includes: the communication module is used for transmitting configuration data and image data; the FPGA control chip is connected with the communication module, converts the configuration data into a control signal and converts the image data into an RGB signal; and the MIPI bridge chip is connected with the FPGA control chip and converts the RGB signals into MIPI signals, wherein the MIPI bridge chip comprises a first output port and a second output port, and the MIPI signals are output at least one of the first output port and the second output port according to the control signals. The MIPI signal transmitter can configure a single/double port output mode according to configuration data, and can realize multi-path signal transmission in the double port output mode, so that a test system is simplified, and test requirements are met more conveniently and efficiently.

Description

MIPI signal transmitter

Technical Field

The utility model relates to a display screen test field, in particular to MIPI signal transmitter.

Background

MIPI D-PHY is largely used in the part of the processor that interfaces with the display screen. With the improvement of the requirements of people on screen resolution and high refresh rate, the data transmission rate of the MIPI D-PHY cannot meet the current requirements, more and more intelligent display screen driving ICs begin to use the MIPI C-PHY to carry out image transmission, and the requirements of MIPI C-PHY interface display module detection equipment are accelerated.

However, in the market, MIPI signal transmitter devices for MIPI C-PHY interface display module detection devices are few, expensive, and also have weak functions, for example, multi-path MIPI signal transmission cannot be supported, so that two devices need to be used simultaneously during a cascade test, and particularly, under the condition that two modes of video and command need to be supported, corresponding devices need to be purchased for tests in different modes, thereby increasing the test cost and the complexity of the test environment.

SUMMERY OF THE UTILITY MODEL

In view of the above problem, the utility model aims at providing a MIPI signal transmitter, this MIPI signal transmitter can switch single/dual port output mode according to the configuration data to can realize multichannel signalling under dual port output mode, thereby simplify test system, more convenient efficient satisfies the chip test demand.

According to the utility model discloses an embodiment provides a MIPI signal transmitter, a serial communication port, include: the communication module is used for transmitting configuration data and image data; the FPGA control chip is connected with the communication module, converts the configuration data into a control signal and converts the image data into an RGB signal; and the MIPI bridge chip is connected with the FPGA control chip and converts the RGB signals into MIPI signals, wherein the MIPI bridge chip comprises a first output port and a second output port, and the MIPI signals are output at least one of the first output port and the second output port according to the control signals.

Optionally, the FPGA control chip includes a data processor, an SPI converter, and a storage controller, where the data processor is connected to the communication module, and is configured to classify the image data and the configuration data and send the image data and the configuration data to the SPI converter; the SPI converter is connected with the data processor, receives the configuration data, converts the configuration data into the control signal and sends the control signal to at least one of the memory controller and the MIPI bridge chip; and the storage controller is connected with the data processor and the SPI converter, processes the image data according to the control signal and outputs the RGB signals to the MIPI bridge chip.

Optionally, the control signal comprises: the method comprises the steps of outputting a mode control signal, sending the mode control signal to a storage controller and a MIPI bridging chip, and configuring an output mode of the MIPI signal transmitter, wherein the output mode comprises the following steps: a single port output mode and a dual port output mode.

Optionally, in the single-port output mode, the memory controller converts the complete image data to obtain the RGB signals.

Optionally, the MIPI signal is output through one of the first output port and the second output port.

Optionally, in the dual-port output mode, the RGB signals include a first RGB signal and a second RGB signal, where the memory controller converts the image data into a first partial image data and a second partial image data after processing the image data into corresponding RGB signals, the first RGB signal corresponds to the first partial image data, and the second RGB signal corresponds to the second partial image data.

Optionally, the MIPI signal includes a first MIPI signal and a second MIPI signal, and one of the first output port and the second output port outputs the first MIPI signal, and the other outputs the second MIPI signal.

Optionally, the first MIPI signal corresponds to the first RGB signal, and the second MIPI signal corresponds to the second RGB signal.

Optionally, the MIPI bridge chip further includes an MCU and a MIPI converter.

Optionally, the control signal further includes a working mode control signal, and the working mode control signal is sent to the MIPI bridge chip and is used for configuring a working mode of the MIPI signal transmitter, where the working mode includes a video mode and a command mode.

Optionally, in the video mode, the MIPI converter operates to convert the RGB signal into the MIPI signal.

Optionally, in the command mode, the MCU converts the RGB signals into MCU signals, and then the MCU converts the RGB signals into the MIPI signals.

Optionally, the signal transmitter further includes a memory connected to the FPGA control chip for storing the complete image data.

Optionally, the signal transmitter further includes a memory connected to the FPGA control chip and configured to store the first partial image data and the second partial image data.

Optionally, the communication module includes a USB communication module or an ethernet for transmitting the configuration data and the image data online.

According to the utility model discloses a MIPI signal transmitter, including first output port and second output port, FPGA control chip selects MIPI signal transmitter to work in different output mode and/or mode according to the configuration signal of difference, and carry out different processing in order to obtain the MIPI signal that corresponds to image data according to the configuration signal of difference, and export through at least one output port in first output port and the second output port, make MIPI signal transmitter can the different output mode of adaptation, thereby reduce the complexity of test cost and test environment, more convenient efficient satisfies the chip test demand.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 is a schematic block diagram showing a structure of a MIPI signal transmitter according to an embodiment of the present invention.

Fig. 2 shows a schematic block diagram of a MIPI signal transmitter in a single-port output mode according to an embodiment of the present invention.

Fig. 3 shows a schematic block diagram of a MIPI signal transmitter in a dual-port output mode according to an embodiment of the present invention.

Fig. 4 shows an equivalent circuit structure diagram of a MIPI bridge chip of a MIPI signal transmitter according to an embodiment of the present invention.

Fig. 5 shows a signal transmission flowchart of a MIPI signal transmitter according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to". In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.

As shown in fig. 1, the MIPI signal transmitter includes a communication module 10, an FPGA control chip 20, and a MIPI bridge chip 30.

And the communication module 10 sends the configuration data and the image data to the FPGA control chip 20. In some embodiments, the communication module 10 is a USB communication chip, which can implement online transmission of configuration data and image data, and in alternative embodiments, the communication module 10 is an ethernet.

And the FPGA control chip 20 is connected with the communication module, converts the configuration data into a control signal to configure the MIPI signal transmitter, and converts the image data into an RGB signal.

Further, referring to fig. 2 and 3, the fpga control chip 20 includes a data processor 21, an SPI converter 22, and a memory controller 23.

The data processor 21 is communicatively connected to the communication module 10, and performs a classification process on the image data and the configuration data. Wherein the configuration data is sent to the SPI converter 22 and the image data is sent to the memory controller 23.

The SPI converter 22 receives the configuration data sent by the data processor 21, converts the configuration data into the control signal, and sends the control signal to at least one of the memory controller 23 and the MIPI bridge chip 30 to configure the MIPI signal transmitter.

The memory controller 23 receives the image data sent by the data processor 21, processes the image data according to the control signal, and outputs the RGB signals.

And the MIPI bridge chip 30 is connected to the FPGA control chip 20, and converts the RGB signals into MIPI signals, wherein the MIPI bridge chip 30 includes a first output port and a second output port, each of the output ports is connectable to the display screen 50, and the MIPI signals are output at least one of the first output port and the second output port according to the control signal.

In an alternative embodiment, the MIPI signal transmitter further includes a memory 40 for storing image data.

Fig. 2 and fig. 3 respectively show schematic block diagrams of a MIPI signal transmitter in a single/dual port output mode according to an embodiment of the present invention. The MIPI signal transmitter of the present invention is further described with reference to fig. 2 and 3.

The MIPI signal transmitter comprises a communication module 10, an FPGA control chip 20 and an MIPI bridge chip 30.

The communication module 10 sends the image data and the configuration data to the data processor 21.

The data processor 21 classifies the image data and transmits the image data to the SPI converter 22 and the memory controller 23.

The SPI converter 22 converts the configuration data and outputs a corresponding control signal. The control signal includes an output mode control signal for configuring an output mode (i.e., a single-port output mode or a dual-port output mode) of the MIPI signal transmitter.

When the MIPI signal transmitter operates in the single-port output mode, as shown in fig. 2, the SPI converter 22 transmits an output mode control signal to the memory controller 23 and the MIPI bridge chip 30, and configures the memory controller 23 and the MIPI bridge chip 30 into the single-port output mode. The memory controller 23 converts the received complete image data into RGB signals and transmits the RGB signals to the MIPI bridge chip 30. In an alternative embodiment, referring to fig. 2, the MIPI signal generator further includes a memory 40, the memory controller 23 receives the image data and then writes the image data into the memory 40 in sequence, and after the configuration of the driving IC of the display screen 50 is completed, the image data in the memory 40 is read out in sequence and converted into RGB signals, and then the RGB signals are sent to the MIPI bridge chip 30.

The MIPI bridge chip 30 receives the RGB signal and converts it into a MIPI signal, and selects one of the first output port and the second output port of the MIPI bridge chip as an output port according to the output mode control signal to transmit the MIPI signal.

When the MIPI signal transmitter operates in the dual-port output mode, as shown in fig. 3, the SPI converter 22 transmits an output mode control signal to the memory controller 23 and the MIPI bridge chip 30, respectively, and the memory controller 23 and the MIPI bridge chip 30 are configured in the dual-port output mode. The memory controller 23 receives and processes the image data, converts the image data into a first partial image data and a second partial image data, converts the first partial image data and the second partial image data into RGB signals, and transmits the RGB signals to the MIPI bridge chip 30, where the RGB signals include a first RGB signal corresponding to the first partial image data and a second RGB signal corresponding to the second partial image data. In an alternative embodiment, referring to fig. 3, the MIPI signal generator further includes a memory 40, the memory controller 23 processes the image data after receiving the image data, processes the image data into a first partial image data and a second partial image data, respectively stores the first partial image data and the second partial image data in the memory 40, reads out the first partial image data and the second partial image data in the memory after completing the configuration of the driving IC of the display screen 50, converts the first partial image data and the second partial image data into corresponding first RGB signals and corresponding second RGB signals, and sends the first RGB signals and the second RGB signals to the MIPI bridge chip 30.

In the dual-port output mode, the MIPI bridge chip 30 receives the first RGB signal and the second RGB signal and converts the first RGB signal and the second RGB signal into a first MIPI signal corresponding to the first RGB signal and a second MIPI signal corresponding to the second RGB signal, and selects one of a first output port and a second output port of the MIPI bridge chip to transmit the first MIPI signal and the other output port to transmit the second MIPI signal according to the output mode control signal, thereby realizing transmission of multiple MIPI signals and realizing cascade connection of two display screens.

Further, the control signal that the SPI converter 22 converts and outputs the configuration data further includes a working mode control signal, and the SPI converter 22 transmits the working mode control signal to the MIPI bridge chip 30, so that the MIPI signal transmitter can switch between the video mode and the command mode.

Fig. 4 shows an equivalent circuit structure diagram of the MIPI bridge chip 30. The MIPI bridge chip 30 further includes a MIPI converter 31 and an MCU32, and the working mode control signal can be equivalent to a switch K _SPI . The operating mode control signal changes the operating state of MCU32 to adapt to the video mode or command mode. In the video mode, the MCU32 does not operate, and the MIPI converter 31 converts the RGB signal into an MIPI signal; in the command mode, the MCU32 works, the RGB signals are converted into MCU signals by the MCU32, and then converted into MIPI signals by the MIPI converter 31. Therefore, the test system is simplified to a great extent, and the chip test requirements can be met more conveniently and efficiently.

Fig. 5 shows a signal transmission flowchart of a MIPI signal transmitter according to the embodiment of the present invention, which specifically includes the following steps:

s101: acquiring image data and configuration data;

in this step, the communication module 10 transmits the configuration data and the image data to the data processor 21.

S102: configuring single-port output or dual-port output according to the configuration data;

in this step, the data processor 21 classifies and then transmits the configuration data to the SPI converter 22, and the SPI converter 22 converts the configuration data into a control signal, wherein the control signal includes an output mode control signal for configuring an output mode of the MIPI signal transmitter.

When the MIPI signal generator is configured in the single-port output mode, step S103 and step S104 are performed:

s103: converting the complete image data into corresponding RGB signals;

in this step, the memory controller 23 converts the received complete image data into a first RGB signal and transmits it to the MIPI bridge chip 30.

S104: converting the RGB signals into MIPI signals and sending the MIPI signals;

in this step, the MIPI bridge chip selects one of the first output port and the second output port as an output port according to the output mode control signal, and transmits the MIPI signal obtained by the RGB signal conversion.

When the MIPI signal generator is configured in the dual-port output mode, step S105 and step S106 are performed:

s105: processing the image data into first partial image data and second partial image data and then converting the first partial image data and the second partial image data into corresponding RGB signals;

in this step, the memory controller 23 processes the image data after receiving the image data, processes the image data into first partial image data and second partial image data, converts the first partial image data and the second partial image data into first RGB signals corresponding to the first partial image data and second RGB signals corresponding to the second partial image data, and transmits the first RGB signals and the second RGB signals to the MIPI bridge chip 30.

S106: converting the RGB signals into signals and sending the signals;

in this step, the MIPI bridge chip 30 converts the first RGB signal and the second RGB signal into the first MIPI signal and the second MIPI signal according to the output mode control signal, wherein the first MIPI signal corresponds to the first RGB signal, and the second MIPI signal corresponds to the second RGB signal. The MIPI bridge chip 30 selects one of the first output port and the second output port to transmit the first MIPI signal and the other to transmit the second MIPI signal according to the output mode control signal.

Further, as described above, different conversion steps for the RGB signals may also be implemented to adapt the adaptation mode and the command mode according to the control data. Under the video mode, MCU32 does not work, and MIPI converter 31 converts RGB signal into MIPI signal, and under the command mode, MCU32 work, MCU32 convert RGB signal into MCU signal earlier and convert into MIPI signal by MIPI converter 31 again. Therefore, the working mode control signal adapts the adaptive mode or the command mode by changing the working state of the MCU, so that the test system is simplified to a great extent, and the chip test requirement is met more conveniently and efficiently.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An MIPI signal transmitter, comprising:

the communication module is used for transmitting configuration data and image data;

the FPGA control chip is connected with the communication module, converts the configuration data into a control signal and converts the image data into an RGB signal; and

an MIPI bridge chip connected with the FPGA control chip for converting the RGB signals into MIPI signals,

the MIPI bridge chip comprises a first output port and a second output port, and the MIPI signals are output at least one of the first output port and the second output port according to the control signals.

2. The signal transmitter of claim 1, wherein the FPGA control chip comprises a data processor, an SPI converter, and a memory controller,

the data processor is connected with the communication module and used for classifying the image data and the configuration data and sending the image data and the configuration data to the SPI converter;

the SPI converter is connected with the data processor, receives the configuration data, converts the configuration data into the control signal and sends the control signal to at least one of the memory controller and the MIPI bridge chip; and

and the storage controller is connected with the data processor and the SPI converter, processes the image data according to the control signal and outputs the RGB signals to the MIPI bridge chip.

3. The signal transmitter of claim 2, wherein the control signal comprises:

the method comprises the steps of outputting a mode control signal, sending the mode control signal to a storage controller and a MIPI bridging chip, and configuring an output mode of the MIPI signal transmitter, wherein the output mode comprises the following steps: a single port output mode and a dual port output mode.

4. The signal transmitter of claim 3, wherein in the single-port output mode, the memory controller converts the complete image data to obtain the RGB signals.

5. The signal transmitter of claim 4, wherein the MIPI signal is output through one of the first and second output ports.

6. The signal transmitter of claim 3, wherein in the dual-port output mode, the RGB signals comprise first RGB signals and second RGB signals, wherein the memory controller converts the image data into first partial image data and second partial image data and converts the first RGB signals into corresponding RGB signals, wherein the first RGB signals correspond to the first partial image data, and wherein the second RGB signals correspond to the second partial image data.

7. The signal transmitter of claim 6, wherein the MIPI signals include a first MIPI signal and a second MIPI signal, one of the first output port and the second output port outputs the first MIPI signal, and the other outputs the second MIPI signal.

8. The signal transmitter of claim 7, wherein the first MIPI signal corresponds to the first RGB signal, and the second MIPI signal corresponds to the second RGB signal.

9. The signal transmitter of any one of claims 3 to 8, wherein the MIPI bridge chip further comprises an MCU and a MIPI converter.

10. The signal transmitter of claim 9, wherein the control signals further comprise an operating mode control signal, the operating mode control signal being transmitted to the MIPI bridge chip for configuring an operating mode of the MIPI signal transmitter, wherein the operating mode includes a video mode and a command mode.

11. The signal transmitter of claim 10, wherein in the video mode, the MIPI converter operates to convert the RGB signal into the MIPI signal.

12. The signal transmitter of claim 10, wherein in the command mode, the MCU converts the RGB signals into MCU signals first, and then the MIPI signals are converted by the MIPI converter.

13. The signal transmitter of claim 4, further comprising a memory coupled to the FPGA control chip for storing the complete image data.

14. The signal transmitter of claim 6, further comprising a memory coupled to the FPGA control chip for storing the first partial image data and the second partial image data.

15. The signal transmitter of claim 1, wherein the communication module comprises a USB communication module or an ethernet for transmitting the configuration data and the image data online.