CN214477445U

CN214477445U - Novel TO series SlP packaged integrated circuit packaging structure

Info

Publication number: CN214477445U
Application number: CN202120572427.4U
Authority: CN
Inventors: 王文正
Original assignee: Shenzhen Ccmic Electronics Co ltd
Current assignee: Shenzhen Ccmic Electronics Co ltd
Priority date: 2021-03-19
Filing date: 2021-03-19
Publication date: 2021-10-22
Anticipated expiration: 2031-03-19

Abstract

The utility model discloses a novel TO series SlP packaging integrated circuit's packaging structure, including the PCB board, the PCB board is ceramic PCB board, one side on the ceramic PCB board makes required circuit or the part position that needs the paster, the ceramic PCB board has A contact surface, B contact surface and three participate in the connecting pin, and this three participate in the connecting pin is respectively TO link up 1 foot, 2 feet and 3 feet of A contact surface and B contact surface; the ceramic PCB is provided with a synchronous rectification circuit, and the synchronous rectification circuit comprises an MOS (metal oxide semiconductor) tube, a resistor, a second capacitor and a synchronous rectification chip electrically connected with the MOS tube; the utility model does not need electroplating, does not need a bar cutting system, does not need electroplating process, and then does not pollute the environment. And a bar cutting system is not needed, so that the production efficiency can be improved, and the production cost can be reduced. The utility model discloses a TO series SlP encapsulation integrated circuit's packaging structure can realize the systematic encapsulation of TO series multiwafer, many parts.

Description

Novel TO series SlP packaged integrated circuit packaging structure

Technical Field

The utility model relates TO a TO series SlP packaging structure, specific saying so relates TO a novel TO series SlP encapsulation integrated circuit's packaging structure.

Background

The existing TO series integrated circuit package is made of copper or iron as an integral molding structure, and the traditional package structure has the following defects:

1. the copper frame needs to be electroplated, the electroplating pollutes the environment, and the cost is high;

2. multi-wafer and multi-part SIP packaging is not possible;

3. the cost of copper is high, which further affects the cost of packaging products;

4. and a bar cutting system is needed after the product is formed, so that the production efficiency is low, and the production cost is increased.

SUMMERY OF THE UTILITY MODEL

TO the not enough among the prior art, the TO-be-solved technical problem of the utility model lies in providing a novel TO series SlP encapsulates integrated circuit's packaging structure.

In order to solve the technical problem, the utility model discloses a following scheme realizes: the utility model discloses a novel TO series SlP encapsulation integrated circuit's packaging structure, including the PCB board, the PCB board is ceramic PCB board, one side on the ceramic PCB board makes required circuit or needs the part position of paster, the ceramic PCB board has A contact surface, B contact surface and three participate in the connecting pin, and this three participate in the connecting pin is respectively TO link up 1 foot, 2 feet and 3 feet of A contact surface and B contact surface;

the ceramic PCB is provided with a synchronous rectification circuit, and the synchronous rectification circuit comprises an MOS (metal oxide semiconductor) tube, a resistor, a second capacitor and a synchronous rectification chip electrically connected with the MOS tube;

the MOS tube is fixed through conductive adhesive, a base pin D of the MOS tube is electrically connected to a contact surface A or a contact surface B of the ceramic PCB, the contact surface A and the contact surface B are conducted, and the pin 2 is electrically connected with the contact surface A or the contact surface B;

the synchronous rectification chip is fixed on the ceramic PCB through an insulating glue and is not electrically connected with the ceramic PCB;

the GATE pin of the synchronous rectification chip is connected with the G base pin of the MOS tube;

a GND pin of the synchronous rectification chip and a VS pin of the synchronous rectification chip are connected to an S-base pin of the MOS tube;

the VDD pin of the synchronous rectification chip is connected with the second capacitor, and the other end of the second capacitor is connected to the S-base pin of the MOS tube;

the VD pin of the synchronous rectification chip is connected with one end of the resistor, and the other end of the resistor is connected with the D base pin of the MOS tube;

and the S-shaped base pin of the MOS tube is conducted with the 1 pin or the 3 pins of the PCB.

Furthermore, the back of the ceramic PCB board is provided with a copper exposing structure for heat dissipation.

Further, the resistor can be replaced by a first capacitor, and after the resistor is replaced by the first capacitor, the second capacitor is replaced by a resistor.

Furthermore, the pins 1, 2 and 3 are respectively connected with metal pins.

Compared with the prior art, the beneficial effects of the utility model are that: the novel TO series SlP packaged IC packaging structure of the utility model does not need electroplating and a bar cutting system. No electroplating process is needed, and further no pollution is caused to the environment. And a bar cutting system is not needed, so that the production efficiency can be improved, and the production cost can be reduced. The utility model discloses a TO series SlP encapsulation integrated circuit's packaging structure can realize the systematic encapsulation of TO series multiwafer, many parts.

Drawings

Fig. 1 is a schematic diagram of the package structure of the TO series SlP packaged integrated circuit of the present invention.

Fig. 2 is a diagram of each pin distribution of the synchronous rectification chip of the present invention.

Fig. 3 is a schematic diagram of the synchronous rectification circuit of the present invention.

Fig. 4 is a schematic view of the a-side structure of the ceramic PCB of the present invention.

Fig. 5 is a schematic view of the structure of the side B of the ceramic PCB of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making more clear and definite definitions of the protection scope of the present invention. It is obvious that the described embodiments of the invention are only some of the embodiments of the invention, and not all of them. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.

Embodiment 1, the utility model discloses a specific structure as follows:

referring TO fig. 1-5, the novel TO series SlP package structure of the present invention includes a PCB 2, the PCB 2 is a ceramic PCB, a desired circuit or a part position requiring a chip is manufactured on one side of the ceramic PCB, the ceramic PCB has an a contact surface, a B contact surface and three pin connecting pins, the three pin connecting pins are 1 pin, 2 pins and 3 pins respectively penetrating the a contact surface and the B contact surface; the pin 1 and the pin 3 are connected and conducted or not connected;

the ceramic PCB is provided with a synchronous rectification circuit, and the synchronous rectification circuit comprises an MOS (metal oxide semiconductor) tube 4, a resistor 5, a second capacitor 6 and a synchronous rectification chip 7 electrically connected with the MOS tube 4;

the MOS tube 4 is fixed through conductive adhesive, a base pin D of the MOS tube is electrically connected to a contact surface A or a contact surface B of the ceramic PCB, the contact surface A and the contact surface B are conducted, and the pin 2 is electrically connected with the contact surface A or the contact surface B; preferably: 2 the foot is connected with the B contact surface (as shown in figure 5);

the synchronous rectification chip 7 is fixed on the ceramic PCB through an insulating glue and is not electrically connected with the ceramic PCB;

the GATE pin of the synchronous rectification chip 7 is connected with the G base pin of the MOS tube 4;

a GND pin of the synchronous rectification chip 7 and a VS pin of the synchronous rectification chip 7 are connected to an S-base pin of the MOS tube 4;

the VDD pin of the synchronous rectification chip 7 is connected with the second capacitor 6, and the other end of the second capacitor 6 is connected to the S-base pin of the MOS tube 4;

the VD pin of the synchronous rectification chip 7 is connected with one end of the resistor 5, and the other end of the resistor 5 is connected with the D pin of the MOS tube 4;

and the S-base pin of the MOS tube 4 is communicated with the pin 1 or the pin 3 of the PCB.

Further, the resistor 5 can be replaced by a first capacitor, and when the resistor 5 is replaced by the first capacitor, the second capacitor 6 is replaced by a resistor.

Furthermore, the pins 1, 2 and 3 are respectively connected with metal pins 8.

Example 2:

the utility model also discloses a novel TO series SlP encapsulates integrated circuit's packaging structure's packaging method, and this packaging method includes following step:

selecting a ceramic PCB;

manufacturing a required circuit or a part position needing to be pasted with a chip on one surface of the ceramic PCB;

thirdly, arranging a copper exposing structure on the back of the ceramic PCB for heat dissipation;

step four, prefabricating three metal pins 8;

fifthly, combining and fixing the three metal pins 8 with the 1 pin, the 2 pin and the 3 pin of the manufactured line pavement of the ceramic PCB respectively through an SMT (surface mount technology), and then fixedly attaching the resistor and the second capacitor to the manufactured line pavement;

and step six, molding the semi-finished product formed in the step five through plastic package resin, and exposing the three metal pins 8 out of the molded shell.

Example 3:

the utility model provides a synchronous rectification chip 7's model can adopt the chip of ZA2081S model.

The above only is the preferred embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the same way in the protection scope of the present invention.

Claims

1. A novel TO series SlP packaging integrated circuit packaging structure comprises a PCB (2), and is characterized in that: the PCB (2) is a ceramic PCB, a required circuit or a part position required to be pasted is manufactured on one surface of the ceramic PCB, the ceramic PCB is provided with an A contact surface, a B contact surface and three pin connecting pins, and the three pin connecting pins are respectively 1 pin, 2 pins and 3 pins penetrating through the A contact surface and the B contact surface;

the ceramic PCB is provided with a synchronous rectification circuit, and the synchronous rectification circuit comprises an MOS (metal oxide semiconductor) tube (4), a resistor (5), a second capacitor (6) and a synchronous rectification chip (7) electrically connected with the MOS tube (4);

the MOS tube (4) is fixed through conductive adhesive, a base pin D of the MOS tube is electrically connected to a contact surface A or a contact surface B of the ceramic PCB, the contact surface A and the contact surface B are conducted, and the pin 2 is electrically connected with the contact surface A or the contact surface B;

the synchronous rectification chip (7) is fixed on the ceramic PCB through an insulating glue and is not electrically connected with the ceramic PCB;

the GATE pin of the synchronous rectification chip (7) is connected with the G base pin of the MOS tube (4);

a GND pin of the synchronous rectification chip (7) and a VS pin of the synchronous rectification chip (7) are connected to an S-base pin of the MOS tube (4);

the VDD pin of the synchronous rectification chip (7) is connected with the second capacitor (6), and the other end of the second capacitor (6) is connected to the S-base pin of the MOS transistor (4);

the VD pin of the synchronous rectification chip (7) is connected with one end of the resistor (5), and the other end of the resistor (5) is connected with the D pin of the MOS tube (4);

and the S-shaped base pin of the MOS tube (4) is communicated with the 1 pin or the 3 pins on the ceramic PCB.

2. The package structure of claim 1, wherein the ceramic PCB is provided with exposed copper structures on its back side for heat dissipation.

3. The package structure of a new TO series SlP packaged ic according TO claim 1, wherein the resistor (5) can be replaced by a first capacitor, and when the resistor (5) is replaced by the first capacitor, the second capacitor (6) is replaced by a resistor.

4. The package structure of a novel TO series SlP packaged integrated circuit according TO claim 1, wherein metal pins (8) are connected TO the 1 pin, the 2 pin and the 3 pin respectively.