CN214476968U

CN214476968U - Chip capacitor

Info

Publication number: CN214476968U
Application number: CN202120901919.3U
Authority: CN
Inventors: 张继华
Original assignee: Individual
Current assignee: Triassic Guangdong Technology Co ltd
Priority date: 2021-04-28
Filing date: 2021-04-28
Publication date: 2021-10-22
Anticipated expiration: 2031-04-28

Abstract

The utility model relates to a chip capacitor, including medium base member layer, the upper surface on medium base member layer covers there is first electrode layer, and lower surface covering has the second electrode layer, be provided with first adhesion promotion layer between first electrode layer and the medium base member layer, be provided with second adhesion promotion layer between second electrode layer and the medium base member layer. Through setting up first adhesion promotion layer and second adhesion promotion layer, can strengthen the membrane base cohesion between first electrode layer and second electrode layer and the medium base member layer, prevent that first electrode layer and second electrode layer from breaking away from the medium base member layer gradually at the in-process that the condenser used, guarantee the stability and the reliability of condenser.

Description

Chip capacitor

Technical Field

The utility model belongs to the technical field of the condenser and specifically relates to a chip capacitor.

Background

In recent years, with the widespread use of electronic components in various industries, attention has been gradually turned to the reliability of components, especially the lifetime reliability, while only the performance of the components is emphasized. With the development of microwave communication technology, the used communication frequency is continuously developing towards high frequency, the frequency of civil mobile communication is developing from 900MHz to 1800MHz, and then to 2400MHz, and meanwhile, the signal frequency of military radar is gradually developing from 18GHz to 40GHz, so that electronic components such as capacitors are also continuously developing towards high frequency application field.

The chip ceramic capacitor (SLC) has no inner electrode, and has smaller Equivalent Series Inductance (ESL) value and Equivalent Series Resistance (ESR) value, so the chip ceramic capacitor has better high-frequency performance and wider application in the field of microwave communication. Because the upper electrode of the SLC generally uses Au, Ag, Al, etc. as the electrode, the bottom electrode is usually connected to the corresponding packaging area in the integrated circuit or ceramic thin film circuit by conductive adhesive or eutectic Bonding manner of AuSn, PbSn, etc., and the upper electrode is electrically interconnected with other circuit elements by Wire Bonding (Wire Bonding) technology, thereby satisfying the micro-assembly packaging process, the SLC is widely applied to microwave hybrid integrated circuits, usually plays roles of filtering, stopping, coupling, decoupling, etc., and the dosage in modern civil and military communication devices is getting larger and larger.

However, because the film-substrate bonding force between the metal electrode and the ceramic substrate is poor, the current gold-tin alloy packaging process generally places the gold-tin alloy preformed sheet in an area to be packaged first, then places the electronic component on the gold-tin preformed sheet, and then heats the gold-tin alloy preformed sheet to 270-320 ℃ to melt the gold-tin alloy preformed sheet, and when the temperature is reduced below a melting point (such as room temperature), the packaging process can be completed. The high temperature during heating and the stress that is subsequently relieved over time during subsequent use can cause portions of the electrode film layer of the capacitive device to detach from its substrate and cause the device to fail.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a chip capacitor is provided, the reliable performance of condenser when using is promoted to the membrane base cohesion between reinforcing electrode layer and the dielectric substrate.

The utility model provides a technical scheme that its technical problem adopted is: the utility model provides a chip capacitor, includes medium base member layer, the upper surface of medium base member layer covers there is first electrode layer, and lower surface covers there is the second electrode layer, be provided with first adhesion promotion layer between first electrode layer and the medium base member layer, be provided with the second adhesion promotion layer between second electrode layer and the medium base member layer.

Further, the first adhesion promoting layer and the second adhesion promoting layer are tantalum nitride layers.

Further, the thickness of the tantalum nitride layer is 10-3000 nm.

Further, the dielectric substrate layer is square.

Furthermore, the side length of the medium substrate layer is 0.3-10 mm, and the thickness of the medium substrate layer is 50-3000 microns.

Further, the dielectric substrate layer is a ceramic layer with a dielectric constant of 3-90000.

Further, the second electrode layer and the first electrode layer are single-layer metal or multi-layer metal.

Further, the single layer metal is gold, silver, copper, aluminum, nickel, titanium or platinum.

Further, the multilayer metal is titanium/gold, titanium tungsten/gold, chromium/gold, titanium tungsten/nickel/gold, titanium/copper/gold, chromium/copper/gold, molybdenum/copper/gold.

Further, the thickness of the second electrode layer and the first electrode layer is 0.01-10 μm.

The utility model has the advantages that: through setting up first adhesion promotion layer and second adhesion promotion layer, can strengthen the membrane base cohesion between first electrode layer and second electrode layer and the medium base member layer, prevent that first electrode layer and second electrode layer from breaking away from the medium base member layer gradually at the in-process that the condenser used, guarantee the stability and the reliability of condenser.

Drawings

Fig. 1 is a schematic diagram of the present invention.

Detailed Description

The present invention will be further explained with reference to the drawings and examples.

As shown in fig. 1, the utility model discloses a chip capacitor, including medium base member layer 3, the upper surface of medium base member layer 3 covers there is first electrode layer 1, and lower surface covering has second electrode layer 5, be provided with first adhesion promotion layer 2 between first electrode layer 1 and the medium base member layer 3, be provided with second adhesion promotion layer 4 between second electrode layer 5 and the medium base member layer 3.

The dielectric substrate layer 3 is made of an insulating material, and preferably a ceramic layer having a dielectric constant of 3 to 90000. The dielectric substrate layer 3 can be in various shapes such as rectangle, prism and the like, preferably square, the side length of the dielectric substrate layer is 0.3-10 mm, the thickness of the dielectric substrate layer is 50-3000 micrometers, and the specific shape and size are designed according to the actual application requirements.

The second electrode layer 5 and the first electrode layer 1 are made of conductive materials and can be single-layer metal or multi-layer metal. Specifically, the method comprises the following steps: the single-layer metal is one of gold, silver, copper, aluminum, nickel, titanium and platinum, and the thickness of the single-layer metal is 0.01-10 mu m. The multilayer metal is a stack of multiple metal layers, and the stack manner includes titanium/gold, titanium tungsten/gold (i.e. titanium tungsten layer overlaps gold layer), chromium/gold, titanium tungsten/nickel/gold (i.e. titanium tungsten layer, nickel layer and gold layer are stacked in three layers, and the stacking order is not limited), titanium/copper/gold, chromium/copper/gold, molybdenum/copper/gold. The total thickness of the multiple metal layers is 0.01-10 μm.

The first adhesion promoting layer 2 and the second adhesion promoting layer 4 are used for enhancing the bonding strength between the electrode and the medium substrate layer 3, the first adhesion promoting layer 2 and the second adhesion promoting layer 4 are made of materials which can be firmly combined with the medium substrate layer 3 and the electrode, preferably a tantalum nitride layer is adopted, the tantalum nitride film can be combined with the medium substrate layer 3 and the electrode made of metal materials, the effect of enhancing the bonding force is achieved, and meanwhile the performance of the capacitor is not influenced.

The thickness of medium base member layer 3 is greater than the thickness of second electrode layer 5 and first electrode layer 1, and the thickness of second electrode layer 5 and first electrode layer 1 is greater than the thickness of first adhesion promotion layer 2 and second adhesion promotion layer 4, the thickness of tantalum nitride layer is 10 ~ 3000nm, and it can to guarantee good bonding effect.

The utility model discloses the preparation method of condenser does: the upper surface and the lower surface of the medium substrate layer 3 are covered with a first adhesion promoting layer 2 and a second adhesion promoting layer 4, the material of the first adhesion promoting layer 2 and the second adhesion promoting layer 4 is tantalum nitride, a tantalum nitride film can be obtained through the existing sputtering or evaporation process, the second electrode layer 5 and the first electrode layer 1 can be single-layer metal, such as gold, silver, copper, aluminum, molybdenum, nickel, titanium or platinum, or multilayer metal, such as titanium/gold, titanium tungsten/gold, chromium/gold, titanium tungsten/nickel/gold, titanium/copper/gold, chromium/copper/gold, molybdenum/copper/gold, and the second electrode layer 5 and the first electrode layer 1 can be obtained through printing, sputtering, evaporation, sputtering/chemical plating or sputtering/electroplating. And preparing an electrode pattern by means of photoresist homogenizing, photoetching and etching. Finally, a plurality of chip capacitors as shown in figure 1 are obtained through splitting and cleaning.

The utility model discloses an increase first adhesion promoting layer 2 and second adhesion promoting layer 4, increased substantially the joint strength between electrode and the base member, effectively alleviated along with live time's extension, the electrode breaks away from the problem of base member gradually, can guarantee the life of condenser and the reliability of performance.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The utility model provides a chip capacitor, includes medium base member layer (3), the upper surface of medium base member layer (3) covers has first electrode layer (1), and the lower surface covers has second electrode layer (5), its characterized in that: a first adhesion promoting layer (2) is arranged between the first electrode layer (1) and the medium base body layer (3), and a second adhesion promoting layer (4) is arranged between the second electrode layer (5) and the medium base body layer (3).

2. A chip capacitor as claimed in claim 1, wherein: the first adhesion promoting layer (2) and the second adhesion promoting layer (4) are tantalum nitride layers.

3. A chip capacitor as claimed in claim 2, wherein: the thickness of the tantalum nitride layer is 10-3000 nm.

4. A chip capacitor as claimed in claim 1, wherein: the medium matrix layer (3) is square.

5. A chip capacitor according to claim 4, characterized in that: the side length of the medium matrix layer (3) is 0.3-10 mm, and the thickness is 50-3000 mu m.

6. A chip capacitor as claimed in claim 1, 4 or 5, characterized in that: the dielectric substrate layer (3) is a ceramic layer with a dielectric constant of 3-90000.

7. A chip capacitor as claimed in claim 1, wherein: the second electrode layer (5) and the first electrode layer (1) are single-layer metal or multi-layer metal.

8. A chip capacitor as claimed in claim 7, wherein: the single-layer metal is gold, silver, copper, aluminum, nickel, titanium or platinum.

9. A chip capacitor as claimed in claim 7, wherein: the multilayer metal is titanium/gold, titanium tungsten/gold, chromium/gold, titanium tungsten/nickel/gold, titanium/copper/gold, chromium/copper/gold, molybdenum/copper/gold.

10. A chip capacitor as claimed in claim 7, 8 or 9, wherein: the thickness of the second electrode layer (5) and the first electrode layer (1) is 0.01-10 mu m.