CN213459436U - Be applicable to 30um gold wire bonding chip condenser - Google Patents
Be applicable to 30um gold wire bonding chip condenser Download PDFInfo
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- CN213459436U CN213459436U CN202021289219.5U CN202021289219U CN213459436U CN 213459436 U CN213459436 U CN 213459436U CN 202021289219 U CN202021289219 U CN 202021289219U CN 213459436 U CN213459436 U CN 213459436U
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Abstract
The utility model relates to the technical field of electronic equipment, and discloses a 30um gold wire bonding chip capacitor, which is provided with a first gold electrode layer, a first transition metal layer, a ceramic dielectric body, a second transition metal layer and a second gold electrode layer from top to bottom in sequence; the thickness of the first gold electrode layer is more than or equal to 3 mu m; the first transition metal layer comprises a plurality of metal layers; the second transition metal layer comprises a plurality of metal layers; the thickness of the second gold electrode layer is greater than or equal to 3 μm. The utility model discloses the effectual problem of traditional condenser and the less enough problem of the thin gold wire bonding strength of diameter of having solved.
Description
Technical Field
The utility model relates to an electronic equipment technical field particularly, relates to a be applicable to 30um gold wire bonding chip condenser.
Background
With the continuous improvement of microwave circuit integration, the volume of elements is required to be smaller and smaller, and gold wire bonding is required to be adopted between components when the microwave integrated circuit is used; gold wire bonding refers to pressure welding of extremely fine gold wires with good ductility and conductivity on the surface of a substrate, a chip or a chip-chip; gold wire bonding is a key process in the micro-assembly technology, the bonding quality of the gold wire bonding directly affects the reliability and the electrical property stability of a product, and the main index for measuring the quality of the gold wire bonding is bonding strength. In order to ensure the reliability of a high-power or high-current module and increase the bonding strength of the gold wire, the gold wire with the thickness of 25 microns is changed into the gold wire with the thickness of 30 microns. However, in the chip capacitor used for gold wire bonding in the related art, after a gold wire of 30 μm is bonded to an electrode layer in the chip capacitor in the related art, there is a problem 1: the transition layer metal of the chip capacitor can not effectively resist the pressure and thermal stress during bonding, so that the electrode falls off; 2: the chip capacitor has insufficient bonding strength when bonding with 30 μm gold wire.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a be applicable to 30um gold wire bonding chip condenser for solve above-mentioned problem.
The utility model discloses a realize like this: a is suitable for 30um gold wire to bond the chip capacitor, from the first gold electrode layer, first transition metal layer, ceramic dielectric body, second transition metal layer and second gold electrode layer sequentially from top to bottom; the thickness of the first gold electrode layer is more than or equal to 3 mu m; the first transition metal layer comprises a plurality of metal layers; the second transition metal layer comprises a plurality of metal layers; the thickness of the second gold electrode layer is greater than or equal to 3 μm.
Furthermore, the first transition metal layer comprises a nickel layer and a titanium-tungsten alloy layer from bottom to top in sequence, and the second transition metal layer comprises a nickel-chromium layer.
Furthermore, the thickness of the nickel layer is 0.5-1 μm, the thickness of the titanium-tungsten alloy layer is 0.05-0.20 μm, and the thickness of the nickel-chromium layer is 0.5-1.0 μm.
Further, the first transition metal layer sequentially comprises a titanium tungsten layer and a titanium layer from top to bottom, and the second transition metal layer sequentially comprises a platinum layer and a titanium layer from top to bottom.
Furthermore, the thickness of the titanium layer is 0.05-0.20 μm, the thickness of the titanium-tungsten layer is 0.05-0.20 μm, the thickness of the platinum layer is 0.5-1.0 μm, and the thickness of the titanium layer is 0.5-1.0 μm.
The first gold electrode sub-layer is arranged inside the ceramic dielectric body and is parallel to the first gold electrode layer, the second gold electrode sub-layer is arranged inside the ceramic dielectric body and is parallel to the second gold electrode layer, the first gold electrode layer is connected with the first gold electrode sub-layer through vertical via holes, the second gold electrode layer is connected with the second gold electrode sub-layer through vertical via holes, the first gold electrode sub-layer is arranged close to the second gold electrode sub-layer, the second gold electrode sub-layer is arranged close to the first gold electrode layer, and the projection surfaces of the first gold electrode sub-layer and the second gold electrode sub-layer in the direction perpendicular to the first gold electrode layer are overlapped.
Furthermore, the overlapping area of the projection surfaces of the first gold electrode sublayer and the second gold electrode sublayer in the direction perpendicular to the first gold electrode layer is more than or equal to 70% of the area of the first gold electrode layer.
Furthermore, the ceramic dielectric body is divided into three layers by the first gold electrode sub-layer, the second gold electrode sub-layer, the first gold electrode layer and the second gold electrode layer.
The utility model has the advantages that: the utility model provides a be applicable to 30um gold wire bonding chip condenser:
1: the thickness of the first gold electrode layer and the second gold electrode layer is changed to be more than or equal to 3 microns, so that bonding with a gold wire with the thickness of 30 microns is increased;
2: the first transition metal layer and the second transition metal layer are arranged between the first gold electrode layer and the ceramic dielectric body, so that the connection strength of the first gold electrode layer and the ceramic dielectric body is increased in sequence, the problem that the electrodes are stripped from the ceramic dielectric body due to thermal stress and mechanical stress during bonding is avoided, the bonding strength is increased, and the reliability of the module is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a 30um gold wire bonded chip capacitor according to an embodiment;
FIG. 2 is a schematic diagram of a test for a 30um gold wire bonded chip capacitor according to an embodiment;
fig. 3 is a schematic structural diagram of a capacitor suitable for a 30um gold wire bonded chip according to the fourth embodiment;
in the figure: 100-a first gold electrode layer, 110-a first gold electrode sub-layer, 200-a first transition metal layer, 300-a ceramic dielectric body, 400-a second transition metal layer, 500-a second gold electrode layer, 510-a second gold electrode sub-layer, and 600-a vertical via hole.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "inside" and "outside" are used for indicating the position or positional relationship based on the position or positional relationship shown in the drawings, or the position or positional relationship that the utility model is usually placed when using, and are only for convenience of describing the present invention and simplifying the description, but not for indicating or implying that the device or element to be referred must have a specific position, be constructed and operated in a specific position, and thus should not be construed as limiting the present invention.
The terms "first," "second," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The first embodiment is as follows:
as shown in fig. 1, the first gold electrode layer 100, the first transition metal layer 200, the ceramic dielectric body 300, the second transition metal layer 400 and the second gold electrode layer 500 are sequentially arranged from top to bottom; the thickness of the first gold electrode layer 100 is equal to 3 μm; the first transition metal layer 200 includes a plurality of metal layers, and the first transition metal layer is: one or more of titanium tungsten, nickel chromium, titanium tungsten and platinum; specifically, the first transition metal layer 200 sequentially comprises a nickel layer with a thickness of 0.7 μm and a titanium-tungsten alloy layer with a thickness of 0.10 μm from top to bottom; the second transition metal layer 400 includes a plurality of metal layers, and the second transition metal layer is: one or more of titanium tungsten, nickel-chromium, titanium tungsten and platinum are combined, and specifically, the first transition layer metal is a nickel-chromium layer with the thickness of 0.70 mu m; the thickness of the second gold electrode layer 500 is equal to 3 μm; with the above settings, comparative tensile tests of 25 μm and 30 μm were performed: three tests were performed on each of the 9 positions to be measured, with the following results:
as can be seen from the above test, the bonding strength with the gold wire of 30 μm is higher in this example.
Example two:
in the present embodiment, the first gold electrode layer 100, the first transition metal layer 200, the ceramic dielectric body 300, the second transition metal layer 400 and the second gold electrode layer 500 are sequentially disposed from top to bottom; the thickness of the first gold electrode layer 100 is equal to 3 μm; the first transition metal layer 200 comprises a plurality of metal layers, and specifically, the first transition metal layer 200 sequentially comprises a nickel layer with a thickness of 0.5 μm and a titanium-tungsten alloy layer with a thickness of 0.05 μm from top to bottom; the second transition metal layer 400 includes a plurality of metal layers, specifically, a first transition metal layer is a nickel-chromium layer with a thickness of 0.5 μm; the thickness of the second gold electrode layer 500 is equal to 3 μm; with the above settings, comparative tensile tests of 25 μm and 30 μm were performed: three tests were performed on each of the 9 positions to be measured, with the following results:
as can be seen from the above test, the bonding strength with the gold wire of 30 μm is higher in this example.
Example three:
in the present embodiment, the first gold electrode layer 100, the first transition metal layer 200, the ceramic dielectric body 300, the second transition metal layer 400 and the second gold electrode layer 500 are sequentially disposed from top to bottom; the thickness of the first gold electrode layer 100 is equal to 3 μm; the first transition metal layer 200 comprises a plurality of metal layers, and specifically, the first transition metal layer 200 sequentially comprises a nickel layer with the thickness of 1 μm and a titanium-tungsten alloy layer with the thickness of 0.20 μm from top to bottom; the second transition metal layer 400 includes a plurality of metal layers, specifically, a first transition metal layer is a nickel-chromium layer with a thickness of 1 μm; the thickness of the second gold electrode layer 500 is equal to 3 μm; with the above settings, comparative tensile tests of 25 μm and 30 μm were performed: three tests were performed on each of the 9 positions to be measured, with the following results:
as can be seen from the above test, the bonding strength with the gold wire of 30 μm is higher in this example.
Example four:
in order to overcome the problem of low capacitance density of single-layer ceramic, the capacitor is constructed by adopting a multilayer structure in the embodiment, and meanwhile, the strength of the capacitor is improved.
As shown in fig. 3, the present embodiment is substantially the same as the first embodiment, and has a difference that the present embodiment further includes a first gold electrode sub-layer 110 and a second gold electrode sub-layer 510, the first gold electrode sub-layer 110 is disposed inside the ceramic dielectric body 300 and is parallel to the first gold electrode layer 100, the second gold electrode sub-layer 510 is disposed inside the ceramic dielectric body 300 and is parallel to the second gold electrode layer 500, the first gold electrode layer 100 and the first gold electrode sub-layer 110 are connected by a vertical via 600, the second gold electrode layer 500 and the second gold electrode sub-layer 510 are connected by a vertical via 600, the first gold electrode sub-layer 110 is disposed close to the second gold electrode sub-layer 510, the second gold electrode sub-layer 510 is disposed close to the first gold electrode layer 100, and projection planes of the first gold electrode sub-layer 110 and the second gold electrode sub-layer 510 in a direction perpendicular to the first gold electrode layer 100 are overlapped and an overlapping area is 85%.
It should be noted that in some other embodiments, the first gold electrode sublayer 110, the second gold electrode sublayer 510, the first gold electrode layer 100, and the second gold electrode layer 500 divide the ceramic dielectric body 300 into three layers.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A30 um gold wire bonding chip capacitor is characterized in that a capacitor body is sequentially arranged from top to bottom
A first gold electrode layer; the thickness of the first gold electrode layer is more than or equal to 3 mu m;
a first transition metal layer; the first transition metal layer comprises a plurality of metal layers;
a ceramic dielectric body;
a second transition metal layer; the second transition metal layer comprises a plurality of metal layers;
a second gold electrode layer; the thickness of the second gold electrode layer is more than or equal to 3 mu m.
2. The chip capacitor of claim 1, wherein the first transition metal layer comprises a nickel layer and a titanium-tungsten alloy layer from bottom to top, and the second transition metal layer comprises a nickel-chromium layer.
3. The chip capacitor of claim 2, wherein the nickel layer has a thickness of 0.5-1 μm, the titanium-tungsten alloy layer has a thickness of 0.05-0.20 μm, and the nickel-chromium layer has a thickness of 0.5-1.0 μm.
4. The chip capacitor suitable for 30um gold wire bonding as claimed in claim 1, wherein the first transition metal layer comprises a TiW layer and a Ti layer in sequence from bottom to top, and the second transition metal layer comprises a Pt layer and a Ti layer in sequence from top to bottom.
5. The chip capacitor of claim 4, wherein the titanium layer has a thickness of 0.05-0.20 μm, the TiW layer has a thickness of 0.05-0.20 μm, the Pt layer has a thickness of 0.5-1.0 μm, and the titanium layer has a thickness of 0.5-1.0 μm.
6. The chip capacitor suitable for 30um gold wire bonding of claim 1, further comprising a first gold electrode sub-layer and a second gold electrode sub-layer, wherein the first gold electrode sub-layer is disposed inside the ceramic dielectric body and parallel to the first gold electrode layer, the second gold electrode sub-layer is disposed inside the ceramic dielectric body and parallel to the second gold electrode layer, the first gold electrode layer and the first gold electrode sub-layer are connected through a vertical via hole, the second gold electrode layer and the second gold electrode sub-layer are connected through a vertical via hole, the first gold electrode sub-layer is disposed close to the second gold electrode sub-layer, the second gold electrode sub-layer is disposed close to the first gold electrode layer, and projection planes of the first gold electrode sub-layer and the second gold electrode sub-layer are overlapped in a direction perpendicular to the first gold electrode layer.
7. The chip capacitor of claim 6, wherein the overlapping area of the projection planes of the first gold electrode sublayer and the second gold electrode sublayer in the direction perpendicular to the first gold electrode layer is greater than or equal to 70% of the area of the first gold electrode layer.
8. The chip capacitor of claim 7, wherein the first gold electrode sublayer, the second gold electrode sublayer, the first gold electrode layer and the second gold electrode layer divide the ceramic dielectric into three layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021289219.5U CN213459436U (en) | 2020-07-03 | 2020-07-03 | Be applicable to 30um gold wire bonding chip condenser |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021289219.5U CN213459436U (en) | 2020-07-03 | 2020-07-03 | Be applicable to 30um gold wire bonding chip condenser |
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| Publication Number | Publication Date |
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| CN213459436U true CN213459436U (en) | 2021-06-15 |
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| CN202021289219.5U Active CN213459436U (en) | 2020-07-03 | 2020-07-03 | Be applicable to 30um gold wire bonding chip condenser |
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