CN214279157U

CN214279157U - Image signal processing circuit

Info

Publication number: CN214279157U
Application number: CN202023067033.8U
Authority: CN
Inventors: 孙健
Original assignee: Nanjing Weijing Shikong Information Technology Co ltd
Current assignee: Nanjing Weijing Shikong Information Technology Co ltd
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2021-09-24
Anticipated expiration: 2030-12-18

Abstract

The utility model relates to an image signal processing circuit, belonging to the technical field of three-dimensional dynamic visual VR; an image signal processing circuit includes: the device comprises a processing module, an optimization module and an output module; the processing module comprises: synchronous separating circuit and amplifier circuit, the optimization module includes: a photoelectric isolation circuit; the utility model discloses a when a large amount of image signal processing need be carried out, and these image signal are mingled with not few clutter signals, carry out clutter signal's elimination in the signal through the synchronous separation circuit among the processing module, and amplify the output to output signal, thereby can reduce the output that causes the image signal and form fuzzy and cracked danger; simultaneously because the reason of work load, the work of high power can make the voltage signal of output disturb image signal, the utility model discloses a photoelectric isolation circuit carries out the signal of telecommunication and the isolation of input/output image signal to guarantee the stability of signal.

Description

Image signal processing circuit

Technical Field

The utility model relates to an image signal processing circuit belongs to three-dimensional dynamic visual VR technical field.

Background

Virtual reality, also known as VR technology, can be applied in the fields of city planning, interior design, movie tv, games, etc., and is well known only for its application in the viewing of movie tv, as well as in virtual reality games. The application of VR technology in building design is briefly introduced, and the VR technology is fused with building information model technology (BIM), so that the building information model has a more obvious display effect, and the combination of the VR technology and the BIM technology is the development trend of the building design industry in the future.

At present, the development of computer graphics technology is very rapid, and a solid technical foundation is provided for the appearance of virtual simulation technical products. In recent years, three-dimensional dynamic virtual simulation has attracted general attention as one of important technical fields of computer simulation. The virtual simulation technology research not only has great significance in the field of computer graphics, but also has important theoretical research significance and engineering practical value in the traditional field. The traditional field is a special natural environment, is complex and changeable, has irregularity in both time and space, and therefore, the mathematical modeling and simulation implementation of the traditional field are relatively complex processes.

In addition, in the existing three-dimensional dynamic visual scene VR technology, a large number of image signals are required to be imaged, and the image signals are collected and transmitted through various sensors, wherein a plurality of clutter signals are mixed, and the clutter signals can cause imaging blur and fracture danger to the output of the image signals; meanwhile, due to the workload, the high-power operation can cause the output voltage signal to interfere with the image signal.

SUMMERY OF THE UTILITY MODEL

Utility model purpose: an image signal processing circuit is provided that solves the above-mentioned problems.

The technical scheme is as follows: an image signal processing circuit comprising:

a processing module, the processing module comprising: a synchronous separation circuit, an amplification circuit connected to the synchronous separation circuit; the processing module is mainly used for eliminating clutter signals of image signals and stably outputting output signals;

an optimization module, the optimization module comprising: a photoelectric isolation circuit; the optimization module is mainly used for carrying out isolation transmission on interference of analog signals and digital signals in electric signal transmission;

and the output module is used for outputting the signal.

In a further embodiment, the synchronization separation circuit comprises: the circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a polar capacitor C2, a polar capacitor C3, a polar capacitor C4, a polar capacitor C5, a polar capacitor C6, a triode Q1, a triode Q2 and a triode Q3;

one end of the resistor R6 is connected to one end of the polar capacitor C2 and receives an input signal, a base of the transistor Q1 is connected to one end of the resistor R10 and one end of the resistor R5 at the same time and to the other end of the polar capacitor C2, a collector of the transistor Q1 is connected to one end of the polar capacitor C3 and one end of the resistor R11 at the same time, an emitter of the transistor Q1 is connected to one end of the resistor R12, the other end of the resistor R5 is connected to the other end of the resistor R12 and grounded, the other end of the resistor R11 is connected to the other end of the resistor R10 and receives an operating voltage, a base of the transistor Q2 is connected to one end of the resistor R7 and the other end of the polar capacitor C3 at the same time and a collector of the transistor Q2 is connected to one end of the resistor R9 and one end of the polar capacitor C6 at the same time and the other end of the resistor R7 is connected to the other end of the resistor R9 and receives an operating voltage, an emitter of the triode Q2 is simultaneously connected with one end of the resistor R13 and one end of the polar capacitor C4, the other end of the resistor R13 is simultaneously connected with one end of the resistor R14, the other end of the polar capacitor C4 and one end of the polar capacitor C5, the other end of the resistor R14 is connected with the other end of the polar capacitor C5 and grounded, the other end of the polar capacitor C6 is connected with one end of the resistor R8, a base of the triode Q3 is connected with the other end of the resistor R8, an emitter of the triode Q3 is grounded, a collector of the triode Q3 is connected with one end of the resistor R15 and outputs a signal, and a voltage is input to the other end of the resistor R15;

the synchronous separation circuit eliminates signals which do not conform to work by comparing the levels of clutter signals in the input signals.

In a further embodiment, the amplification circuit comprises: the circuit comprises a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an amplifier U3A, an amplifier U3B and a capacitor C7;

the pin 2 of the amplifier U3A is connected to one end of the resistor R16 and one end of the resistor R17 at the same time, the other end of the resistor R16 is grounded, the pin 3 of the amplifier U3A inputs a signal, the pin No. 4 of the amplifier U3A is grounded, the pin No. 1 of the amplifier U3A is simultaneously connected with the other end of the resistor R17 and one end of the resistor R18, the No. 8 pin of the amplifier U3A is inputted with voltage, the No. 5 pin of the amplifier U3A is connected with the other end of the resistor R18, the No. 8 pin of the amplifier U3A is inputted with voltage, the No. 4 pin of the amplifier U3A is grounded, the pin No. 6 and the pin No. 7 of the amplifier U3A are connected with one end of the resistor R19, the other end of the resistor R19 is simultaneously connected with one end of the resistor R20 and the other end of the capacitor C7 and outputs signals, and the other end of the capacitor C7 is connected with the other end of the resistor R20 and is grounded;

the amplifying circuit performs secondary amplification on the output signal through two paths of amplifiers, so that the stability of the signal is kept.

In a further embodiment, the optoelectronic isolation circuit comprises: the circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an adjustable resistor RV1, a capacitor C1, an amplifier U2A and a photoelectric isolator U1;

pin No. 2 of the opto-isolator U1 is connected to one end of the resistor R1, signal is input from the other end of the resistor R1, pin No. 1 of the opto-isolator U1 is connected to one end of the resistor R2, signal is input from the other end of the resistor R2, pin No. 4 of the opto-isolator U1 is simultaneously connected to one end of the resistor R3 and one end of the resistor R4, voltage is input from the other end of the resistor R3, pin No. 3 of the opto-isolator U1 is simultaneously connected to one end of the adjustable resistor RV1, one end of the capacitor C1 and pin No. 4 of the amplifier U2A and grounded, pin No. 3 of the amplifier U2A is simultaneously connected to the other end of the capacitor C1 and the control end of the adjustable resistor RV1, the other end of the adjustable resistor RV1 is connected to the other end of the resistor R4, pin No. 2 of the amplifier U2A is connected to pin No. 1 and signal is output, the pin 8 of the amplifier U2A inputs the operating voltage.

Has the advantages that: the utility model discloses a when a large amount of image signal processing need be carried out, and these image signal are mingled with not few clutter signals, carry out clutter signal's elimination in the signal through the synchronous separation circuit among the processing module, and amplify the output to output signal, thereby can reduce the output that causes the image signal and form fuzzy and cracked danger; simultaneously because the reason of work load, the work of high power can make the voltage signal of output disturb image signal, the utility model discloses a photoelectric isolation circuit carries out the signal of telecommunication and the isolation of input/output image signal to guarantee the stability of signal.

Drawings

Fig. 1 is a working block diagram of the processing module of the present invention.

Fig. 2 is a diagram of the optoelectronic isolation circuit of the present invention.

Fig. 3 is a circuit diagram of the synchronous separation circuit of the present invention.

Fig. 4 is an amplification circuit diagram of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these details; in other instances, well-known features have not been described in order to avoid obscuring the present invention.

An image signal processing circuit comprising: the device comprises a processing module, an optimization module and an output module.

As shown in fig. 1, the processing module includes: and the synchronous separation circuit is connected with the amplifying circuit.

As shown in fig. 2, the photoelectric isolation circuit includes: the circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an adjustable resistor RV1, a capacitor C1, an amplifier U2A and a photoelectric isolator U1.

As shown in fig. 3, the synchronization separating circuit includes: the circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a polar capacitor C2, a polar capacitor C3, a polar capacitor C4, a polar capacitor C5, a polar capacitor C6, a triode Q1, a triode Q2 and a triode Q3.

As shown in fig. 4, the amplifying circuit includes: the circuit comprises a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an amplifier U3A, an amplifier U3B and a capacitor C7.

In one embodiment, one end of the resistor R6 is connected to one end of the polar capacitor C2 and receives a signal, a base of the transistor Q1 is connected to one end of the resistor R10 and one end of the resistor R5 at the same time and the other end of the polar capacitor C2 at the same time, a collector of the transistor Q1 is connected to one end of the polar capacitor C3 and one end of the resistor R11 at the same time, an emitter of the transistor Q1 is connected to one end of the resistor R12, the other end of the resistor R5 is connected to the other end of the resistor R12 and grounded, the other end of the resistor R11 is connected to the other end of the resistor R10 and receives an operating voltage, a base of the transistor Q2 is connected to one end of the resistor R7 and the other end of the polar capacitor C3 at the same time, and a collector of the transistor Q2 is connected to one end of the resistor R9 and one end of the polar capacitor C6 at the same time, the other end of the resistor R7 is connected to the other end of the resistor R9 and inputs a working voltage, the emitter of the triode Q2 is connected to one end of the resistor R13 and one end of the polar capacitor C4, the other end of the resistor R13 is connected to one end of the resistor R14, the other end of the polar capacitor C4 and one end of the polar capacitor C5, the other end of the resistor R14 is connected to the other end of the polar capacitor C5 and grounded, the other end of the polar capacitor C6 is connected to one end of the resistor R8, the base of the triode Q3 is connected to the other end of the resistor R8, the emitter of the triode Q3 is grounded, the collector of the triode Q3 is connected to one end of the resistor R15 and outputs a signal, and the other end of the resistor R15 inputs a voltage.

In one embodiment, pin 2 of the amplifier U3A is connected to both one end of the resistor R16 and one end of the resistor R17, the other end of the resistor R16 is grounded, the pin 3 of the amplifier U3A inputs a signal, the pin No. 4 of the amplifier U3A is grounded, the pin No. 1 of the amplifier U3A is simultaneously connected with the other end of the resistor R17 and one end of the resistor R18, the No. 8 pin of the amplifier U3A is inputted with voltage, the No. 5 pin of the amplifier U3A is connected with the other end of the resistor R18, the No. 8 pin of the amplifier U3A is inputted with voltage, the No. 4 pin of the amplifier U3A is grounded, the pin No. 6 and the pin No. 7 of the amplifier U3A are connected with one end of the resistor R19, the other end of the resistor R19 is connected with one end of the resistor R20 and the other end of the capacitor C7 at the same time and outputs signals, and the other end of the capacitor C7 is connected with the other end of the resistor R20 and is grounded.

In one embodiment, pin No. 2 of the opto-isolator U1 is connected to one end of the resistor R1, the other end of the resistor R1 is used for inputting signals, pin No. 1 of the opto-isolator U1 is connected to one end of the resistor R2, the other end of the resistor R2 is used for inputting signals, pin No. 4 of the opto-isolator U1 is simultaneously connected to one end of the resistor R3 and one end of the resistor R4, the other end of the resistor R3 is used for inputting voltages, pin No. 3 of the opto-isolator U1 is simultaneously connected to one end of the adjustable resistor RV1, one end of the capacitor C1 and pin No. 4 of the amplifier U2A and is grounded, pin No. 3 of the amplifier U2A is simultaneously connected to the other end of the capacitor C1 and a control end of the adjustable resistor RV1, the other end of the adjustable resistor RV1 is connected to the other end of the resistor R4, pin No. 2 of the amplifier U2A is connected to the pin No. 1 and is used for outputting signals, the pin 8 of the amplifier U2A inputs the operating voltage.

The working principle is as follows: when the three-dimensional dynamic scene works, image signals are collected through a sensor, the collected image signals are transmitted to an image processing circuit for processing and outputting, when the signals are input, the signals are input through a synchronous separation circuit, peak voltage is absorbed through a resistor R6 and a polar capacitor C2, the peak voltage is input into a base electrode of a triode Q1, the triode Q1 is conducted according to the discharge of the polar capacitor C2, meanwhile, a collector electrode of a triode Q1 outputs the signals to a base electrode of a triode Q2, a resistor R7 is matched with the polar capacitor C2 to stabilize the input, so that the input voltage is prevented from being overlarge, the triode Q2 is input to eliminate noise waves, the signals are output to a triode Q3 through a collector electrode of a triode Q2, the triode Q3 shapes the signals, the noise waves which do not reach the level are eliminated, and the noise waves are output through the collector electrode of a triode Q3;

an output signal is input through a pin 3 of the amplifier U3A, the amplifier U3A performs primary amplification, the input value amplifier U3B performs secondary amplification, and meanwhile, a pin 7 of the amplifier U3B performs output signal, and protection output is performed through the capacitor C7 and the resistor R20;

when signal processing is carried out, isolation input is carried out through the photoelectric isolation module, an input signal is input into the photoelectric isolator U1 through the resistor R1, the photoelectric isolator U1 is protected to the amplifier U2A, the adjustable resistor RV1 adjusts input voltage, the capacitor C1 carries out filtering, and the signal is output through the No. 1 pin of the amplifier U2A.

The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the details of the above embodiments, and the technical concept of the present invention can be modified to perform various equivalent transformations, which all belong to the protection scope of the present invention.

Claims

1. An image signal processing circuit characterized by comprising:

a processing module, the processing module comprising: a synchronous separation circuit, an amplification circuit connected to the synchronous separation circuit;

an optimization module, the optimization module comprising: a photoelectric isolation circuit;

and the output module is used for outputting the signal.

2. The image signal processing circuit according to claim 1, wherein the synchronization separation circuit comprises: the circuit comprises a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a polar capacitor C2, a polar capacitor C3, a polar capacitor C4, a polar capacitor C5, a polar capacitor C6, a triode Q1, a triode Q2 and a triode Q3;

one end of the resistor R6 is connected to one end of the polar capacitor C2 and receives an input signal, a base of the transistor Q1 is connected to one end of the resistor R10 and one end of the resistor R5 at the same time and to the other end of the polar capacitor C2, a collector of the transistor Q1 is connected to one end of the polar capacitor C3 and one end of the resistor R11 at the same time, an emitter of the transistor Q1 is connected to one end of the resistor R12, the other end of the resistor R5 is connected to the other end of the resistor R12 and grounded, the other end of the resistor R11 is connected to the other end of the resistor R10 and receives an operating voltage, a base of the transistor Q2 is connected to one end of the resistor R7 and the other end of the polar capacitor C3 at the same time and a collector of the transistor Q2 is connected to one end of the resistor R9 and one end of the polar capacitor C6 at the same time and the other end of the resistor R7 is connected to the other end of the resistor R9 and receives an operating voltage, the emitter of the triode Q2 is connected with one end of the resistor R13 and one end of the polar capacitor C4, the other end of the resistor R13 is connected with one end of the resistor R14, the other end of the polar capacitor C4 and one end of the polar capacitor C5, the other end of the resistor R14 is connected with the other end of the polar capacitor C5 and grounded, the other end of the polar capacitor C6 is connected with one end of the resistor R8, the base of the triode Q3 is connected with the other end of the resistor R8, the emitter of the triode Q3 is grounded, the collector of the triode Q3 is connected with one end of the resistor R15 and outputs a signal, and the other end of the resistor R15 inputs a voltage.

3. The image signal processing circuit according to claim 1, wherein the amplifying circuit comprises: the circuit comprises a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an amplifier U3A, an amplifier U3B and a capacitor C7;

the pin 2 of the amplifier U3A is connected to one end of the resistor R16 and one end of the resistor R17 at the same time, the other end of the resistor R16 is grounded, the pin 3 of the amplifier U3A inputs a signal, the pin No. 4 of the amplifier U3A is grounded, the pin No. 1 of the amplifier U3A is simultaneously connected with the other end of the resistor R17 and one end of the resistor R18, the No. 8 pin of the amplifier U3A is inputted with voltage, the No. 5 pin of the amplifier U3A is connected with the other end of the resistor R18, the No. 8 pin of the amplifier U3A is inputted with voltage, the No. 4 pin of the amplifier U3A is grounded, the pin No. 6 and the pin No. 7 of the amplifier U3A are connected with one end of the resistor R19, the other end of the resistor R19 is connected with one end of the resistor R20 and the other end of the capacitor C7 at the same time and outputs signals, and the other end of the capacitor C7 is connected with the other end of the resistor R20 and is grounded.

4. The image signal processing circuit of claim 1, wherein the optoelectronic isolation circuit comprises: the circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an adjustable resistor RV1, a capacitor C1, an amplifier U2A and a photoelectric isolator U1;