CN214278785U

CN214278785U - Server mainboard

Info

Publication number: CN214278785U
Application number: CN202120117836.5U
Authority: CN
Inventors: 李世坤
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2021-01-15
Filing date: 2021-01-15
Publication date: 2021-09-24
Anticipated expiration: 2031-01-15

Abstract

The utility model discloses a server mainboard, including CPU0 and CPU1, CPU0 and CPU1 pass through GMI interface connection; the Port0 of the CPU0 is connected with a RAID controller, the Port1 is set as two Slimline interfaces, and the Port2 is set as a GenZ interface; port0 of the CPU1 is set to two Slimline interfaces, Port1 is set to PCIe x8slot, Port2 is set to GenZ interface, Port3 is set to PCIe x16 slot. The utility model provides a sea light 7000 CPU's server mainboard SATA interface not support the problem of establishing RAID, can also adapt to nimble extension.

Description

Server mainboard

Technical Field

The utility model relates to an integrated circuit board design field, concretely relates to server mainboard.

Background

In order to improve the level of high-tech research and development and manufacture in China and deal with the technical blockade of the United states, domestic CPUs (Central Processing units) have been developed rapidly in recent years, wherein CPUs such as Loongson, Shenwei, Feiteng, Mega-Guo, Kunpeng, Hai and the like are mainly applied, the CPUs are divided into different types such as X86, MIPS, ARM and the like due to different architectures, the Loongson and Feiteng are mainly applied to desktop PCs (Personal computers) and servers, and the performance is slightly poor. Whereas the marine CPU is a member of the X86 processor, both computing power and PCIe resources can compete with Intel CPUs. Currently, the marine light has launched 7200 series of processors, each of which supports 8-channel DDR4 memory (Double Data Rate memory, fourth generation dual Rate memory), 8-channel 16-bit PCIe (Peripheral Component Interconnect Express) channel, where 4 channels are used for interconnection between CPUs, and the Rate is as high as 10.6 GT/s.

However, the public board based on the marine 7000CPU has a simple interface, is not flexible enough to extend, and cannot support a GPU (Graphics Processing Unit) and a SATA (Serial Advanced Technology Attachment) interface, so that it does not support the formation of a Redundant Array of Independent Disks (RAID).

Disclosure of Invention

In order to solve the technical problem, the utility model provides a server mainboard can establish RAID, selects configuration PCIe resource in a flexible way.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a server motherboard comprising a CPU0 and a CPU1, the CPU0 and the CPU1 being connected by a GMI interface;

the Port0 of the CPU0 is connected with a RAID controller, the Port1 is set as two Slimline interfaces, and the Port2 is set as a GenZ interface;

port0 of the CPU1 is set to two Slimline interfaces, Port1 is set to PCIe x8slot, Port2 is set to GenZ interface, Port3 is set to PCIe x16 slot.

Further, the RAID controller is ASM 1061R.

Further, the PCIe interface of the RAID controller ASM1061R is connected to Port0 of the CPU 0;

the two SATA interfaces of ASM1061R are connected to the two SATA connectors of the motherboard;

the clock interface of ASM1061R connects the crystal;

the serial peripheral interface of the ASM1061R is connected with Flash;

configuration pins of ASM1061R connect to the baseboard management controller.

Further, the two Slimline interfaces of the CPU0 are connected to a Riser board having two PCIe x8 slots;

the GenZ interface of CPU0 and PCIe x16 slot of CPU1 are connected to a Riser board having one PCIe x16 slot and two PCIe x8 slots;

the two Slimline interfaces of the CPU1 are connected to a Riser board with two PCIe x8 slots;

the PCIe x8slot of CPU1 and the GenZ interface of CPU1 connect to a Riser board having three PCIe x8 slots.

Further, each Slimline interface of the CPU0 and the CPU1 is connected with 2 NVMe disks respectively;

each GenZ interface of the CPU0 and CPU1 is connected to 4 NVMe disks, respectively.

Further, two Slimline interfaces of the CPU0 are connected with the GPU 1; the GenZ interface of the CPU0 is connected with a GPU 2;

two Slimline interfaces of the CPU1 are connected with a GPU 3; the GenZ interface of the CPU1 is connected to the GPU 4.

Further, the CPU0 is also connected to the baseboard management controller and the network controller, and is provided with a built-in Mezz card interface and an OCP3.0 interface.

The utility model has the advantages that:

the utility model discloses a provide a server mainboard, the server mainboard SATA interface of having solved the aurora 7000CPU does not support the problem of establishing RAID, can expand in a flexible way.

After the RAID is built, when 1 block of system disk fails, the normal operation of the whole system is not influenced. Moreover, the utility model discloses richen sealight 7000 CPU's PCIE resource, according to the nimble configuration of configuration demand of difference, at most support 10 standard PCIe trench, perhaps provide 16NVMe hard disk interface, perhaps support 4 full-width GPUs, provide basic functions such as board-mounted network card, SATA, USB, display card simultaneously, can satisfy diversified demand.

Drawings

FIG. 1 is a schematic diagram of a motherboard structure of a prior art Hai Guang 7000 official server.

Fig. 2 is a schematic diagram of the improved server motherboard structure according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a connection structure of a RAID controller according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a PCIe configuration connection structure according to embodiment 10 of the present invention.

Fig. 5 is a schematic diagram of the connection structure of the embodiment 16NVMe configuration of the present invention.

Fig. 6 is a schematic diagram of the GPU configuration connection structure according to embodiment 4 of the present invention.

Detailed Description

In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.

As shown in fig. 1, the server motherboard design of the maritime light 7000 edition mainly includes a maritime light 7000CPU, a DDR4 memory, a BMC AST2500, a CPLD, a USB, a network interface, and other external interfaces. When the I/O interface of the CPU of the marine lighting 7000 is configured as SATA, RAID cannot be configured, and when there is a failure of 1 system disk, normal operation of the entire system is affected. Moreover, the PCIe slot of the CPU of the marine light 7000 is designed into a fixed interface style of X8 or X16 or X20, cannot adapt to the change of configuration, and has limited types of external plug-in cards and limited application scenes.

In order to solve the above problem, as shown in fig. 2, an embodiment of the present invention discloses a server motherboard, which includes a CPU0 and a CPU1, where the CPU0 and the CPU1 are connected through a GMI interface;

Specifically, Port0 lane [2] of the CPU0 is connected to the RAID controller ASM1061R, the ASM1061R converts 1 interface of pci ex1 into two SATA3.0 interfaces, supports RAID0, RAID1 and AHCI modes, and can switch different modes according to use needs. The RAID chip can also adopt other types of chips.

Lan [0] of the CPU0 Port0 is connected to a Baseboard Management Controller (BMC) to manage the system health status.

Lane [2] of CPU0 Port0 connects to RAID controller, manages SATA interface system disks.

The Lane [4:7] of CPU0 Port0 is connected to the network controller and can provide a two gigabit Port.

Lane [0:7] of the CPU0 Port1 can be configured in SATA or PCIe mode, is designed as Slimline interface, and can be connected with a SATA back panel or an NVMe back panel according to different requirements.

Lane [8:15] of the CPU0 Port1 only supports PCIe mode, is also designed into Slimline interface, and can be connected with NVMe backboard or Riser card.

Lane [0:15] of CPU0 Port2 is designed as GenZ interface, and can be inserted into a Riser card or connected with NVMe disk.

Lane [0:7] of CPU0 Port3 is designed as a built-in Mezz card interface, and external interface space is saved.

Lane [8:15] of CPU0 Port3 is designed as an OCP3.0 interface.

Lane [0:7] of the CPU1 Port0 can be configured in SATA or PCIe mode, is designed as Slimline interface, and can be connected with a SATA back panel or an NVMe back panel according to different requirements.

Lane [8:15] of the CPU1 Port0 only supports PCIe mode, is also designed into Slimline interface, and can be connected with NVMe backboard or Riser card.

Lane [0:7] of the CPU1 Port1 can be configured in SATA or PCIe mode, is designed as Slimline interface, and can be connected with a SATA back panel or an NVMe back panel according to different requirements.

Lane [8:15] of the CPU1 Port1 only supports a PCIe mode, is designed into a standard PCIe x8slot, can be vertically inserted with a PCIe card, and can also be combined with a GenZ interface to form a Riser card interface.

Lane [0:15] of CPU1 Port2 is designed as GenZ interface, and can be inserted into a Riser card or connected with NVMe disk.

Lane [0:15] of the CPU1 Port3 is designed into a standard PCIe x16 slot, can be vertically inserted with a PCIe card, and can also be combined with a GenZ interface to form a Riser card interface.

When the RAID controller is the ASM1061R, a schematic connection diagram of the board is shown in fig. 3. Lane [2] of the CPU0 Port0 of the sea light 7000 is connected to a PCIe interface of the ASM 1061R; connecting the two SATA interfaces of the ASM1061R to the two SATA connectors of the motherboard; connecting the crystal to a clock interface of the ASM 1061R; connecting Flash to an SPI interface of the ASM 1061R; the configuration pins of ASM1061R are connected to the BMC.

When the mainboard power supply is connected to a power supply and started, the ASM1061R control module completes power-on and reset according to a power-on sequence; the mainboard is powered on to enter a BIOS setting interface, the mode of the ASM1061R is configured, and a proper configuration mode is selected. And after the RAID mode configuration is completed, saving the setting and restarting the mainboard, and enabling the setting to take effect. Thus, the utility model discloses the system disk of server mainboard builds RAID's design can realize.

The utility model discloses according to the configuration demand of difference, nimble configuration, at most support 10 standard PCIe trench, perhaps provide 16NVMe hard disk interface, perhaps support 4 full-width GPUs.

Specifically, fig. 4 is a schematic diagram illustrating a 10PCIe configuration connection structure. Two slim interfaces slim 1 and slim 2 of the CPU0 are connected to a Riser board having 2 pci ex8 slots by cables; the GenZ interface of CPU0 and the X16 Slot of CPU1 are connected to Riser boards of one PCIeX16 Slot and two PCIeX8 slots; two Slimline interfaces Slimline3 and Slimline4 of the CPU1 are connected to a Riser board with 2 PCIeX8 slots through cables; the GenZ interface of CPU1 and the X8Slot of CPU1 are connected to 3 Riser boards of PCIeX8 Slot.

Fig. 5 is a schematic view of a 16NVMe configuration connection structure. Each NVMe occupies the bandwidth of PCIe X4, and Slimline1 of the CPU0 is an interface of PCIe X8 and can connect 2 NVMe disks; slimline2 of the CPU0 is an interface of PCIe X8, and 2 NVMe disks can be connected; the GenZ interface of the CPU0 is an interface of PCIe X16, and 4 NVMe disks can be connected; slimline3 of the CPU1 is an interface of PCIe X8, and 2 NVMe disks can be connected; slimline4 of the CPU1 is an interface of PCIe X8, and 2 NVMe disks can be connected; the GenZ interface of the CPU1 is a PCIe X16 interface, and can connect 4 NVMe disks.

Fig. 6 is a schematic diagram of a connection structure of a 4GPU configuration. Each GPU occupies the bandwidth of PCIe X16, and two Slimline interfaces Slimline1 and Slimline2 of the CPU0 are connected to the GPU1 by cables; the GenZ interface of the CPU0 is connected to the GPU2 through a cable; two Slimline interfaces Slimline3 and Slimline4 of the CPU1 are connected to the GPU3 by cables; the GenZ interface of the CPU1 is connected to the GPU4 via a cable.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the scope of the present invention is not limited thereto. Various modifications and alterations will occur to those skilled in the art based on the foregoing description. And are neither required nor exhaustive of all embodiments. On the basis of the technical scheme of the utility model, various modifications or deformations that technical personnel in the field need not pay out creative work and can make still are within the protection scope of the utility model.

Claims

1. A server motherboard comprising a CPU0 and a CPU1, the CPU0 and the CPU1 being connected via a GMI interface;

2. The server motherboard of claim 1 wherein the RAID controller is an ASM 1061R.

3. The server motherboard of claim 2 wherein the PCIe interface of the RAID controller ASM1061R is connected to Port0 of CPU 0;

the clock interface of ASM1061R connects the crystal;

the serial peripheral interface of the ASM1061R is connected with Flash;

configuration pins of ASM1061R connect to the baseboard management controller.

4. The server motherboard of claim 1 wherein two Slimline interfaces of the CPU0 are connected to a Riser board having two PCIe x8 slots;

5. The server motherboard of claim 1 wherein each Slimline interface of the CPU0 and CPU1 is connected to 2 NVMe disks;

6. The server motherboard of claim 1 wherein two Slimline interfaces of the CPU0 are connected to the GPU 1; the GenZ interface of the CPU0 is connected with a GPU 2;

7. The server motherboard of claim 1 wherein the CPU0 is further connected to a baseboard management controller and a network controller, and is provided with a built-in Mezz card interface and an OCP3.0 interface.