CN107688376B - Hard disk backboard supporting self-adaptive hard disk interface - Google Patents
Hard disk backboard supporting self-adaptive hard disk interface Download PDFInfo
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Abstract
The invention provides a hard disk backboard supporting a self-adaptive hard disk interface, which comprises a hard disk interface, wherein the hard disk interface is connected with an SATA interface, a PCIE interface, a CPLD, a buffer module, an I2C expansion controlled module and a hard disk state I2C protocol conversion module; the I2C expansion controlled module is further connected with an I2C bus, the I2C bus is further connected with a first I2C interface and a temperature sensor, and the I2C bus is further connected with a hard disk state I2C protocol conversion module and a CPLD; the buffer module is also connected with the CPLD and the PCIE interface; the I2C expansion controlled module is also connected with the CPLD; the CPLD is also connected with a second I2C interface, an SGPIO interface, an error indicator light, an on-site indicator light and an active indicator light; the SATA interface is connected with a south bridge chip PCH, the PCIE interface is connected with a CPU, the first I2C interface is connected with a BMC, and the second I2C interface is connected with the CPU.
Description
Technical Field
The invention belongs to the field of hard disk backplanes, and particularly relates to a hard disk backplane supporting a self-adaptive hard disk interface.
Background
The current mainstream hard disks of the front hard disk of the server are SATA, SAS hard disks and SSD, but the NVME SSD hard disks are expensive and have limited popularity, hard disk back plates produced by various server manufacturers mainly support the SATA and SAS hard disks, along with the rapid development of the server industry, the NVME hard disks have lower delay, higher transmission performance and lower power consumption control and are continuously evolved from high end to mainstream, the demand is increased day by day, and under the condition of the increasing market of the NVME hard disks, the old back plates cannot meet the actual demand.
Therefore, it is very necessary to provide a hard disk backplane supporting an adaptive hard disk interface to overcome the above-mentioned drawbacks in the prior art.
Disclosure of Invention
The present invention provides a hard disk backplane supporting an adaptive hard disk interface to solve the above technical problem, aiming at the defect that the old hard disk backplane cannot meet the actual requirement.
In order to achieve the purpose, the invention provides the following technical scheme:
a hard disk backboard supporting a self-adaptive hard disk interface comprises a hard disk interface, wherein the hard disk interface is connected with an SATA interface, a PCIE interface, a CPLD, a buffer module, an I2C bus expansion controlled module and a hard disk state I2C protocol conversion module;
the I2C bus expansion controlled module is further connected with a first I2C bus, the first I2C bus is further connected with a first I2C interface and a temperature sensor, and the first I2C bus is further connected with a hard disk state I2C protocol conversion module and a CPLD;
the buffer module is also connected with the CPLD and the PCIE interface;
the I2C bus expansion controlled module is also connected with the CPLD;
the CPLD is also connected with a second I2C interface, an SGPIO interface, a hard disk error indicator light, a hard disk on-site indicator light and a hard disk activity indicator light;
the SATA interface is also connected with a south bridge chip PCH, the PCIE interface is also connected with a CPU, the first I2C interface is also connected with a BMC, and the second I2C interface is also connected with the CPU.
Further, the I2C bus extension controlled module comprises an I2C bus extension unit and an I2C bus controlled unit; the I2C bus expansion unit is connected with a first I2C bus, and the I2C bus controlled unit is connected with the I2C bus expansion unit, the hard disk interface and the CPLD.
Further, the hard disk interface comprises a hard disk in-place information port and a hard disk error information port, and the hard disk in-place information port and the hard disk error information port are both connected with the CPLD. The hard disk interface supports the hot plug function of the hard disk.
Furthermore, the power supply device also comprises an external power supply interface, wherein the external power supply interface is connected with a power supply conversion module, and the CPLD is connected with the power supply conversion module. The CPLD can also be connected with a hard disk power supply for supplying power, an external power supply interface can be connected with 5V or 12V, and the output voltage of the power supply conversion module is 3.3V.
Further, the quantity of hard disk interface is 4, and the quantity of SATA interface is 4, and the quantity of PCIE interface is 4, and the quantity of buffer module is 4, and the quantity of hard disk error indicator is 4, and the quantity of hard disk location pilot lamp is 4, and the quantity of hard disk activity pilot lamp is 4.
Further, the hard disk backplane comprises a first side, a second side, a third side, a fourth side, a front side and a back side;
the four hard disk interfaces are uniformly arranged on the fourth side of the front surface of the hard disk back plate and are parallel to the fourth side;
the first PCIE interface is arranged at the position, close to the first side and the second side, of the back of the hard disk backboard and is parallel to the second side, and the first SATA interface is arranged at the position, close to the first PCIE interface and the second side, of the back of the hard disk backboard and is parallel to the second side;
the third SATA interface is arranged at the center of the back of the hard disk backboard and is parallel to the second side;
the third PCIE interface is arranged at the position, close to the third SATA interface, of the back face of the hard disk backboard from the third side direction and is vertical to the second side;
the second PCIE interface is arranged at the position, close to the third SATA interface from the direction of the first side, on the back surface of the hard disk backboard and is vertical to the second side;
the second SATA interface is arranged in the middle of the first SATA interface and the third SATA interface and is vertical to the second side;
the fourth SATA interface is arranged on the back of the hard disk backboard and close to the third side and the second side and is parallel to the second side, and the fourth PCIE interface is arranged on the back of the hard disk backboard and close to the fourth SATA interface and the second side and is perpendicular to the second side.
Further, the hard disk interface adopts an SFF-8639 type hard disk connector, and the PCIE interface adopts an optical fiber copper cable connector OCUlink supporting a PCIE x4 signal.
Furthermore, the CPLD adopts a CPLD chip of LCMXO2-1200 model, and the hard disk state I2C protocol conversion module adopts a chip of TCA6408 model.
Further, an I2C bus extension unit adopts an I2C bus extension chip of PCA9546 model; the I2C bus controlled unit uses a chip of type 74LV 3162.
Further, the hard disk state I2C protocol conversion module and the CPLD are used to determine whether the hard disk interface has a hard disk insertion and an inserted hard disk type;
when it is determined that there is a hard disk inserted and the inserted hard disk type is an NVME hard disk,
the hard disk state I2C protocol conversion module informs a BMC that the type of the hard disk is an NVME hard disk, the BMC informs a CPU to be connected with a PCIE interface, and the CPU communicates with a CPLD through a second I2C interface to control an active indicator lamp of the NVME hard disk;
the CPLD controls the I2C bus expansion controlled module to be opened, and the BMC is communicated with the I2C of the hard disk interface to be opened;
the CPLD controls the buffer module to be opened, and the communication between the PCIE interface and the hard disk interface is opened;
the CPLD controls an error indicator lamp of the NVME hard disk and an in-place indicator lamp of the NVME hard disk;
when it is determined that a hard disk is inserted and the type of the inserted hard disk is an SAS or SATA hard disk,
the hard disk state I2C protocol conversion module informs the BMC that the type of the hard disk is an SAS or SATA hard disk, the BMC informs the PCH of being connected with an SATA interface, and the PCH communicates with the CPLD through an SGPIO interface to control an active indicator lamp of the SAS or SATA hard disk;
the CPLD controls an error indicator light of the SAS or SATA hard disk and an in-place indicator light of the SAS or SATAE hard disk.
The invention has the beneficial effects that:
the invention can meet the requirements of the system on different types of hard disks of NVME, SAS and SATA, realizes the lighting requirement of the server on the hard disks, and supports the error indicator lamp, the in-place indicator lamp and the movable indicator lamp of the hard disks.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
FIG. 1 is a schematic diagram of the connection of the present invention;
FIG. 2 is a schematic connection diagram according to an embodiment of the present invention;
FIG. 3 is a first schematic diagram of the front side structure of the present invention;
FIG. 4 is a second schematic view of the backside structure of the present invention;
1-a hard disk interface; 1.1-a first hard disk interface; 1.2-a second hard disk interface; 1.3-a third hard disk interface; 1.4-a fourth hard disk interface; 2-SATA interface; 2.1-first SATA interface; 2.2-a second SATA interface; 2.3-third SATA interface; 2.4-fourth SATA interface; 3-PCIE interface; 3.1-a first PCIE interface; 3.2-a second PCIE interface; 3.3-a third PCIE interface; 3.4-fourth PCIE interface; 4-CPLD; 5-a buffer module; 5.1-a first buffer module; 5.2-a second buffer module; 5.3-a third buffer module; 5.4-a fourth buffer module; 6-I2C expand controlled modules; 6.1-I2C bus expansion unit; 6.2.1-first I2C bus controlled Unit; 6.2.2-second I2C bus controlled Unit; 7-hard disk state I2C protocol conversion module; 8-first I2C interface; 9-a temperature sensor; 10-second I2C interface; 11-SGPIO interface; 12-hard disk error indicator light; 13-hard disk on-site indicator light; 14-hard disk activity indicator light; 15-PCH; 16-a CPU; 17-BMC; a.1-a first side of a hard disk backplane; a.2-a second side of the hard disk backboard; a.3-third side of hard disk backboard; a.4-hard disk backplane fourth side.
The specific implementation mode is as follows:
in order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the present embodiment.
As shown in fig. 1, the present invention provides a hard disk backplane supporting a self-adaptive hard disk interface, which includes a hard disk interface 1, where the hard disk interface is connected to a SATA interface 2, a PCIE interface 3, a CPLD 4, a buffer module 5, an I2C bus expansion controlled module 6, and a hard disk state I2C protocol conversion module 7;
the I2C bus expansion controlled module is further connected with a first I2C bus, the first I2C bus is further connected with a first I2C interface 8 and a temperature sensor 9, and the first I2C bus is further connected with a hard disk state I2C protocol conversion module 7 and a CPLD 4;
the buffer module 5 is also connected with the CPLD 4 and the PCIE interface 3;
the I2C bus expansion controlled module 6 is also connected with the CPLD 4;
the CPLD 4 is also connected with a second I2C interface 10, an SGPIO interface 11, a hard disk error indicator lamp 12, a hard disk on-site indicator lamp 13 and a hard disk activity indicator lamp 14;
the SATA interface 2 is further connected with a south bridge chip PCH 15, the PCIE interface 3 is further connected with a CPU 16, the first I2C interface 9 is further connected with a BMC 17, and the second I2C interface 10 is also connected with the CPU 16.
As shown in fig. 2, in the above embodiment, the number of the hard disk interfaces 1 is 4, the first hard disk interface 1.1, the second hard disk interface 1.2, the third hard disk interface 1.3 and the fourth hard disk interface 1.4, the number of the SATA interfaces 2 is 4, the first SATA interface 2.1, the second SATA interface 2.2, the third SATA interface 2.3 and the fourth SATA interface 2.4, the number of the PCIE interfaces 3 is 4, the first PCIE interface 3.1, the second PCIE interface 3.2, the third PCIE interface 3.3 and the fourth PCIE interface 3.4, the number of the buffer modules 4 is 4, the first buffer module 4.1, the second buffer module 4.2, the third buffer module 4.3 and the fourth buffer module 4.4; the I2C bus extension controlled module 6 comprises an I2C bus extension unit 6.1, a first I2C bus controlled unit 6.2.1 and a second I2C bus controlled unit 6.2.2;
the first hard disk interface 1.1 is connected with the first SATA interface 2.1, the first PCIE interface 3.1, the first buffer module 5.1, the first I2C bus controlled unit 6.2.1, the CPLD 4 and the hard disk state I2C protocol conversion module 7,
the first buffer module 5.1 is also connected with the CPLD 4 and the first PCIE interface 3.1;
the second hard disk interface 1.2 is connected with the second SATA interface 2.2, the second PCIE interface 3.2, the second buffer module 5.2, the first I2C bus controlled unit 6.2.1, the CPLD 4 and the hard disk state I2C protocol conversion module 7,
the second buffer module 5.2 is also connected with the CPLD 4 and the second PCIE interface 3.2;
the third hard disk interface 1.3 is connected with the third SATA interface 2.3, the third PCIE interface 3.3, the third buffer module 5.3, the second I2C bus controlled unit 6.2.2, the CPLD 4, and the hard disk state I2C protocol conversion module 7,
the third buffer module 5.3 is also connected with the CPLD 4 and the third PCIE interface 3.3;
the fourth hard disk interface 1.4 is connected with the fourth SATA interface 2.4, the fourth PCIE interface 3.4, the fourth buffer module 5.4, the second I2C bus controlled unit 6.2.2, the CPLD 4 and the hard disk state I2C protocol conversion module 7,
the fourth buffer module 5.4 is also connected with the CPLD 4 and the fourth PCIE interface 3.4;
the first I2C bus controlled unit 6.2.1 is connected with the I2C bus expansion unit 6.1 and the CPLD 4, the second I2C bus controlled unit 6.2.2 is connected with the I2C bus expansion unit 6.1 and the CPLD 4, and the I2C bus expansion unit 6.1 is connected with the first I2C bus;
the number of the hard disk error indicating lamps is also 4, the number of the hard disk positioning indicating lamps is 4, the number of the hard disk activity indicating lamps is 4, and each hard disk error indicating lamp, each hard disk positioning indicating lamp and each hard disk activity indicating lamp indicate the state of the corresponding hard disk;
the hard disk interface comprises a hard disk in-place information port and a hard disk error information port, and the hard disk in-place information port and the hard disk error information port are both connected with the CPLD;
the backboard further comprises an external power interface, the external power interface is connected with a power conversion module, and the CPLD is connected with the power conversion module. The CPLD can also be connected with a hard disk power supply for supplying power, an external power supply interface can be connected with 5V or 12V, and the output voltage of the power supply conversion module is 3.3V;
as shown in fig. 3 and 4, the hard disk backplane includes a first side a.1, a second side a.2, a third side a.3, a fourth side a.4, a front side, and a back side;
the first hard disk interface 1.1, the second hard disk interface 1.2, the third hard disk interface 1.3 and the fourth hard disk interface 1.4 are uniformly arranged on the fourth side A.4 of the front surface of the hard disk back plate and are parallel to the fourth side A.4;
the first PCIE interface 3.1 is arranged at the position close to the first side A.1 and the second side A.2 on the back of the hard disk backboard and is parallel to the second side A.2, and the first SATA interface 2.1 is arranged at the position close to the first PCIE interface 3.1 and the second side A.2 on the back of the hard disk backboard and is parallel to the second side A.2;
the third SATA interface 2.3 is arranged at the center of the back of the hard disk backboard and is parallel to the second side A.2;
the third PCIE interface 3.3 is disposed at a position on the back of the hard disk backplane, which is close to the third SATA interface 2.3 from the direction of the third side a.3, and is perpendicular to the second side a.2;
the second PCIE interface 3.2 is disposed at a position on the back of the hard disk backplane, which is close to the third SATA interface 2.3 from the direction of the first side a.1, and is perpendicular to the second side a.2;
the second SATA interface 2.2 is disposed at a position between the first SATA interface 2.1 and the third SATA interface 2.3, and is perpendicular to the second side a.2;
a fourth SATA interface 2.4 is disposed at a position close to the third side a.3 and the second side a.2 on the back of the hard disk backplane and is parallel to the second side a.2, and a fourth PCIE interface 3.4 is disposed at a position close to the fourth SATA interface 2.4 and the second side a.2 and is perpendicular to the second side a.2;
the first hard disk interface 1.1, the second hard disk interface 1.2, the third hard disk interface 1.3 and the fourth hard disk interface 1.4 all adopt hard disk connectors of SFF-8639 type, and the first PCIE interface 3.1, the second PCIE interface 3.2, the third PCIE interface 3.3 and the fourth PCIE interface 3.4 adopt optical fiber copper cable connectors OCUlink supporting PCIEX4 signals;
the CPLD adopts a CPLD chip with the model of LCMXO2-1200, and the hard disk state I2C protocol conversion module adopts a chip with the model of TCA 6408;
the I2C bus extension unit adopts an I2C bus extension chip of PCA9546 model; the first I2C bus controlled unit and the second I2C bus controlled unit adopt chips of 74LV3162 type.
The hard disk state I2C protocol conversion module and the CPLD are used for judging whether a hard disk is inserted into the hard disk interface or not and judging the type of the inserted hard disk;
when it is determined that there is a hard disk inserted and the inserted hard disk type is an NVME hard disk,
the hard disk state I2C protocol conversion module informs a BMC that the type of the hard disk is an NVME hard disk, the BMC informs a CPU to be connected with a PCIE interface, and the CPU communicates with a CPLD through a second I2C interface to control an active indicator lamp of the NVME hard disk;
the CPLD controls the I2C bus expansion controlled module to be opened, and the BMC is communicated with the I2C of the hard disk interface to be opened;
the CPLD controls the buffer module to be opened, and the communication between the PCIE interface and the hard disk interface is opened;
the CPLD controls an error indicator lamp of the NVME hard disk and an in-place indicator lamp of the NVME hard disk;
when it is determined that a hard disk is inserted and the type of the inserted hard disk is an SAS or SATA hard disk,
the hard disk state I2C protocol conversion module informs the BMC that the type of the hard disk is an SAS or SATA hard disk, the BMC informs the PCH of being connected with an SATA interface, and the PCH communicates with the CPLD through an SGPIO interface to control an active indicator lamp of the SAS or SATA hard disk;
the CPLD controls an error indicator light of the SAS or SATA hard disk and an in-place indicator light of the SAS or SATAE hard disk.
In the 2U server, 12 hard disk requirements are met through the combination of 3 back plates with the four hard disk interfaces, and different types of hard disks can be selected according to actual requirements.
The SATA interface, abbreviated as Serial ATA, is a computer bus and mainly used for data transmission between a motherboard and a mass storage device (e.g., a hard disk and an optical disk drive). ATA, AT attachment, embedded interface, ATA is also known as IDE interface.
OCuLink, Optical Copper Link, fiber/Copper cable Link.
CPLD, Complex Programmable Logic Device.
BMC, Basebard Management Controller, Baseboard Management Controller.
The embodiments of the present invention are illustrative rather than restrictive, and the above-mentioned embodiments are only provided to help understanding of the present invention, so that the present invention is not limited to the embodiments described in the detailed description, and other embodiments derived from the technical solutions of the present invention by those skilled in the art also belong to the protection scope of the present invention.
Claims (10)
1. A hard disk backboard supporting a self-adaptive hard disk interface is characterized by comprising a hard disk interface (1), wherein the hard disk interface is connected with a SATA interface (2), a PCIE interface (3), a CPLD (4), a buffer module (5), an I2C bus expansion controlled module (6) and a hard disk state I2C protocol conversion module (7);
the I2C bus expansion controlled module is further connected with a first I2C bus, the first I2C bus is further connected with a first I2C interface (8) and a temperature sensor (9), and the first I2C bus is further connected with a hard disk state I2C protocol conversion module (7) and a CPLD (4);
the buffer module (5) is also connected with the CPLD (4) and the PCIE interface (3);
the I2C bus expansion controlled module (6) is also connected with the CPLD (4);
the CPLD (4) is also connected with a second I2C interface (10), an SGPIO interface (11), a hard disk error indicator lamp (12), a hard disk in-place indicator lamp (13) and a hard disk activity indicator lamp (14);
the SATA interface (2) is also connected with a south bridge chip PCH (15), the PCIE interface (3) is also connected with a CPU (16), the first I2C interface (9) is also connected with a BMC (17), and the second I2C interface (10) is also connected with the CPU (16); the south bridge chip PCH (15) is also connected with the SGPIO interface (11);
the hard disk state I2C protocol conversion module and the CPLD are used for judging whether a hard disk is inserted into the hard disk interface or not and judging the type of the inserted hard disk;
when it is determined that there is a hard disk inserted and the inserted hard disk type is an NVME hard disk,
the hard disk state I2C protocol conversion module informs a BMC that the type of the hard disk is an NVME hard disk, the BMC informs a CPU to be connected with a PCIE interface, and the CPU communicates with a CPLD through a second I2C interface to control an active indicator lamp of the NVME hard disk;
when it is determined that a hard disk is inserted and the type of the inserted hard disk is an SAS or SATA hard disk,
the hard disk state I2C protocol conversion module informs the BMC that the hard disk is an SAS or SATA hard disk, the BMC informs the south bridge chip PCH to be connected with the SATA interface, and the south bridge chip PCH controls the active indicator light of the SAS or SATA hard disk through the communication between the SGPIO interface and the CPLD.
2. The hard disk backplane supporting the adaptive hard disk interface of claim 1, wherein the I2C bus extension controlled module comprises an I2C bus extension unit and an I2C bus controlled unit; the I2C bus expansion unit is connected with the first I2C bus and the CPLD, and the I2C bus controlled unit is connected with the I2C bus expansion unit, the hard disk interface and the CPLD.
3. The hard disk backplane supporting the adaptive hard disk interface of claim 1, wherein the hard disk interface comprises a hard disk on-site information port and a hard disk error information port, and both the hard disk on-site information port and the hard disk error information port are connected to the CPLD.
4. The hard disk backplane supporting the adaptive hard disk interface of claim 1, further comprising an external power interface, wherein the external power interface is connected with a power conversion module, and the CPLD is connected with the power conversion module.
5. The hard disk backplane supporting the adaptive hard disk interface of claim 1, wherein the number of hard disk interfaces is 4, the number of SATA interfaces is 4, the number of PCIE interfaces is 4, the number of buffer modules is 4, the number of hard disk error indicator lamps is 4, the number of hard disk positioning indicator lamps is 4, and the number of hard disk active indicator lamps is 4.
6. A hard disk backplane supporting an adaptive hard disk interface according to claim 5, characterized in that the hard disk backplane comprises a first side (A.1), a second side (A.2), a third side (A.3), a fourth side (A.4), a front side and a back side;
the four hard disk interfaces are uniformly arranged on the fourth side (A.4) of the front surface of the hard disk back plate and are parallel to the fourth side (A.4);
the first PCIE interface (3.1) is arranged at the position, close to the first side (A.1) and the second side (A.2), on the back of the hard disk backboard and is parallel to the second side (A.2), and the first SATA interface (2.1) is arranged at the position, close to the first PCIE interface (3.1) and the second side (A.2), on the back of the hard disk backboard and is parallel to the second side (A.2);
the third SATA interface (2.3) is arranged at the center of the back of the hard disk backboard and is parallel to the second side (A.2);
the third PCIE interface (3.3) is arranged at the position, close to the third SATA interface (2.3) from the direction of the third side (A.3), on the back of the hard disk backboard and is vertical to the second side (A.2);
the second PCIE interface (3.2) is arranged at the position, close to the third SATA interface (2.3) from the direction of the first side (A.1), on the back surface of the hard disk backboard and is vertical to the second side (A.2);
the second SATA interface (2.2) is arranged in the middle of the first SATA interface (2.1) and the third SATA interface (2.3) and is vertical to the second side (A.2);
the fourth SATA interface (2.4) is arranged at the position close to the third side (A.3) and the second side (A.2) on the back of the hard disk backboard and is parallel to the second side (A.2), and the fourth PCIE interface (3.4) is arranged at the position close to the fourth SATA interface (2.4) and the second side (A.2) and is vertical to the second side (A.2).
7. The hard disk backplane supporting the adaptive hard disk interface of claim 1, wherein the hard disk interface is an SFF-8639 hard disk connector, and the PCIE interface is an optical fiber copper cable connector OCUlink supporting a PCIE x4 signal.
8. The hard disk backplane supporting the adaptive hard disk interface of claim 1, wherein the CPLD is a CPLD chip of LCMXO2-1200 model, and the hard disk state I2C protocol conversion module is a chip of TCA6408 model.
9. The hard disk backplane supporting the adaptive hard disk interface as claimed in claim 2, wherein the I2C bus extension unit is an I2C bus extension chip of PCA9546 type; the I2C bus controlled unit uses a chip of type 74LV 3162.
10. The hard disk backplane supporting the adaptive hard disk interface of claim 5, wherein the hard disk state I2C protocol conversion module and the CPLD are used for judging whether the hard disk interface has a hard disk insertion and a hard disk type of the hard disk insertion;
when it is determined that there is a hard disk inserted and the inserted hard disk type is an NVME hard disk,
the hard disk state I2C protocol conversion module informs a BMC that the type of the hard disk is an NVME hard disk, the BMC informs a CPU to be connected with a PCIE interface, and the CPU communicates with a CPLD through a second I2C interface to control an active indicator lamp of the NVME hard disk;
the CPLD controls the I2C bus expansion controlled module to be opened, and the BMC is communicated with the I2C of the hard disk interface to be opened;
the CPLD controls the buffer module to be opened, and the communication between the PCIE interface and the hard disk interface is opened;
the CPLD controls an error indicator lamp of the NVME hard disk and an in-place indicator lamp of the NVME hard disk;
when it is determined that a hard disk is inserted and the type of the inserted hard disk is an SAS or SATA hard disk,
the hard disk state I2C protocol conversion module informs the BMC that the type of the hard disk is an SAS or SATA hard disk, the BMC informs a south bridge chip PCH to be connected with an SATA interface, and the south bridge chip PCH controls an active indicator lamp of the SAS or SATA hard disk through communication between an SGPIO interface and a CPLD;
the CPLD controls an error indicator light of the SAS or SATA hard disk and an in-place indicator light of the SAS or SATAE hard disk.
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| CN201710898201.1A CN107688376B (en) | 2017-09-28 | 2017-09-28 | Hard disk backboard supporting self-adaptive hard disk interface |
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