CN214256758U

CN214256758U - Electronic component, circuit board assembly and electronic equipment

Info

Publication number: CN214256758U
Application number: CN202121324659.4U
Authority: CN
Inventors: 曲林; 黄秋育
Original assignee: Honor Device Co Ltd
Current assignee: Shenzhen Glory Intelligent Machine Co ltd
Priority date: 2021-06-15
Filing date: 2021-06-15
Publication date: 2021-09-21
Anticipated expiration: 2031-06-15

Abstract

The application provides an electronic component, a circuit board assembly and an electronic device. This electronic component includes: the device comprises a device body and a plurality of pin terminals, wherein the device body is provided with a first surface, the plurality of pin terminals are arranged on the first surface and comprise a plurality of rows of pin terminals, the plurality of pin terminals of each row of pin terminals are used for realizing the same signal transmission, and the plurality of rows of pin terminals are arranged in a ring shape. In the electronic component that this application embodiment provided, can the excessive gluey region of gluing of accurate control underfill, can reduce the gluey quantity of underfill and the gluey area of coverage of underfill to reduce the thermal stress that the underfill was glued, avoid the influence to the solder joint because of the thermal stress that the underfill was glued to the solder joint to a certain extent at least, avoid the solder joint problem of inefficacy.

Description

Electronic component, circuit board assembly and electronic equipment

Technical Field

The application relates to the technical field of electronic equipment, in particular to an electronic component, a circuit board assembly and electronic equipment.

Background

With the gradual development of electronic devices, the design of solder joints between a chip on a circuit board and the circuit board tends to be more and more miniaturized, the mechanical stress resistance of the solder joints is poor, and in addition, the weight of the chip is heavy, the miniaturized solder joints cause the connection force between the circuit board and the chip to be small, and the addition of underfill between the circuit board and the chip to improve the connection force is a general solution. However, since the thermal expansion coefficient of the underfill is often large, the thermal stress generated by the thermal expansion of the underfill can easily cause the failure of the solder joint under the action of the thermal stress. On the basis, how to solve the problem of welding spot failure is an important direction for research of various manufacturers.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides an electronic component, a circuit board assembly and an electronic device, which are beneficial to solving the failure problem of welding spots.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect, some embodiments of the present application provide an electronic component, including: the device comprises a device body and a plurality of pin terminals, wherein the device body is provided with a first surface, the plurality of pin terminals are arranged on the first surface and comprise a plurality of rows of pin terminals, the plurality of pin terminals of each row of pin terminals are used for realizing the same signal transmission, and the plurality of rows of pin terminals are arranged in a ring shape.

In the electronic component provided by the embodiment of the application, because the plurality of pin terminals of each row of pin terminals are used for realizing the same signal transmission, and the plurality of rows of pin terminals are arranged in a ring shape, when the electronic component is installed on a circuit board, the corresponding pads, welding materials and the pin terminals can construct retaining walls. Like this, can the excessive gluey region of gluing of accurate control underfill, can reduce the gluey quantity of underfill and the area of coverage that the underfill glued to reduce the thermal stress that the underfill glued, avoid at least to a certain extent because of the thermal stress of underfill to the influence of solder joint, avoid the solder joint problem of inefficacy.

In some possible implementations of the first aspect, the area enclosed by the plurality of rows of pin terminals is located in a middle region of the first surface. The problems of pores and the like in the underfill positioned in the middle part can be avoided at least to a certain extent, and the problem of short circuit is solved.

In some possible implementations of the first aspect, the plurality of pin terminals further includes a first pin terminal and a second pin terminal that are adjacently disposed, the first pin terminal and the second pin terminal are located in an area surrounded by the plurality of rows of pin terminals, and a difference in operating voltage between the first pin terminal and the second pin terminal is greater than or equal to 1 v.

In some possible implementations of the first aspect, multiple rows of pin terminals are used to achieve the same signal transfer. Therefore, the closed-loop retaining wall is favorably arranged, and the blocking effect on the underfill is improved.

In some possible implementations of the first aspect, at least two adjacent rows of pin terminals are used to implement different signal transfers.

In a second aspect, some embodiments of the present application provide an electronic component, including: the device comprises a device body and a plurality of retaining walls, wherein the device body is provided with a first surface, and the first surface is provided with a pin terminal suitable for being welded with a circuit board; the retaining walls are arranged on the first surface and protrude out of the first surface, and the retaining walls are arranged in a ring shape.

In the electronic component that this application embodiment provided, because electronic component is including arranging into annular a plurality of barricades, when electronic component installed on the circuit board, can block the underfill after a plurality of barricades enclose the composition ring form, prevent that the underfill from entering into a plurality of barricades and enclose synthetic regional. Like this, can the excessive gluey region of gluing of accurate control underfill, can reduce the gluey quantity of underfill and the gluey area of coverage of underfill to reduce the thermal stress that the underfill glued, avoid the influence of the solder joint that thermal stress pair because of the underfill glues at least to a certain extent, avoid the inefficacy problem, and the setting of barricade can also improve first electronic components's structural strength, reduce first electronic components and parts deformation and stress risk.

In some possible implementations of the second aspect, the region surrounded by the plurality of retaining walls is located in a middle region of the first surface. The problems of pores and the like in the underfill positioned in the middle part can be avoided at least to a certain extent, and the problem of short circuit is solved.

In some possible implementations of the second aspect, the pin terminals are multiple, the multiple pin terminals include a first pin terminal and a second pin terminal that are adjacently disposed, the first pin terminal and the second pin terminal are located in an area surrounded by the multiple retaining walls, and an operating voltage difference between the first pin terminal and the second pin terminal is greater than or equal to 1 v. Therefore, the electronic component has high reliability in operation.

In some possible implementations of the second aspect, the retaining wall is located at an edge of the first surface. On the one hand, the purpose that the underfill is isolated outside the retaining wall and the underfill is surrounded and is arranged at the periphery of the device body to realize physical glue separation can be achieved, on the other hand, the packaging contact angle can be increased, the underfill is favorable for adhering to the peripheral wall of the retaining wall, the connection force between the circuit board body and the device body is improved, and the packaging effect is improved.

In some possible implementations of the second aspect, the retaining wall is metallic or non-metallic.

In some possible implementations of the second aspect, the plurality of retaining walls are arranged in a closed loop. This provides a good barrier to underfill.

In some possible implementations of the second aspect, at least two adjacent retaining walls are spaced apart.

In a third aspect, some embodiments of the present application provide a circuit board comprising: the circuit board comprises a circuit board body and a plurality of welding pads. The circuit board body is provided with a second surface, the plurality of bonding pads are arranged on the second surface and comprise a plurality of rows of bonding pads, the bonding pads of each row of bonding pads are used for realizing the same signal transmission, a connecting band is connected between any two adjacent bonding pads in each row of bonding pads, and the bonding pads of the plurality of rows are arranged in a ring shape.

In some circuit boards provided in the embodiments of the present application, since the plurality of pads of each row of pads are used for achieving the same signal transmission, a connection band is connected between any two adjacent pads of the plurality of pads of each row of pads, and the plurality of rows of pads are arranged in a ring shape, so that when the circuit board is mounted on an electronic component, the corresponding pads, the soldering material, and the pin terminals can construct a retaining wall. Like this, can the excessive gluey region of gluing of accurate control underfill, can reduce the gluey quantity of underfill and the area of coverage that the underfill glued to reduce the thermal stress that the underfill glued, avoid at least to a certain extent because of the thermal stress of underfill to the influence of solder joint, avoid the solder joint problem of inefficacy.

In some possible implementations of the third aspect, the plurality of pads further includes a first pad and a second pad that are adjacently disposed, the first pad and the second pad are located in a region surrounded by the plurality of rows of pads, and an operating voltage difference between the first pad and the second pad is greater than or equal to 1 v.

In some possible implementations of the third aspect, multiple rows of pads are used to implement the same signal transmission, and a connection band is connected between two adjacent rows of pads. Therefore, the closed-loop retaining wall is favorably arranged, and the blocking effect on the underfill is improved.

In some possible implementations of the third aspect, at least two adjacent rows of pads among the multiple rows of pads are used to implement different signal transmission, and the two adjacent rows of pads implementing different signal transmission are spaced apart.

In some possible implementations of the third aspect, any two adjacent rows of the multiple rows of pads are used to implement different signal transmission, and the two adjacent rows of pads are spaced apart.

In a fourth aspect, some embodiments of the present application provide a circuit board comprising: the circuit board body is provided with a second surface, and the second surface is provided with a welding disc suitable for being welded with the electronic component; the plurality of retaining walls are arranged on the second surface and are arranged in a ring shape.

In some circuit boards provided in the embodiments of the present application, since the circuit board includes a plurality of retaining walls arranged in a ring shape, the underfill can be blocked after the plurality of retaining walls are enclosed into a ring shape, so as to prevent the underfill from entering into an area enclosed by the plurality of retaining walls. Like this, can the excessive gluey region of gluing of accurate control underfill, can reduce the gluey quantity of underfill and the gluey area of coverage of underfill to reduce the gluey thermal stress of underfill, avoid at least to a certain extent because of the gluey thermal stress of underfill to the influence of solder joint, avoid the solder joint problem of becoming invalid, and the setting of barricade can also improve the structural strength of circuit board, reduce circuit board deformation and stress risk.

In some possible implementations of the fourth aspect, the number of the pads is multiple, the multiple pads include a first pad and a second pad that are adjacently disposed, the first pad and the second pad are located in an area surrounded by the multiple retaining walls, and an operating voltage difference between the first pad and the second pad is greater than or equal to 1 v.

In some possible implementations of the fourth aspect, the retaining wall is metallic or non-metallic.

In some possible implementations of the fourth aspect, the plurality of retaining walls are arranged in a closed loop. This is advantageous for improving the blocking effect of the underfill.

In some possible implementations of the fourth aspect, at least two adjacent retaining walls are spaced apart.

In a fifth aspect, some embodiments of the present application provide a circuit board assembly comprising: the electronic device comprises a first electronic component and a circuit board, wherein the first electronic component is the electronic component in any one of the technical schemes; the circuit board is the circuit board of any one of the above technical solutions, the second surface of the circuit board is opposite to the first surface of the first electronic component, and the multiple rows of pin terminals of the first electronic component are respectively welded with the multiple rows of pads of the circuit board.

Because the circuit board assembly provided by the embodiment of the application comprises the electronic component and the circuit board in the technical scheme, the electronic component and the circuit board can solve the same technical problem and achieve the same technical effect.

In a sixth aspect, some embodiments of the present application provide a circuit board assembly comprising: the electronic device comprises a first electronic component and a circuit board, wherein the first electronic component is the electronic component of any one of the technical schemes; the circuit board is provided with a second surface, the second surface is opposite to the first surface of the first electronic component, the second surface is provided with a bonding pad, the bonding pad is welded with the pin terminal of the first surface, and the plurality of retaining walls of the first electronic component are positioned between the first surface and the second surface.

Because the circuit board assembly provided by the embodiment of the application comprises the electronic components in the technical scheme, the circuit board assembly and the electronic components can solve the same technical problem and achieve the same technical effect.

In some possible implementations of the sixth aspect, a height dimension of the retaining wall in a direction perpendicular to the circuit board is h, a distance between the first surface and the second surface is d, and h and d satisfy: d-h is less than or equal to 50 microns.

In some possible implementations of the sixth aspect, the circuit board assembly further includes: the second electronic component is arranged on one side, away from the circuit board, of the first electronic component, the first electronic component is provided with a third surface facing the second electronic component, a bonding pad is arranged on the third surface, the second electronic component is provided with a fourth surface facing the first electronic component, a pin terminal is arranged on the fourth surface, the pin terminal on the fourth surface is welded on the bonding pad on the third surface, at least one of the third surface and the fourth surface is provided with a plurality of glue repelling portions, the glue repelling portions are located between the third surface and the fourth surface, and the glue repelling portions are arranged in a ring shape.

In some possible implementations of the sixth aspect, the glue repellants are located at edges of the third surface or the fourth surface.

In a seventh aspect, some embodiments of the present application provide a circuit board assembly comprising: the circuit board is the circuit board in any technical scheme, the second surface of the circuit board is opposite to the first surface of the first electronic component, a pad of the second surface is welded with the pin terminal of the first surface, and a plurality of retaining walls of the circuit board are located between the first surface and the second surface.

Because the circuit board assembly provided by the embodiment of the application comprises the circuit board in the technical scheme, the circuit board assembly and the circuit board can solve the same technical problem and achieve the same technical effect.

In some possible implementations of the seventh aspect, a height dimension of the retaining wall in a direction perpendicular to the circuit board is h, a distance between the first surface and the second surface is d, and h and d satisfy: d-h is less than or equal to 50 microns.

In some possible implementations of the seventh aspect, the region surrounded by the plurality of retaining walls is located in a middle region of the first surface of the first electronic component.

In some possible implementations of the seventh aspect, the dam is located at an edge of the first surface of the first electronic component. On the one hand, the purpose that the underfill is isolated outside the retaining wall and the underfill is surrounded and is arranged at the periphery of the device body to realize physical glue separation can be achieved, on the other hand, the packaging contact angle can be increased, the underfill is favorable for adhering to the peripheral wall of the retaining wall, the connection force between the circuit board body and the device body is improved, and the packaging effect is improved.

In some possible implementations of the seventh aspect, the circuit board assembly further includes: the second electronic component is arranged on one side, away from the circuit board, of the first electronic component, the first electronic component is provided with a third surface facing the second electronic component, a bonding pad is arranged on the third surface, the second electronic component is provided with a fourth surface facing the first electronic component, a pin terminal is arranged on the fourth surface, the pin terminal on the fourth surface is welded on the bonding pad on the third surface, at least one of the third surface and the fourth surface is provided with a plurality of glue repelling portions, the glue repelling portions are located between the third surface and the fourth surface, and the glue repelling portions are arranged in a ring shape.

In some possible implementations of the seventh aspect, the glue repelling portion is located at an edge of the third surface or the fourth surface.

In an eighth aspect, some embodiments of the present application provide an electronic device, comprising: a housing; the circuit board assembly is arranged in the shell.

Because the electronic equipment provided by the embodiment of the application comprises the circuit board assembly in any technical scheme, the electronic equipment and the circuit board assembly can solve the same technical problem and achieve the same technical effect.

Drawings

Fig. 1 is a perspective view of an electronic device provided by some embodiments of the present application;

FIG. 2 is an exploded view of the electronic device of FIG. 1;

fig. 3 is a schematic cross-sectional view of a circuit board assembly according to some embodiments of the present application;

FIG. 4 is a top view of a circuit board of the circuit board assembly of FIG. 3;

FIG. 5 is a cross-sectional schematic view of a circuit board assembly according to further embodiments of the present application;

fig. 6 is a top view of the circuit board assembly shown in fig. 5, with the first electronic component not shown in fig. 6;

fig. 7 is a bottom view of a first electronic component of the circuit board assembly shown in fig. 5;

FIG. 8 is a top view of a circuit board of the circuit board assembly shown in FIG. 5;

FIG. 9 is a schematic view of a single row of bond pads in some embodiments of the present application;

fig. 10 is a top view of a circuit board assembly in accordance with still further embodiments of the present application, with a first electronic component not shown in fig. 10;

FIG. 11 is a top view of a circuit board of the circuit board assembly shown in FIG. 10;

fig. 12 is a top view of a circuit board assembly in accordance with still other embodiments of the present application, with a first electronic component not shown in fig. 12;

FIG. 13 is a top view of a circuit board in the circuit board assembly shown in FIG. 12;

fig. 14 is a top view of a circuit board assembly in accordance with some other embodiments of the present application, with a first electronic component not shown in fig. 14;

FIG. 15 is a top view of a circuit board of the circuit board assembly shown in FIG. 14;

fig. 16 is a top view of a circuit board assembly in accordance with other embodiments of the present application, with the first electronic component not shown in fig. 16;

FIG. 17 is a top view of a circuit board in the circuit board assembly shown in FIG. 16;

FIG. 18 is a cross-sectional block diagram of a circuit board assembly according to still other embodiments of the present application;

fig. 19 is a top view of the circuit board assembly shown in fig. 18, with the first electronic component not shown in fig. 19;

FIG. 20 is a top view of a circuit board in the circuit board assembly shown in FIG. 19;

fig. 21 is a bottom view of a first electronic component in accordance with some embodiments of the present application;

FIG. 22 is a schematic view of a retaining wall according to some embodiments of the present application;

fig. 23 is a bottom view of a first electronic component in accordance with other embodiments of the present application;

fig. 24 is a top view of a circuit board assembly of an embodiment of the present application, with a first electronic component not shown in fig. 24;

FIG. 25 is a top view of a circuit board of the circuit board assembly shown in FIG. 24;

FIG. 26 is a cross-sectional block diagram of a circuit board assembly according to still other embodiments of the present application;

fig. 27 is a cross-sectional block diagram of a circuit board assembly according to still other embodiments of the present application.

Detailed Description

In the embodiments of the present application, the terms "first", "second", "third", and "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", "third", "fourth" may explicitly or implicitly include one or more of the features.

In the embodiments of the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The present application provides an electronic device, which is a type of electronic device having a circuit board assembly 30. Specifically, the electronic device according to the embodiments of the present application may be a mobile phone or a smart phone (e.g., an iPhone-based phone, an Android-based phone), a Portable game device (e.g., an nintendo DS, a PlayStation Portable, a game-oven advanced, an iPhone), a laptop, a Personal Digital Assistant (PDA), a Portable internet device, a music player, and a data storage device, other handheld devices, and devices such as a watch, an in-ear phone, a pendant, a headset, etc., and other wearable devices (e.g., electronic glasses, electronic clothes, an electronic bracelet, an electronic necklace, an electronic tattoo, a head-mounted device (HMD), etc.). Specifically, the electronic device may be a tablet computer, a mobile phone, a tablet navigator, an e-reader, a remote controller, a Personal Computer (PC), a notebook computer, a vehicle-mounted device, a network television, and the like. In the embodiments of the present application, the electronic device is a mobile phone as an example.

Referring to fig. 1 and fig. 2, fig. 1 is a perspective view of an electronic device according to some embodiments of the present disclosure, and fig. 2 is an exploded view of the electronic device shown in fig. 1. Specifically, the electronic apparatus includes a housing 10, a functional device 20, a battery 40, and a circuit board assembly 30. The case 10 serves to protect the functional device 20, the battery 40, and the circuit board assembly 30, among others.

Referring to fig. 1 and 2, the housing 10 is formed by splicing a front cover plate (not shown), a frame 11 and a rear cover 12. The materials of the front cover plate, the frame 11 and the back cover 12 include, but are not limited to, one or more of glass, metal and ceramic, and the materials of the front cover plate, the frame 11 and the back cover 12 may be the same or different, and are not specifically limited in the embodiments of the present application.

A functional device 20 is arranged in the housing 10, the functional device 20 being adapted to perform one or more functions of the electronic device. The functional device 20 includes, but is not limited to, a camera module, a display screen, a speaker, a receiver, an antenna, a microphone, a Universal Serial Bus (USB) interface, a Subscriber Identity Module (SIM) card interface, a button, and the like.

A battery 40 is disposed in the battery compartment of the housing 10, and the battery 40 is used for supplying electric power for the operation of the electronic device. The battery 40 may include, but is not limited to, a nickel-cadmium battery, a nickel-hydrogen battery, a lithium battery or other types of batteries including a battery core and a protection board, and the specific type of the battery 40 may be selected according to actual needs and is not particularly limited herein. Moreover, the number of the cells 40 in the embodiment of the present application may be multiple, or may be one, and the specific number and arrangement of the cells 40 in the embodiment of the present application may be set according to actual needs.

The circuit board assembly 30 is disposed in the housing 10, the circuit board assembly 30 is used for electrically connecting the plurality of functional devices 20, and the circuit board assembly 30 is used for performing operations such as signal control, data signal processing, and data signal storage on the functional devices 20. The circuit board assembly 30 may be a main board of the electronic device, and may also be other circuit boards of the electronic device, such as a circuit board for carrying a speaker (speaker) and a USB interface in a mobile phone, which is not limited in this respect. The circuit board assembly 30 is used as an example of a motherboard of an electronic device, which should not be construed as a specific limitation to the present application.

Referring to fig. 3, fig. 3 is a schematic cross-sectional structure diagram of a circuit board assembly 30 according to some embodiments of the present application. Specifically, the circuit board assembly 30 includes a first electronic component 31 and a circuit board 32.

The first electronic component 31 includes, but is not limited to, a chip, a resistor, a capacitor, an inductor, a potentiometer, a tube, a heat sink, an electromechanical element, a connector, a semiconductor discrete device, a sensor, a power supply, a switch, a micro-motor, an electronic transformer, a relay, and the like. It should be noted that, in the embodiment of the present application, the number and the arrangement manner of the first electronic components 31 may be set according to actual needs, and the number and the arrangement manner of the first electronic components 31 are not limited in the embodiment of the present application. A plurality of spaced apart pin terminals 312 are provided on the first electronic component 31.

Referring to fig. 4, fig. 4 is a top view of the circuit board 32 of the circuit board assembly 30 shown in fig. 3. The circuit board 32 includes, but is not limited to, a Printed Circuit Board (PCB) and a flexible circuit board (FPC). In the embodiment shown in fig. 3 and 4, the circuit board 32 is a PCB board. The shape of the circuit board 32 includes, but is not limited to, rectangular, square, polygonal, circular, etc., and in the embodiment shown in fig. 4, the shape of the circuit board 32 is rectangular.

The circuit board 32 is used for carrying the first electronic component 31 and is electrically connected with the first electronic component 31. Specifically, referring to fig. 4, a plurality of spaced apart pads 322 are disposed on the circuit board 32, and the plurality of pads 322 are used for soldering with the plurality of pin terminals 312. The shape of the bonding pad 322 includes, but is not limited to, rectangular, square, polygonal, circular, oval, or irregular, among others. In the embodiment shown in fig. 4, the pad 322 is circular in shape. The plurality of pads 322 may be arranged in an array. Of course, the plurality of pads 322 may also be irregularly arranged.

With continued reference to fig. 3 and 4, a solder material, such as solder paste, is disposed on the solder pads 322 of the circuit board 32, the pin terminals 312 of the first electronic component 31 are bonded to the solder pads 322 by the solder material, and the solder material is heated and melted, so that the solder pads 322, the pin terminals 312, and the solder material disposed between the solder pads 322 and the pin terminals 312 are fused into a whole, i.e., a solder joint. As the functions of the first electronic component 31 are gradually diversified, the performance of the first electronic component 31 is gradually improved, or the volume of the first electronic component 31 is miniaturized, the density of the pin terminals 312 on the first electronic component 31 is increased. On this basis, the volume of the individual pin terminals 312 is smaller and smaller, and the solder joint design tends to be more and more miniaturized. The miniaturized solder joint has a poor resistance to mechanical stress, resulting in a low connection force between the first electronic component 31 and the circuit board 32. In order to increase the connection force between the first electronic component 31 and the circuit board 32, in some embodiments, referring to fig. 3, an underfill 33 (underfill) is added between the first electronic component 31 and the circuit board 32. The underfill 33 may bond the first electronic component 31 and the circuit board 32 together to improve the connection force between the first electronic component 31 and the circuit board 32. However, since the Coefficient of Thermal Expansion (CTE) of the underfill 33 is generally large, when heat generated by the operation of the first electronic component 31 is transferred to the underfill 33, the underfill 33 is likely to thermally expand to enlarge the distance between the first electronic component 31 and the circuit board 32. Thereby causing the solder joint to fail under thermal stress.

In order to solve the problem of failure of a welding spot under the action of thermal stress, the application is improved as shown in the following embodiment:

specifically, referring to fig. 5 and fig. 6, fig. 5 is a schematic cross-sectional structure diagram of a circuit board assembly 30 according to another embodiment of the present application, fig. 6 is a top view of the circuit board assembly 30 shown in fig. 5, and the first electronic component 31 is not shown in fig. 6. In the present embodiment, the circuit board assembly 30 includes a first electronic component 31, a circuit board 32, and an underfill 33.

Referring to fig. 7, fig. 7 is a bottom view of the first electronic component 31 in the circuit board assembly 30 shown in fig. 5. In the embodiment shown in fig. 7, the first electronic component 31 includes: a device body 311 and a plurality of pin terminals 312. The device body 311 has a first surface 3111. The plurality of pin terminals 312 are disposed on the first surface 3111, and the plurality of pin terminals 312 are spaced apart. The first electronic component 31 is for mounting to the circuit board 32 via a plurality of pin terminals 312. Specifically, the plurality of pin terminals 312 are arranged in an array, and of course, the pin terminals 312 may also be arranged irregularly.

With continued reference to fig. 7, the plurality of pin terminals 312 includes a plurality of rows of pin terminals 312, and each row of pin terminals 312 has a plurality of pin terminals 312. Specifically, the number of pin terminals 312 in different rows of pin terminals 312 may be the same or different.

A plurality of pin terminals 312 per row of pin terminals 312 are used to achieve the same signal transfer. Specifically, different rows of pin terminals 312 may be used to implement the same signal transmission, and different rows of pin terminals 312 may also be used to implement different signal transmissions, or several rows of pin terminals 312 are used to implement the same signal transmission, and the remaining several rows of pin terminals 312 are used to implement different signal transmissions, as long as the same row of pin terminals 312 is ensured to be used to transmit the same signal.

With continued reference to fig. 7, the plurality of pin terminals 312 in each row of pin terminals 312 are arranged in a row, and the plurality of rows of pin terminals 312 are arranged in a ring. The rings in which the rows of pin terminals 312 are arranged may be square rings, circular rings, elliptical rings, or profiled rings.

Illustratively, in the embodiment shown in fig. 7, the plurality of pin terminals 312 are divided into three types, wherein one type of pin terminals 312 constitutes a plurality of rows of pin terminals 312, and is four rows, the four rows of pin terminals 312 are arranged in a square ring, and the number of pin terminals 312 in any two rows of pin terminals 312 is different, another type of pin terminal 312 is located outside the square ring in which the four rows of pin terminals 312 are arranged, and the last type of pin terminal 312 is located inside the square ring in which the four rows of pin terminals 312 are arranged.

It is understood that, on the basis that one of the pin terminals 312 is provided in the device body 311, the other two pin terminals 312 may be selected according to actual needs.

Referring to fig. 8, fig. 8 is a top view of the circuit board 32 in the circuit board assembly 30 shown in fig. 5. In the embodiment shown in fig. 8, the circuit board 32 includes a circuit board body 321, the circuit board body 321 has a second surface 3211, the second surface 3211 is opposite to the first surface 3111 of the first electronic component 31, the second surface 3211 is provided with a plurality of pads 322, and the plurality of pads 322 are spaced apart from each other. Specifically, the shape of the bonding pad 322 includes, but is not limited to, a rectangle, a square, a polygon, a circle, an ellipse, or a special shape, and the like, and in the embodiment shown in fig. 4, the bonding pad 322 is rectangular. The plurality of pads 322 may be arranged in an array, and of course, the plurality of pads 322 may also be arranged irregularly.

With continued reference to fig. 8, the plurality of pads 322 includes a plurality of rows of pads 322, each row of pads 322 having a plurality of pads 322. Specifically, the number of pads 322 in different rows of pads 322 may be the same or different. Multiple pads 322 in each row of pads 322 are used to achieve the same signal transfer. Specifically, the pads 322 in different rows are used for achieving the same signal transmission, and the pads 322 in different rows may also be used for achieving different signal transmission, or several rows of pads 322 are used for achieving the same signal transmission, and the rest rows of pads 322 are used for achieving different signal transmission, as long as it is ensured that the same row of pads 322 is used for achieving the same signal transmission.

Referring to fig. 9, fig. 9 is a diagram illustrating a single row of pads 322 according to some embodiments of the present disclosure. In the embodiment shown in fig. 9, a connection tape 323 is connected between any adjacent two pads 322 of the plurality of pads 322 of each row of pads 322.

Specifically, a portion of the second surface 3211 of the circuit board 32 is not covered with green oil, and a plurality of spaced-apart pads 322 in each row of pads 322 and a connection tape 323 connecting between the two pads 322 are implemented by exposing copper on the circuit board 32 according to a designed link.

Each row of pads 322 is arranged in a row and the rows of pads 322 are arranged in a ring. The ring in which the rows of pads 322 are arranged may be a square ring, a circular ring, an elliptical ring, or a profiled ring.

Illustratively, in the embodiment shown in fig. 8, the pads 322 are divided into three types, wherein one type of pad 322 forms a plurality of rows of pads 322 and is four rows, the four rows of pads 322 are arranged in a square ring, the number of pads 322 of any two rows of pads 322 is different, another type of pad 322 is located outside the square ring formed by the four rows of pads 322, and the last type of pad 322 is located inside the square ring formed by the four rows of pads 322.

It can be understood that, on the basis of the circuit board body 321 provided with one of the pads 322, the other two pads 322 may be selected to be provided or not according to actual needs.

Referring again to fig. 5, the rows of pads 322 are soldered to the rows of pin terminals 312. Specifically, the multiple rows of pads 322 correspond to the multiple rows of pin terminals 312 one to one, the corresponding pads 322 and the pin terminals 312 are used for realizing the same signal transmission, and the corresponding pads 322 are welded to the pin terminals 312.

Specifically, the number of the pin terminals 312 and the number of the pads 322 may be the same, and the plurality of pin terminals 312 and the plurality of pads 322 are soldered in a one-to-one correspondence. The number of the pin terminals 312 and the number of the pads 322 may also be different, one pin terminal 312 is welded with a plurality of pads 322, and the number of the pads 322 corresponding to different pin terminals 312 may be the same or different; a plurality of pin terminals 312 may be soldered to one solder pad 322, and the number of the pin terminals 312 soldered to different solder pads 322 may be the same or different.

Specifically, during the assembly of the circuit board assembly 30, a soldering material such as solder paste is provided on the pads 322 and the connection tape 323. The plurality of pin terminals 312 may be respectively bonded to the corresponding pads 322 by a soldering material such that the pin terminals 312 press a portion of the soldering material, and among the corresponding pads 322 and pin terminals 312, a portion of the soldering material located between the pin terminals 312 and the pads 322 is pressed to a connection band 323 connected to the pads 322 and fills a gap between the connection band 323 and the device body 311. After the welding material is heated and melted, the multiple rows of pads 322, the connection strips 323, the multiple rows of pin terminals 312 corresponding to the multiple rows of pads 322 one by one, and the welding material disposed between the multiple rows of pads 322 and the multiple rows of pin terminals 312 are fused into a whole, so as to form multiple retaining walls 34 arranged in a ring shape. In this way, compared to a scheme in which the connection tape 323 is not provided and the soldering material is only provided between the pads 322 and the pin terminals 312 to form solder joints, the provision of the connection tape 323 not only can enhance the structural strength of the pads 322, but also can facilitate the provision of the soldering material between the connection tape 323 and the first electronic component 31 for soldering, so that the structural strength of the solder joints is higher, and since the same row of pads 322 is used to achieve the same signal transmission, even if the connection tape 323 connects two adjacent pads 322 in the row of pads 322, the function of the circuit board assembly 30 is not affected.

In addition, since the plurality of retaining walls 34 are located between the device body 311 and the circuit board body 321, the region enclosed by the plurality of retaining walls 34 is located between the device body 311 and the circuit board body 321. Then, when the underfill 33 is filled between the device body 311 and the circuit board body 321, the underfill 33 may not enter the region surrounded by the plurality of retaining walls 34 under the blocking action of the plurality of retaining walls 34, but be located between the device body 311 and the circuit board body 321 and surround the periphery of the ring defined by the plurality of retaining walls 34. Like this, through device 3D packaging structure, and need not increase device overall arrangement interval, just can play the effect that blocks glue, can the excessive gluey region of accurate control underfill 33, reduce the quantity of underfill 33 and the coverage area of underfill 33 to reduce underfill 33's thermal stress, avoid underfill 33's thermal stress to the solder joint to a certain extent at least, avoid the inefficacy problem of solder joint.

In the first electronic component 31 provided in the embodiment of the present application, since the plurality of pin terminals 312 of each row of pin terminals 312 are used for achieving the same signal transmission, the plurality of rows of pin terminals 312 are arranged in a ring shape, so that when the first electronic component 31 is mounted on the circuit board 32, the corresponding pads 322, solder material and the pin terminals 312 form the retaining walls 34. Then, when the underfill 33 is filled between the first electronic component 31 and the circuit board 32, the underfill 33 is not filled into the region surrounded by the plurality of retaining walls 34 under the blocking action of the plurality of retaining walls 34, but is located between the device body 311 and the circuit board body 321 and surrounds the periphery of the ring defined by the plurality of retaining walls 34. Thus, the glue overflow area of the underfill 33 can be accurately controlled, the amount of the underfill 33 and the coverage area of the underfill 33 can be reduced, thereby reducing the thermal stress of the underfill 33, avoiding the influence of the thermal stress of the underfill 33 on the solder joints at least to a certain extent, and avoiding the problem of solder joint failure.

In the circuit board 32 provided in the embodiment of the present application, since the plurality of pads 322 of each row of pads 322 are used for achieving the same signal transmission, the connection strip 323 is connected between any two adjacent pads 322 of the plurality of pads 322 of each row of pads 322, and the plurality of rows of pads 322 are arranged in a ring shape, so that when the circuit board 32 is mounted on the first electronic component 31, the corresponding pads 322, the soldering material, and the pin terminals 312 form the retaining walls 34. Then, when the underfill 33 is filled between the first electronic component 31 and the circuit board 32, the underfill 33 is not filled into the region surrounded by the plurality of retaining walls 34 under the blocking action of the plurality of retaining walls 34, but is located between the device body 311 and the circuit board body 321 and surrounds the periphery of the ring defined by the plurality of retaining walls 34. Thus, the glue overflow area of the underfill 33 can be accurately controlled, the amount of the underfill 33 and the coverage area of the underfill 33 can be reduced, thereby reducing the thermal stress of the underfill 33, avoiding the influence of the thermal stress of the underfill 33 on the solder joints at least to a certain extent, and avoiding the problem of solder joint failure.

In the circuit board assembly 30 provided in the embodiment of the present application, since the plurality of pin terminals 312 of each row of pin terminals 312 are used for achieving the same signal transmission, the plurality of pin terminals 312 of each row of pin terminals 312 are arranged in a row, the plurality of rows of pin terminals 312 are arranged in a ring shape, since the plurality of pads 322 of each row of pads 322 are used for achieving the same signal transmission, the plurality of pads 322 of each row of pads 322 are arranged in a row, a connection strip 323 is connected between any two adjacent pads 322 of the plurality of pads 322 of each row of pads 322, the plurality of rows of pads 322 are arranged in a ring shape, the plurality of rows of pads 322 correspond to the plurality of rows of pin terminals 312 one to one, the corresponding pads 322 and the pin terminals 312 are welded by a welding material, each corresponding pad 322, welding material and pin terminal 312 form a plurality of retaining walls 34 arranged in a ring shape, when the underfill 33 is filled between the first electronic component 31 and the circuit board 32, the underfill 33 may be located between the device body 311 and the circuit board body 321 and around the periphery of the ring defined by the plurality of retaining walls 34, without entering the region surrounded by the plurality of retaining walls 34 under the blocking action of the plurality of retaining walls 34. Thus, the glue overflow area of the underfill 33 can be precisely controlled, the amount of the underfill 33 and the coverage area of the underfill 33 can be reduced, the thermal stress of the underfill 33 is reduced, and the influence of the thermal stress of the underfill 33 on the solder joint between the pin terminal 312 and the pad 322 is avoided at least to some extent, thereby avoiding the failure problem.

Since the underfill 33 flows in the direction from the outer periphery of the first electronic component 31 to the center of the first electronic component 31, voids and the like are likely to exist in the underfill 33 in the middle of the first electronic component 31, which causes dendrites to be generated, and thus the operating voltage difference between two adjacent pin terminals 312 at the position is large, which is likely to cause short circuit. In some embodiments, by positioning the region surrounded by the rows of pin terminals 312 in the middle region of the first surface 3111, when the first electronic component 31 is mounted on the circuit board 32, the region surrounded by the plurality of annularly arranged retaining walls 34 formed by the corresponding pads 322, the soldering material and the pin terminals 312 can be positioned in the middle region of the first surface 3111, and the underfill 33 can be prevented from entering the region surrounded by the plurality of retaining walls 34 by the blocking action of the plurality of retaining walls 34, but can be positioned around the periphery of the ring defined by the plurality of retaining walls 34, so that the problems of voids and the like in the underfill 33 positioned in the middle region can be avoided at least to some extent, and the short circuit problem can be solved.

It should be noted that "middle" is to be understood in a broad sense, that the area enclosed by the plurality of retaining walls 34 is located in the middle area of the first surface 3111 means that the area enclosed by the plurality of retaining walls 34 is offset from the peripheral edge of the first surface 3111, specifically, the center of the area enclosed by the plurality of retaining walls 34 is offset from the center of the first surface 3111 by a distance smaller than a predetermined value (4 mm, 3mm, 2mm, 1mm, 0.5mm, 0.3mm or 0.25 mm), for example, the center of the area enclosed by the plurality of retaining walls 34 coincides with the center of the first surface 3111.

In some embodiments, referring to fig. 6 and 7, at least two of the pin terminals 312 are located in a region surrounded by the rows of pin terminals 312, specifically, the plurality of pin terminals 312 further includes a first pin terminal 312a and a second pin terminal 312b disposed adjacently, the first pin terminal 312a and the second pin terminal 312b are located in the region surrounded by the rows of pin terminals 312, and an operating voltage difference between the first pin terminal 312a and the second pin terminal 312b is greater than or equal to 1v (e.g., 1.5v, 2v, 3v, 4v, or 5 v), correspondingly, at least two of the pads 322 are located in the region surrounded by the rows of pads 322, specifically, the plurality of pads 322 further includes a first pad 322a and a second pad 322b, the first pad 322a and the second pad 322b are located in the region surrounded by the rows of pads 322, and the operating voltage difference between the first pad 322a and the second pad 322b is greater than or equal to the operating voltage 1v (e.g., 1.5v, 2v, 3v, 4v or 5 v).

That is, the first and second pin terminals 312a and 312b and the first and second pads 322a and 322b corresponding to the first and second pin terminals 312a and 312b are located in the region surrounded by the plurality of retaining walls 34, the operating voltage difference between the first and second pin terminals 312a and 312b is greater than or equal to 1v, and the operating voltage difference between the first and second pads 322a and 322b is greater than or equal to 1 v. For the circuit board assembly 30, the region surrounded by the plurality of retaining walls 34 arranged in a ring shape and constructed by the corresponding pads 322, the soldering material and the pin terminals 312 is located in the middle region of the first surface 3111, and the underfill 33 may not enter the region surrounded by the plurality of retaining walls 34 under the blocking action of the plurality of retaining walls 34, but may be located around the periphery of the ring defined by the plurality of retaining walls 34, so as to avoid the problems of voids and the like in the underfill 33 at the middle position of the first electronic component 31 at least to some extent, and solve the short circuit problem that the working voltage difference is large in the region surrounded by the plurality of retaining walls 34 and two adjacent pin terminals 312/pads 322 are short-circuited.

Referring to fig. 10 and 11, fig. 10 is a top view of a circuit board assembly 30 according to still other embodiments of the present application, in which the first electronic component 31 is not shown in fig. 10, and fig. 11 is a top view of a circuit board 32 in the circuit board assembly 30 shown in fig. 10. The multiple rows of pads 322 are used for realizing the same signal transmission, the connection band 323 is connected between the two adjacent rows of pads 322, correspondingly, in the first electronic component 31, the multiple rows of pin terminals 312 are used for realizing the same signal transmission, so that in the circuit board assembly 30, in addition to the welding material formed between the opposite multiple rows of pads 322 and the multiple rows of pin terminals 312, the welding material may be disposed on the connection band 323 between the two adjacent rows of pads 322 to fill the gap between the connection band 323 and the device body 311, so as to connect the multiple retaining walls 34 into a closed loop after the welding material is fused, thereby further improving the blocking effect of the retaining walls 34 on the underfill 33.

In some embodiments, with continued reference to fig. 10 and 11, multiple rows of pads 322 are used to achieve the same signal transmission, and in each two adjacent rows of pads 322, a connection band 323 is connected between the end pad 322 of one row of pads 322 and the end pad 322 of the other row of pads 322, so that in the circuit board assembly 30, in addition to the welding material formed between the opposite rows of pads 322 and the multiple rows of pin terminals 312, a welding material may be disposed on the connection band 323 between the two adjacent rows of pads 322 to fill the gap between the connection band 323 and the device body 311, so as to connect the multiple retaining walls 34 into a closed loop after the welding material is fused, thereby further improving the blocking effect of the retaining walls 34 on the underfill 33.

In some embodiments, please refer to fig. 14, fig. 14 is a top view of a circuit board assembly 30 according to some other embodiments of the present application, in which the first electronic component 31 is not shown in fig. 14; fig. 15 is a top view of circuit board 32 in circuit board assembly 30 of fig. 14. In the embodiment shown in fig. 14, a plurality of rows of pads 322 are used to realize the same signal transmission, and in each two adjacent rows of pads 322, a connection band 323 is connected between the pads 322 at the end of one row of pads 322 and the pads 322 at the non-end of the other row of pads 322, so that, in the two adjacent rows of pads 322, the other row of pads 322 extends beyond the one row of pads 322 along the length direction of the row of pads 322, so that, in the circuit board assembly 30, in addition to the soldering material formed between the opposing rows of pads 322 and the rows of pin terminals 312, the soldering material may be provided on the connection band 323 between the two adjacent rows of pads 322 to fill the gap between the connection band 323 and the device body 311, so as to connect a plurality of retaining walls 34 into a closed loop shape with a partially protruded outer periphery after the soldering material is fused, and in the process of providing the underfill 33, the glue dispensing separation in the glue area is facilitated.

Alternatively, as shown in FIG. 11, four rows of pads 322 are arranged in a closed square ring. With continued reference to fig. 10, the four retaining walls 34 corresponding to the four rows of pads 322 are arranged in a closed square ring. Of course, the present application is not limited thereto, please refer to fig. 12 and 13, in which fig. 12 is a top view of a circuit board assembly 30 according to still other embodiments of the present application, and the first electronic component 31 is not shown in fig. 12; fig. 13 is a top view of the circuit board 32 in the circuit board assembly 30 shown in fig. 12. In the embodiment shown in fig. 13, eight rows of pads 322 are arranged in a closed eight sided ring. In fig. 12, eight retaining walls 34 corresponding to eight rows of pads 322 are arranged in a closed eight-sided ring shape.

Referring to fig. 6 and 8 again, at least two adjacent rows of pin terminals 312 are used for implementing different signal transmission, correspondingly, at least two adjacent rows of pads 322 are used for implementing different signal transmission, and the two adjacent rows of pads 322 implementing different signal transmission are spaced apart, that is, the two adjacent rows of pads 322 implementing different signal transmission are not connected by the above-mentioned connecting band 323, so that in the circuit board assembly 30, two retaining walls 34 corresponding to the two adjacent rows of pads 322 implementing different signal transmission are spaced apart, so that an electrical connection relationship is not generated between the two retaining walls 34, and the reliability of the operation of the circuit board assembly 30 is ensured.

Specifically, as shown in fig. 6, any two adjacent rows of pin terminals 312 are used for implementing different signal transmission, and correspondingly, among the multiple rows of pads 322, any two adjacent rows of pads 322 are used for implementing different signal transmission, and the two adjacent rows of pads 322 implementing different signal transmission are spaced apart, that is, the two adjacent rows of pads 322 implementing different signal transmission are not connected by a connection tape 323, so that in the circuit board assembly 30, two retaining walls 34 corresponding to the two adjacent rows of pads 322 implementing different signal transmission are spaced apart, so that an electrical connection relationship between the two retaining walls 34 is not generated, and the reliability of the operation of the circuit board assembly 30 is ensured.

With continued reference to fig. 6, in the multiple rows of pads 322, any two adjacent rows of pads 322 are used to implement different signal transmission, and the two adjacent rows of pads 322 implementing different signal transmission are spaced apart and perpendicular, and the end pads 322 of the two adjacent rows of pads 322 are aligned.

Please refer to fig. 16 and 17. Fig. 16 is a top view of circuit board assembly 30 in other embodiments of the present application, with first electronic component 31 not shown in fig. 16, and fig. 17 is a top view of circuit board 32 in circuit board assembly 30 shown in fig. 16. Any two adjacent rows of pin terminals 312 are used for realizing different signal transmission, in the multiple rows of pads 322, any two adjacent rows of pads 322 are used for realizing different signal transmission, and the two adjacent rows of pads 322 for realizing different signal transmission are spaced apart, and in the two adjacent rows of pads 322, one row of pads 322 exceeds the other row of pads 322 along the length direction of the row of pads 322 to extend, so that in the process of arranging the underfill adhesive 33, the glue area dispensing separation is facilitated.

In some embodiments, the first electronic component 31 is an Integrated Circuit (IC), and particularly, the first electronic component 31 includes, but is not limited to, an Application Processor (AP), a Double Data Rate (DDR), and a universal flash memory (UFS). The first electronic component 31 may be packaged in a Wafer Level Package (WLP) manner or a non-wafer level package. Wafer level packages include, but are not limited to, Fan-in wafer level chip scale packages (Fn-in WLCSP) and Fan-out WLCSP. Non-wafer level packages include, but are not limited to, a flip-chip scale package (Fan-out WLCSP), a flip-chip ball grid array (FCBGA) package, and a wire-bonded ball grid array (WBBGA) package, and are not particularly limited herein.

Please refer to fig. 18 and 19. Fig. 18 is a cross-sectional structural view of a circuit board assembly 30 according to still other embodiments of the present application, and fig. 19 is a top view of the circuit board assembly 30 shown in fig. 18, in which the first electronic component 31 is not shown in fig. 19. Specifically, the circuit board assembly 30 includes a first electronic component 31, a circuit board 32, and an underfill 33.

The circuit board 32 includes, but is not limited to, a PCB board and an FPC board. In some embodiments, the circuit board 32 is a PCB, and in particular, the circuit board 32 includes a multilayer wiring structure formed by sequentially and alternately stacking metal layers and insulating dielectric layers. In some embodiments, the circuit board 32 further includes a solder resist layer disposed on the surface of the multilayer wiring structure.

Referring to fig. 20 and 21, fig. 20 is a top view of the circuit board 32 in the circuit board assembly 30 shown in fig. 19, and fig. 21 is a bottom view of the first electronic component 31 according to some embodiments of the present application. In the embodiment shown in fig. 21, the first electronic component 31 includes a component body 311, the component body 311 has a first surface 3111, the first surface 3111 is provided with a plurality of pin terminals 312 adapted to be soldered to the circuit board 32, and the plurality of pin terminals 312 are spaced apart. Specifically, the plurality of pin terminals 312 are arranged in an array, and of course, the plurality of pin terminals 312 may also be arranged irregularly.

In the embodiment shown in fig. 20, the circuit board 32 includes a circuit board body 321, the circuit board body 321 has a second surface 3211, the second surface 3211 is opposite to the first surface 3111 of the first electronic component 31, the second surface 3211 is provided with a plurality of pads 322 adapted to be soldered to the pin terminals 312 of the first electronic component 31, and the pads 322 are spaced apart from each other. Specifically, the plurality of pads 322 are arranged in an array, and of course, the plurality of pads 322 may also be arranged irregularly.

Referring to fig. 20 and 21, at least one of the circuit board 32 and the first electronic component 31 further includes a plurality of retaining walls 34. That is, the circuit board 32 includes a plurality of retaining walls 34, and the first electronic component 31 does not include a plurality of retaining walls 34; the circuit board 32 does not include the plurality of retaining walls 34, and the first electronic component 31 includes the plurality of retaining walls 34; alternatively, the circuit board 32 and the first electronic component 31 each include a plurality of retaining walls 34, and the plurality of retaining walls 34 of the circuit board 32 and the plurality of retaining walls 34 of the first electronic component 31 are connected in a one-to-one correspondence. When the first electronic component 31 includes a plurality of retaining walls 34, the retaining walls 34 are disposed on the first surface 3111, and the retaining walls 34 protrude from the first surface 3111, the retaining walls 34 are spaced apart from the pin terminals 312, and the retaining walls 34 on the device body 311 are arranged in a ring shape; when the circuit board 32 includes a plurality of retaining walls 34, the retaining walls 34 are disposed on the second surface, and the retaining walls 34 protrude from the second surface 3211, for example, the retaining walls 34 protrude from an end of the pad 322 on the second surface, which is far from the second surface 3211, the retaining walls 34 are arranged in a ring shape, and the retaining walls 34 are spaced apart from the pad 322.

Specifically, the plurality of pads 322 may be located within a ring defined by the plurality of retaining walls 34, the plurality of pads 322 may also be located at an outer periphery of the ring defined by the plurality of retaining walls 34, or the plurality of pads 322 may be disposed at the outer periphery of the ring defined by the plurality of retaining walls 34 and within the ring defined by the plurality of retaining walls 34.

Specifically, the plurality of pin terminals 312 may be located in the ring defined by the plurality of retaining walls 34, the plurality of pin terminals 312 may also be located at the outer periphery of the ring defined by the plurality of retaining walls 34, or the plurality of pin terminals 312 are disposed at the outer periphery of the ring defined by the plurality of retaining walls 34 and the ring defined by the plurality of retaining walls 34.

The shape of the retaining wall 34 includes, but is not limited to, a long shape, a folded line shape, and a curved line shape, and the plurality of retaining walls 34 may be the same or different. Referring to fig. 22, fig. 22 is a schematic view of a retaining wall 34 according to some embodiments of the present application. The retaining wall 34 is formed in an elongated shape, and the cross section of the retaining wall 34 is square.

Specifically, during the mounting process of the circuit board assembly 30, the area enclosed by the plurality of retaining walls 34 is located between the first surface 3111 and the second surface 3211, so that when the underfill 33 is used to increase the connection force between the first electronic component 31 and the circuit board 32, the underfill 33 can surround the outer periphery of the ring defined by the plurality of retaining walls 34 without entering the area enclosed by the plurality of retaining walls 34 under the blocking effect of the plurality of retaining walls 34. Thus, the amount of the underfill 33 and the coverage area of the underfill 33 can be reduced, thereby reducing the thermal stress of the underfill 33, avoiding the influence on the solder joints due to the thermal stress of the underfill 33 at least to a certain extent, and avoiding the problem of solder joint failure.

In the first electronic component 31 provided in the embodiment of the present application, since the first electronic component 31 includes the plurality of retaining walls 34 arranged in a ring shape, when the first electronic component 31 is mounted on the circuit board 32, the plurality of retaining walls 34 can block the underfill 33 after being surrounded into a ring shape, so as to prevent the underfill 33 from entering the region surrounded by the plurality of retaining walls 34. Like this, can the excessive gluey region of accurate control underfill 33, can reduce underfill 33's quantity and underfill 33's area of coverage to reduce underfill 33's thermal stress, avoid the influence of the solder joint because of underfill 33's thermal stress to at least to a certain extent, avoid the inefficacy problem, and the setting of barricade 34 can also improve first electronic components 31's structural strength, reduce first electronic components 31 deformation and stress risk.

In the circuit board 32 provided in the embodiment of the present application, since the circuit board 32 includes a plurality of retaining walls 34 arranged in a ring shape, the underfill 33 can be blocked after the plurality of retaining walls 34 are enclosed into a ring shape, so as to prevent the underfill 33 from entering into the area enclosed by the plurality of retaining walls 34. Thus, the glue overflowing area of the underfill 33 can be accurately controlled, the amount of the underfill 33 and the coverage area of the underfill 33 can be reduced, so that the thermal stress of the underfill 33 is reduced, the influence of the thermal stress of the underfill 33 on a welding spot is avoided at least to a certain extent, the problem of failure of the welding spot is avoided, the structural strength of the circuit board 32 can be improved due to the arrangement of the retaining wall 34, and the deformation and stress risk of the circuit board 32 are reduced.

In the circuit board assembly 30 provided in the embodiment of the present application, at least one of the circuit board 32 and the first electronic component 31 includes a plurality of retaining walls 34, and the plurality of retaining walls 34 can block the underfill 33 after being enclosed into a ring shape, so as to prevent the underfill 33 from entering into an area enclosed by the plurality of retaining walls 34. Thus, the glue overflow area of the underfill 33 can be accurately controlled, and the amount of the underfill 33 and the coverage area of the underfill 33 can be reduced, thereby reducing the thermal stress of the underfill 33, avoiding the influence of the thermal stress of the underfill 33 on the solder joints at least to a certain extent, and avoiding the problem of solder joint failure.

Since the underfill 33 flows in the direction from the outer periphery of the first electronic component 31 to the center of the first electronic component 31, voids and the like are likely to exist in the underfill 33 in the middle of the first electronic component 31, which causes dendrites to be generated, and thus the operating voltage difference between two adjacent pin terminals 312 at the position is large, which is likely to cause short circuit. Referring to fig. 21, in the first electronic component 31, the area surrounded by the plurality of retaining walls 34 is located in the middle area of the first surface 3111, so that when the first electronic component 31 is mounted on the circuit board 32, the underfill 33 may not enter the area surrounded by the plurality of retaining walls 34 under the blocking action of the plurality of retaining walls 34, and the underfill 33 is disposed between the first surface 3111 and the second surface 3211 and surrounds the periphery of the ring defined by the plurality of retaining walls 34, so that the problems of voids and the like in the underfill 33 located in the middle can be avoided at least to a certain extent, and the short circuit problem is solved.

It should be noted that "middle" is to be understood in a broad sense, that the area enclosed by the plurality of retaining walls 34 is located in the middle area of the first surface 3111 means that the area enclosed by the plurality of retaining walls 34 is offset from the peripheral edge of the first surface 3111, specifically, the offset distance between the center of the area enclosed by the plurality of retaining walls 34 and the center of the first surface 3111 is smaller than a predetermined value (for example, the predetermined value is 4mm, 3mm, 2mm, 1mm, 0.5mm, 0.3mm or 0.25 mm), for example, the center of the area enclosed by the plurality of retaining walls 34 is coincident with the center of the first surface 3111.

In some embodiments, referring to fig. 21, a plurality of retaining walls 34 are disposed on the device body 311, at least two pin terminals 312 are located in a region surrounded by the retaining walls 34, specifically, the pin terminals 312 further include a first pin terminal 312a and a second pin terminal 312b adjacent to each other, the first pin terminal 312a and the second pin terminal 312b are located in the region surrounded by the retaining walls 34, and an operating voltage difference between the first pin terminal 312a and the second pin terminal 312b is greater than or equal to 1v (e.g., 1.5v, 2v, 3v, 4v, or 5 v).

For the circuit board assembly 30, when the region surrounded by the plurality of retaining walls 34 arranged in a ring shape is located in the middle region of the first surface 3111, the underfill 33 may not enter the region surrounded by the plurality of retaining walls 34 under the blocking action of the plurality of retaining walls 34, but may be located around the periphery of the ring defined by the plurality of retaining walls 34, so as to avoid the problems of the voids in the underfill 33 at the middle position of the first electronic component 31 at least to some extent, and solve the short circuit problem that the working voltage difference is large and two adjacent pin terminals 312/pads 322 are short-circuited in the region surrounded by the plurality of retaining walls 34.

In some embodiments, referring to fig. 11 again, the second surface 3211 is provided with a plurality of retaining walls 34, at least two pads 322 are located in a region surrounded by the plurality of retaining walls 34, specifically, the plurality of pads 322 further includes a first pad 322a and a second pad 322b which are adjacently disposed, the first pad 322a and the second pad 322b are located in the region surrounded by the plurality of retaining walls 34, and an operating voltage difference between the first pad 322a and the second pad 322b is greater than or equal to 1v (e.g., 1.5v, 2v, 3v, 4v, or 5 v).

In some embodiments, please refer to fig. 26, fig. 26 is a cross-sectional structure diagram of a circuit board assembly 30 according to still other embodiments of the present application, and the retaining wall 34 is located at an edge of the first surface 3111. Specifically, when the retaining wall 34 is disposed on the first surface 3111 of the device body 311, by disposing the retaining wall 34 at the edge of the first surface 3111, on one hand, the gap between the device body 311 and the circuit board body 321 can be reduced, so as to isolate the underfill 33 outside the retaining wall 34, and enable the underfill 33 to surround the periphery of the device body 311 to realize physical adhesive isolation, and on the other hand, the package contact angle can be increased, which is beneficial for the underfill 33 to bond the peripheral wall of the retaining wall 34 and the portion of the second surface 3211 of the circuit board 32 surrounding the retaining wall 34, thereby improving the connection force between the circuit board body 321 and the device body 311 and improving the packaging effect.

When the retaining wall 34 is disposed on the second surface 3211 of the circuit board 32, the retaining wall 34 is disposed at the edge of the first surface 3111, on one hand, the gap between the circuit board body 321 and the device body 311 can be reduced, so as to isolate the underfill 33 outside the retaining wall 34, and enable the underfill 33 to surround the periphery of the device body 311, thereby realizing physical adhesive isolation, and on the other hand, the package contact angle can be increased, which is favorable for the underfill 33 to bond the peripheral wall of the retaining wall 34, the part of the second surface 3211 surrounding the retaining wall 34, and the peripheral wall of the device body 311, thereby improving the connection force between the circuit board body 321 and the device body 311, and improving the package effect.

When the retaining walls 34 are disposed on the first surface 3111 of the device body 311 and the second surface 3211 of the circuit board 32, the retaining walls 34 of the first surface 3111 are connected to the retaining walls 34 of the second surface 3211, and the retaining walls 34 of the first surface 3111 and the retaining walls 34 on the second surface 3211 are disposed at the edges of the first surface 3111, so that on one hand, the gap between the circuit board body 321 and the device body 311 can be reduced, the underfill 33 is isolated outside the retaining walls 34, and the underfill 33 is surrounded on the periphery of the device body 311, thereby realizing physical adhesive isolation, and on the other hand, the package contact angle can be increased, which is beneficial to the underfill 33 to bond the peripheral walls of the two retaining walls 34, the portion of the second surface 3211 surrounding the retaining walls 34, and the peripheral wall of the device body 311, thereby improving the connection force between the circuit board body 321 and the device body 311, and improving the package effect.

In some embodiments, retaining wall 34 is metallic or non-metallic. Alternatively, the retaining wall 34 is a metal wire, such as a copper wire. Alternatively, the retaining wall 34 may be implemented using a structural material that is non-metallic on the inside and has a weldable coating on the outside. Alternatively, the retaining wall 34 may be a piece of high molecular material. Specifically, the retaining wall 34 is a plastic component, for example, a retaining wall 34 with a certain height is directly preformed on the first electronic component 31 or the circuit board 32.

In some embodiments, referring to fig. 26, the device body 311 of the first electronic component 31 includes a substrate 3112 and a die 3113, wherein a side surface of the substrate 3112 of the first electronic component 31 facing the circuit board 32 is a first surface 3111, and the die 3113 is disposed on a side surface of the substrate 3112 of the first electronic component 31 opposite to the first surface 3111, that is, a third surface 3114.

Specifically, when the retaining wall 34 is disposed on the device body 311 of the first electronic component 31, the retaining wall 34 and the substrate 3112 of the first electronic component 31 are an integral piece. When the retaining wall 34 is disposed on the circuit board 32, the retaining wall 34 and the circuit board body 321 are an integral piece. The integral structure has higher strength and simpler processing technology. Illustratively, the retaining wall 34 is directly integrated on the substrate 3112 or the circuit board body 321 of the first electronic component 31 through a semiconductor process or a device manufacturing process, and no additional processing is required when the device is applied, so that the cost is low.

In some embodiments, the substrate 3112 and the circuit board body 321 of the first electronic component 31 each include a multilayer wiring structure in which metal layers and insulating dielectric layers are sequentially alternated and stacked. The retaining wall 34 may be formed by thickening an insulating medium layer on the surface layer of the substrate 3112 of the first electronic component 31 or the circuit board body 321.

Referring to fig. 27, fig. 27 is a cross-sectional structural view of a circuit board assembly 30 according to still other embodiments of the present application. A groove 3212 may be formed in the substrate 3112 or the circuit board body 321 of the first electronic component 31, and the substrate 3112 or the groove 3212 of the circuit board body 321 of the first electronic component 31 penetrates through at least one metal layer and at least one insulating dielectric layer of the multilayer wiring structure, so that a step portion may be formed on the substrate 3112 or the circuit board 32 of the first electronic component 31, and the step portion may define the retaining wall 34. Here, it can be understood that when the groove 3212 is opened on the circuit board body 321 to form the retaining wall 34, the pad 322 soldered to the first electronic component 31 is located at the bottom wall of the groove 3212. Similarly, when the substrate 3112 of the first electronic component 31 is provided with the groove 3212 to form the retaining wall 34, the plurality of pin terminals 312 on the device body 311 are located in the retaining wall 34.

Referring to fig. 21, for the plurality of retaining walls 34 disposed on the first electronic component 31, at least two adjacent retaining walls 34 are spaced apart. Illustratively, in the particular example shown in fig. 21, any two adjacent retaining walls 34 are spaced apart. This arrangement may further facilitate the rational utilization of the blank area of the first surface 3111.

Referring to fig. 23, fig. 23 is a bottom view of the first electronic component 31 according to other embodiments of the present application. In fig. 23, as for the plurality of retaining walls 34 disposed on the first electronic component 31, any two adjacent retaining walls 34 are connected, so that the plurality of retaining walls 34 are arranged in a closed ring shape, and the retaining effect of the closed-loop retaining wall 34 on the underfill 33 is better.

With continued reference to fig. 19 and 20, for the retaining walls 34 on the circuit board 32, at least two adjacent retaining walls 34 are spaced apart. Illustratively, in the specific example shown in fig. 19 and 20, any two adjacent retaining walls 34 are spaced apart. With such an arrangement, the blank area of the second surface 3211 can be more favorably utilized.

Referring to fig. 24 and 25, fig. 24 is a top view of a circuit board assembly 30 according to an embodiment of the present disclosure, fig. 24 does not show a first electronic component 31, and fig. 25 is a top view of a circuit board 32 in the circuit board assembly 30 shown in fig. 24. In fig. 24 and 25, as for the plurality of retaining walls 34 provided on the circuit board 32, any two adjacent retaining walls 34 are connected, so that the plurality of retaining walls 34 are arranged in a closed ring shape, and the retaining effect of the closed ring-shaped retaining wall 34 on the underfill 33 is better.

In some examples, during the mounting process of the circuit board assembly 30, since the soldering material is disposed on the pad 322 of the circuit board 32, the pin terminal 312 of the first electronic component 31 is adhered to the soldering material, and the soldering of the first electronic component 31 and the circuit board 32 is realized as a whole after the soldering material is heated and melted, by making the height dimension of the retaining wall 34 in the direction perpendicular to the circuit board 32 be h, the distance between the first surface 3111 and the second surface 3211 be d, and h and d satisfy: d-h is less than or equal to 50 microns, which is beneficial to ensuring the reliable connection between the circuit board 32 and the first electronic component 31 through welding spots. Specifically, d-h takes the value of 40 microns, 35 microns, 30 microns, 20 microns, or 15 microns.

With continued reference to fig. 26 and 27, the circuit board assembly 30 includes a second electronic component 36, the second electronic component 36 is disposed on a side of the first electronic component 31 away from the circuit board 32, the first electronic component 31 has a third surface 3114 facing the second electronic component 36, and the third surface 3114 is provided with a pad. The second electronic component 36 has a fourth surface 361 facing the first electronic component 31, the fourth surface 361 has pin terminals, the pin terminals of the fourth surface 361 are soldered to the pads of the third surface 3114, at least one of the third surface 3114 and the fourth surface 361 has a plurality of glue-repellent portions 37, and the plurality of glue-repellent portions 37 are arranged in a ring shape. Because at least one of the second electronic component 36 and the first electronic component 31 includes the plurality of glue-repellent portions 37, the underfill 33 can be blocked after the plurality of glue-repellent portions 37 are enclosed into a ring shape, and the underfill 33 is prevented from entering the area enclosed by the plurality of glue-repellent portions 37. Thus, the amount of the underfill 33 and the coverage area of the underfill 33 can be reduced, thereby reducing the thermal stress of the underfill 33, avoiding the influence of the thermal stress of the underfill 33 on the solder joints between the connection terminals and the die pad 322, and avoiding the failure problem.

In some embodiments, the glue repellants 37 are located at an edge of the fourth surface 361 or the third surface 3114. Through locating the portion 37 that rejects glue at the edge of fourth surface 361 or third surface 3114, can reduce the gap between fourth surface 361 and the third surface 3114 on the one hand, reach and keep apart underfill 33 outside the portion 37 that rejects glue, make underfill 33 enclose the periphery of establishing at a plurality of portions 37 that reject glue, realize physically separating gluey, on the other hand can increase the encapsulation contact angle, do benefit to underfill 33 and bond the periphery wall, device body 311 and the second electronic components 36 that reject glue portion 37, improve the joining force between first electronic components 31 and the second electronic components 36, improve the encapsulation effect.

In some embodiments, the glue-repellent portion 37 may be a polymer material, for example, the glue-repellent portion 37 with a certain height is dispensed and prepared directly on the third surface 3114 or the fourth surface 361.

In some embodiments, when the glue-repellent portion 37 is disposed on the device body 311, the glue-repellent portion 37 and the substrate 3112 of the first electronic component 31 are an integral piece. When the second electronic component 36 is provided with the glue-repelling portion 37, the glue-repelling portion 37 and the substrate of the second electronic component 36 are an integral piece. The integral structure has higher strength and simpler processing technology.

In some embodiments, the substrate 3112 of the first electronic component 31 and the substrate of the second electronic component 36 each include a multilayer wiring structure in which metal layers and insulating medium layers are sequentially alternated and stacked. The glue-repelling portion 37 may be formed by thickening an insulating medium layer on the surface of the substrate 3112 for the first electronic component 31 and the substrate for the second electronic component 36.

Referring to fig. 27, fig. 27 is a cross-sectional structure view of a circuit board assembly 30 according to an embodiment of the present disclosure. A molding groove 31121 may be formed in the substrate 3112 of the first electronic component 31 and the substrate of the second electronic component 36, and the molding groove 31121 of the substrate 3112 of the first electronic component 31 and the substrate of the second electronic component 36 may penetrate through at least one metal layer and at least one insulating medium layer of the multilayer wiring structure, so that a step portion may be formed in the substrate 3112 of the first electronic component 31 and the substrate of the second electronic component 36, and the step portion may define the glue-repelling portion 37. Here, it is understood that when the mold groove 31121 is opened on the substrate 3112 of the first electronic component 31 to form the repellent portion 37, the land to which the second electronic component 36 described above is soldered is located at the bottom wall of the mold groove 31121. Similarly, when the molding groove 31121 is formed on the substrate of the second electronic component 36 to form the glue-repelling portion 37, the plurality of pin terminal connection terminals on the second electronic component 36 are located in the glue-repelling portion 37.

In some examples, the plurality of glue repellers 37 may be arranged in a closed loop to enhance the blocking effect of the underfill 33. Of course, in other examples, a plurality of the glue repellants 37 may be spaced apart.

Optionally, the first electronic component 31 or the second electronic component 36 is an Integrated Circuit (IC), and particularly, the chip includes, but is not limited to, an Application Processor (AP), a Double Data Rate (DDR), and a universal flash memory (UFS). The first electronic component 31 may be packaged in a Wafer Level Package (WLP) manner or a non-wafer level package. Wafer level packages include, but are not limited to, Fan-in wafer level chip scale packages (Fn-in WLCSP) and Fan-out WLCSP. Non-wafer level packages include, but are not limited to, a flip-chip scale package (Fan-out WLCSP), a flip-chip ball grid array (FCBGA) package, and a wire-bonded ball grid array (WBBGA) package, and are not particularly limited herein.

Specifically, the first electronic component 31 is an application processor, and the second electronic component 36 is a double-rate synchronous dynamic random access memory.

In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. An electronic component, comprising:

a device body having a first surface;

the plurality of pin terminals are arranged on the first surface and comprise a plurality of rows of pin terminals, the plurality of pin terminals of each row of pin terminals are used for realizing the same signal transmission, and the plurality of rows of pin terminals are arranged in a ring shape.

2. The electronic component as claimed in claim 1, wherein a region surrounded by the plurality of rows of pin terminals is located in a central region of the first surface.

3. The electronic component as claimed in claim 1, wherein the plurality of pin terminals further includes a first pin terminal and a second pin terminal disposed adjacently, the first pin terminal and the second pin terminal are located in an area enclosed by the plurality of rows of pin terminals, and an operating voltage difference between the first pin terminal and the second pin terminal is greater than or equal to 1 v.

4. The electronic component as claimed in any one of claims 1 to 3, wherein the plurality of rows of pin terminals are configured to achieve the same signal transmission.

5. The electronic component according to any one of claims 1 to 3, wherein at least two adjacent rows of pin terminals are used to realize different signal transmission.

6. An electronic component, comprising:

the device comprises a device body, a first circuit board and a second circuit board, wherein the device body is provided with a first surface which is provided with a pin terminal suitable for being welded with the circuit board;

the retaining walls are arranged on the first surface and protrude out of the first surface, and the retaining walls are arranged in a ring shape.

7. The electronic component as claimed in claim 6, wherein the region surrounded by the plurality of retaining walls is located in a middle region of the first surface.

8. The electronic component as claimed in claim 6, wherein the plurality of pin terminals include a first pin terminal and a second pin terminal disposed adjacently, the first pin terminal and the second pin terminal are located in an area surrounded by the plurality of retaining walls, and an operating voltage difference between the first pin terminal and the second pin terminal is greater than or equal to 1 v.

9. An electronic component as claimed in claim 6, wherein the dam is located at an edge of the first surface.

10. The electronic component as claimed in claim 6, wherein the dam is metal or nonmetal.

11. The electronic component according to any one of claims 6 to 10, wherein the plurality of retaining walls are arranged in a closed loop shape.

12. An electronic component as claimed in any one of claims 6 to 10, wherein at least two of the retaining walls adjacent to each other are spaced apart.

13. A circuit board, comprising:

a circuit board body having a second surface;

the plurality of pads are arranged on the second surface and comprise a plurality of rows of pads, the plurality of pads of each row of pads are used for realizing the same signal transmission, a connecting band is connected between any two adjacent pads in each row of pads, and the plurality of rows of pads are arranged in a ring shape.

14. The circuit board of claim 13, wherein the plurality of pads further comprises a first pad and a second pad disposed adjacent to each other, the first pad and the second pad are located in a region surrounded by the plurality of rows of pads, and an operating voltage difference between the first pad and the second pad is greater than or equal to 1 v.

15. The circuit board according to any one of claims 13-14, wherein the rows of pads are configured to achieve the same signal transmission, and the connection tape is connected between two adjacent rows of pads.

16. The circuit board according to any one of claims 13-14, wherein at least two adjacent rows of the plurality of rows of pads are used for achieving different signal transmission, and the two adjacent rows of pads achieving different signal transmission are spaced apart.

17. The circuit board of claim 16, wherein any two adjacent rows of the plurality of rows of pads are configured to implement different signal transmission, and wherein the two adjacent rows of pads are spaced apart.

18. A circuit board, comprising:

the circuit board comprises a circuit board body, a first connecting piece and a second connecting piece, wherein the circuit board body is provided with a second surface, and the second surface is provided with a welding disc suitable for being welded with an electronic component;

and the retaining walls are arranged on the second surface and are arranged in a ring shape.

19. The circuit board of claim 18, wherein the number of the pads is plural, the plural pads include a first pad and a second pad which are adjacently disposed, the first pad and the second pad are located in an area surrounded by the plural barriers, and an operating voltage difference between the first pad and the second pad is greater than or equal to 1 v.

20. The circuit board of claim 18, wherein the retaining wall is metal or non-metal.

21. The circuit board of any one of claims 18-20, wherein the plurality of retaining walls are arranged in a closed loop.

22. The circuit board of any one of claims 18-20, wherein at least two adjacent retaining walls are spaced apart.

23. A circuit board assembly, comprising:

a first electronic component as claimed in any one of claims 1 to 5;

a circuit board according to any one of claims 13 to 17, wherein a second surface of the circuit board is opposite to the first surface of the first electronic component, and the plurality of rows of pin terminals of the first electronic component are respectively soldered to the plurality of rows of pads of the circuit board.

24. A circuit board assembly, comprising:

a first electronic component as claimed in any one of claims 6 to 12;

the circuit board, the circuit board has the second surface, the second surface with first surface of first electronic components is relative, the second surface is equipped with the pad, the pad with the pin terminal welding of first surface, a plurality of barricades of first electronic components are located first surface with between the second surface.

25. The circuit board assembly according to claim 24, wherein the height dimension of the retaining wall in a direction perpendicular to the circuit board is h, the distance between the first surface and the second surface is d, and h and d satisfy: d-h is less than or equal to 50 microns.

26. The circuit board assembly of claim 24, further comprising:

the second electronic component is arranged on one side, away from the circuit board, of the first electronic component, the first electronic component is provided with a third surface facing the second electronic component, a pad is arranged on the third surface, a fourth surface facing the first electronic component is arranged on the second electronic component, a pin terminal is arranged on the fourth surface, the pin terminal on the fourth surface is welded on the pad on the third surface, at least one of the third surface and the fourth surface is provided with a plurality of glue-repelling portions, the glue-repelling portions are located between the third surface and the fourth surface, and the glue-repelling portions are arranged in an annular shape.

27. The circuit board assembly of claim 26, wherein the glue repellant is located at an edge of the third surface or the fourth surface.

28. A circuit board assembly, comprising:

a first electronic component having a first surface with a pin terminal;

the circuit board according to any one of claims 18 to 22, wherein a second surface of the circuit board is opposite to the first surface of the first electronic component, and the pads of the second surface are soldered to the pin terminals of the first surface, and the plurality of retaining walls of the circuit board are located between the first surface and the second surface.

29. The circuit board assembly of claim 28, wherein the height dimension of the retaining wall in a direction perpendicular to the circuit board is h, the distance between the first surface and the second surface is d, and h and d satisfy: d-h is less than or equal to 50 microns.

30. The circuit board assembly of claim 28, wherein the region surrounded by the plurality of retaining walls is located in a middle region of the first surface of the first electronic component.

31. The circuit board assembly of claim 28, wherein the dam is located at an edge of the first surface of the first electronic component.

32. The circuit board assembly of claim 28, further comprising:

33. The circuit board assembly of claim 32, wherein the glue repelling portion is located at an edge of the third surface or the fourth surface.

34. An electronic device, comprising:

a housing;

the circuit board assembly of any one of claims 23-33, disposed within the housing.