CN214203168U - Liquid crystal display device having a plurality of pixel electrodes - Google Patents
Liquid crystal display device having a plurality of pixel electrodes Download PDFInfo
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- CN214203168U CN214203168U CN202022976558.7U CN202022976558U CN214203168U CN 214203168 U CN214203168 U CN 214203168U CN 202022976558 U CN202022976558 U CN 202022976558U CN 214203168 U CN214203168 U CN 214203168U
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Abstract
The utility model discloses a liquid crystal display device, including display panel, sequential control circuit, gate drive circuit and source drive circuit, wherein, liquid crystal display device still includes: a backlight circuit providing a backlight to the display panel; the backlight driving circuit is connected with the backlight circuit and used for providing a backlight enabling signal and a backlight power supply voltage for the backlight circuit so as to control the power-on and power-off of the backlight circuit; the equalization control circuit is used for generating an equalization control signal; the correction circuit is used for generating a synchronous control signal according to the backlight power supply voltage, the backlight enabling signal and the equalization control signal, and the synchronous control signal is used for controlling the power-on and power-off of an equalizer of the source electrode driving circuit so that the equalizer of the source electrode driving circuit and the backlight circuit are powered on and powered off synchronously; the screen flashing phenomenon in the process of turning on and turning off the liquid crystal display device can be further improved.
Description
Technical Field
The utility model relates to a display device technical field, in particular to liquid crystal display device.
Background
LCD (Liquid Crystal Display) has many advantages such as low power consumption, light weight, low radiation, etc., and thus has been used to replace the conventional Cathode Ray Tube (CRT) Display. Liquid crystal display devices are widely used in electronic devices such as high-definition digital televisions, desktop computers, notebook computers, tablet computers, mobile phones, digital cameras, and the like.
The liquid crystal display device in the prior art has the screen flashing phenomenon during startup and shutdown, and when the startup and the shutdown of the backlight circuit and the display panel are asynchronous, the screen flashing phenomenon of the liquid crystal display device is more serious.
Fig. 1 is a schematic view showing a structure of a liquid crystal display device of the related art. As shown in fig. 1, the liquid crystal display device 100 includes a backlight driving circuit 110, a backlight circuit 120, an equalization control circuit 130, a display panel 140, a timing control circuit 150, a gate driving circuit 160, and a source driving circuit 170.
The backlight circuit 120 is used to provide backlight to the display panel 140. The related art display panel 140 may be implemented in a vertical electric field driving method such as a Twisted Nematic (TN) mode and a Vertical Alignment (VA) mode or in a horizontal electric field driving manner such as an in-plane switching (IPS) mode and a Fringe Field Switching (FFS) mode. The related art liquid crystal display device may be implemented as any type of liquid crystal display including a transmission type liquid crystal display and a transflective type liquid crystal display, and the backlight circuit 120 may be implemented as a direct type backlight circuit or an edge type backlight circuit.
The backlight driving circuit 110 is connected to the backlight circuit 120, and generates a backlight supply voltage Vled and a backlight enable signal EN to control the backlight circuit 120 to be turned on or off.
The equalization control circuit 130 is used for generating an equalization control signal FB03, and the equalization control signal FB03 can be used for controlling the on and off of an equalizer in the source driving circuit 170. Among them, the equalizer in the source driving circuit 170 is used to compensate for signal distortion (for example, distortion of high frequency components) during transmission between the timing control circuit 150 and the source driving circuit 170.
The backlight driving circuit 110 and the equalization control circuit 130 in the liquid crystal display device 100 in the prior art are relatively independent, so that when the liquid crystal display device 100 is turned on or turned off, the timing for turning on or off the backlight circuit 120 and the display panel 140 is not synchronous, for example, the display panel 140 is turned on before the backlight circuit 120, thereby generating the phenomenon of turning on or off the display screen.
Therefore, there is a need for further improvement of the liquid crystal display device to effectively improve the problem of the flicker at the time of power-on and power-off.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide a liquid crystal display device, which further improves the screen flashing phenomenon during the on/off process of the liquid crystal display device.
According to the utility model discloses an aspect provides a liquid crystal display device, including display panel, sequential control circuit, gate drive circuit and source drive circuit, wherein, liquid crystal display device still includes: a backlight circuit providing a backlight to the display panel; the backlight driving circuit is connected with the backlight circuit and used for providing a backlight enabling signal and a backlight power supply voltage for the backlight circuit so as to control the power-on and power-off of the backlight circuit; the equalization control circuit is used for generating an equalization control signal; and the correction circuit is connected with the equalization control circuit, the backlight driving circuit and the source electrode driving circuit and used for generating a synchronous control signal according to the backlight power supply voltage, the backlight enabling signal and the equalization control signal, and the synchronous control signal is used for controlling the power-on and power-off of an equalizer of the source electrode driving circuit so as to enable the equalizer of the source electrode driving circuit to be synchronously powered on and powered off with the backlight circuit.
Optionally, the correction circuit includes: the first switching signal generating unit receives the backlight power supply voltage and the first voltage signal and generates a first switching signal according to the backlight power supply voltage and the first voltage signal; a second switching signal generating unit receiving the backlight enable signal and generating a second switching signal according to the backlight enable signal; and a switching unit connected to the first switching signal generating unit and the second switching signal generating unit, receiving the first switching signal, the second switching signal, and the equalization control signal, and generating the synchronization control signal according to the equalization control signal under control of the first switching signal and the second switching signal.
Optionally, the first switching signal generating unit includes first to fourth resistors and a comparator, where a non-inverting input terminal of the comparator is connected to a first terminal of the first resistor, a second terminal of the first resistor is connected to the backlight power supply voltage, an inverting input terminal of the comparator is connected to a first terminal of the second resistor, a second terminal of the second resistor is connected to the first voltage signal, the third resistor is connected between an output terminal of the comparator and the power supply voltage, the fourth resistor is connected between the backlight power supply voltage and ground, and an output terminal of the comparator is configured to output the first switching signal.
Optionally, the first switching signal generating unit is configured to output the first switching signal at a low level when the received backlight power supply voltage is at a low level, and output the first switching signal at a high level when the received backlight power supply voltage is at a high level.
Optionally, the second switching signal generating unit includes a D flip-flop, a phase inverter and a fifth resistor, wherein an input end of the phase inverter is connected to the backlight enable signal, an output end of the phase inverter is connected to a clock end of the D flip-flop, the fifth resistor is connected between the input end of the phase inverter and ground, a data end of the D flip-flop is connected to the power voltage, a set end and a reset end of the D flip-flop are grounded, and an output end of the D flip-flop is used for outputting the second switching signal.
Optionally, the second switching signal generating unit is configured to output the second switching signal to be at a high level when the received backlight enable signal is switched from a high level to a low level.
Optionally, the switch unit includes: the first switch, the second switch and the seventh resistor are connected between the equalization control signal and the ground in series; and a sixth resistor connected between the second control terminal of the first switch and ground, wherein the first control terminal of the first switch receives the first switch signal, the first control terminal of the second switch receives the second switch signal, the second control terminal of the second switch is grounded, and an intermediate node between the second switch and the seventh resistor is used for outputting the synchronous control signal.
Optionally, the first switch is turned on when receiving a high level and turned off when receiving a low level, and the second switch is turned on when receiving a low level and turned off when receiving a high level.
Optionally, the equalization control circuit includes: a first intermediate signal generation circuit that receives a source voltage and generates a first intermediate signal from the source voltage; a second intermediate signal generation circuit that receives a power supply voltage and generates a second intermediate signal from the power supply voltage; and an equalization control signal generation circuit connected to the first intermediate signal generation circuit and the second intermediate signal generation circuit, receiving the first intermediate signal and the second intermediate signal, and generating the equalization control signal from the first intermediate signal and the second intermediate signal. Optionally, the equalization control signal generating circuit includes: the inverting input end of the comparator is connected with a first resistor, the other end of the first resistor receives the first intermediate signal, the non-inverting input end of the comparator is connected with a second resistor, the other end of the second resistor is grounded, and the output end of the comparator outputs the balance control signal; and the third resistor and the fourth resistor are sequentially connected in series with the second intermediate signal input end and the output end of the comparator, and intermediate nodes of the third resistor and the fourth resistor are connected with the inverting input end of the comparator.
The utility model discloses a liquid crystal display device includes display panel, sequential control circuit, gate drive circuit, source drive circuit, backlight drive circuit, balanced control circuit and correction circuit. The backlight driving circuit is used for providing a backlight enabling signal and a backlight power supply voltage for the backlight circuit so as to control power-on and power-off of the backlight circuit, the correction circuit is used for generating a power-on and power-off synchronous control signal for controlling an equalizer of the source electrode driving circuit according to the backlight power supply voltage, the backlight enabling signal and an equalization control signal generated by the equalization control circuit, and therefore the influence of abnormal waveforms of the equalization control signal on a rear-stage circuit when the liquid crystal display device is started and stopped can be avoided, the equalizer of the source electrode driving circuit and the backlight circuit can be synchronously started and stopped, and the problem of screen flashing in the starting and stopping process of the liquid crystal display device is solved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic view showing a structure of a liquid crystal display device of the related art;
fig. 2 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention;
fig. 3 is a circuit configuration diagram showing the equalization control circuit of fig. 2;
FIG. 4 is a timing diagram of the equalization control circuit of FIG. 3 at power-on;
FIG. 5 shows a timing diagram for the shutdown of the equalization control circuit of FIG. 3;
FIG. 6 is a circuit configuration diagram showing the correction circuit in FIG. 2;
fig. 7 shows a timing diagram of a correction circuit of an embodiment of the present invention when starting up;
fig. 8 shows a timing diagram of the correction circuit according to an embodiment of the present invention when the power is off.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements or circuits are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Also, certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This patent specification and claims do not intend to distinguish between components that differ in name but not function.
Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. In this document, terms such as "power on" and "power off" are only used to describe that the level value represented by each signal changes when the liquid crystal display device is turned on and off, and do not necessarily imply that "power on" indicates that the level value represented by each signal is switched from a low level state to a high level state, and "power off" indicates that the level value represented by each signal is switched from the high level state to the low level state. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Fig. 2 shows a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention. As shown in fig. 2, the liquid crystal display device 200 includes a backlight driving circuit 210, a backlight circuit 220, an equalization control circuit 230, a display panel 240, a timing control circuit 250, a gate driving circuit 260, a source driving circuit 270, and a correction circuit 280.
The display panel 240 includes a plurality of pixel units arranged in an array, and each pixel unit mainly includes a Thin Film Transistor (TFT), a storage capacitor, and a liquid crystal capacitor. Each pixel unit is connected to the gate driver circuit 260 through a gate line and to the source driver circuit 270 through a source line. In response to a gate driving signal supplied through the gate line, the pixel unit may receive a data signal through the data line, store the data signal in the storage capacitor, and control light emitted from the backlight circuit 220 corresponding to the data signal, thereby displaying luminance corresponding to the data signal.
The timing control circuit 250 is used to control the gate driving circuit 260 and the source driving circuit 270. The timing control circuit 250 may receive an externally provided control signal (e.g., a control signal including a clock signal) and generate a gate control signal and a data control signal based on the control signal.
The gate driving circuit 260 may receive the gate control signal from the timing control circuit 250, generate a gate driving signal based on the gate control signal, and provide the gate driving signal to a corresponding gate line.
The source driving circuit 270 may receive the source control signal and the frame data from the timing control circuit 250, generate a data signal corresponding to the frame data, and supply the data signal to the corresponding data line.
The backlight circuit 220 is used to provide backlight to the display panel 240. The display panel 240 of the present embodiment may be implemented in a vertical electric field driving method such as a Twisted Nematic (TN) mode and a Vertical Alignment (VA) mode or in a horizontal electric field driving manner such as an in-plane switching (IPS) mode and a Fringe Field Switching (FFS) mode. The liquid crystal display device of the present embodiment may be implemented as any type of liquid crystal display including a transmission type liquid crystal display and a transflective type liquid crystal display, and the backlight circuit 220 may be implemented as a direct-type backlight circuit or an edge-light type backlight circuit.
The backlight driving circuit 210 is connected to the backlight circuit 220 and provides a backlight supply voltage Vled and a backlight enable signal EN to control the backlight circuit 220 to be turned on or off.
The correction circuit 280 is respectively connected to the equalization control circuit 230, the backlight driving circuit 210 and the source driving circuit 270 to receive the backlight supply voltage Vled, the backlight enable signal EN and the equalization control signal FB 03. The correction circuit 280 is configured to provide the synchronization control signal EQ to the source driving circuit 270 according to the equalization control signal FB03 under the control of the backlight supply voltage Vled and the backlight enable signal EN. The synchronous control signal EQ can be used to control the turning on and off of the equalizer in the source driver circuit 270. Among them, the equalizer in the source driving circuit 270 is used to compensate for signal distortion (for example, distortion of high frequency components) during transmission between the timing control circuit 250 and the source driving circuit 270.
Fig. 3 is a circuit configuration diagram showing the equalization control circuit in fig. 2. As shown in fig. 3, the equalization control circuit 230 includes a first intermediate signal generation circuit 231, a second intermediate signal generation circuit 232, and an equalization control signal generation circuit 233.
The first intermediate signal generating circuit 231 includes a digital common mode voltage unit 2311, and a first operational amplifier 2312.
The input terminal of the digital common mode voltage unit 2311 receives the power voltage AVdd, and the first operational amplifier 2312 is connected to the digital common mode voltage unit 2311, receives the output of the digital common mode voltage unit 2311, and generates the first intermediate signal FB01 according to the output of the digital common mode voltage unit 2311.
The first intermediate signal generation circuit 231 is connected to the equalization control signal generation circuit 233, receives the power supply voltage AVdd, and generates the first intermediate signal FB01 based on the received power supply voltage AVdd.
The second intermediate signal generating circuit 232 includes a voltage dividing unit 2321, and a second operational amplifier 2322.
The input end of the voltage dividing unit 2321 receives the source voltage VS —, and the second operational amplifier 2322 is connected to the voltage dividing unit 2321 to receive the output of the voltage dividing unit 2321 and generate the second intermediate signal FB02 according to the output thereof.
The second intermediate signal generating circuit 232 is connected to the equalization control signal generating circuit 233, receives the source voltage VS-, and generates a second intermediate signal FB02 according to the received source voltage VS-.
The equalization control signal generation circuit 233 includes resistors R1 to R4, and a third operational amplifier 2331. The first intermediate signal FB01 is connected to the inverting input terminal of the third operational amplifier 2331 through a resistor R1, the second intermediate signal FB02 is connected to the inverting input terminal of the third operational amplifier 2331 through a resistor R3, the non-inverting input terminal of the third operational amplifier 2331 is grounded through a resistor R2, and the output terminal outputs the equalizing control signal FB 03; the resistor R4 has a first terminal connected to the inverting input terminal of the third operational amplifier 2331 and a second terminal connected to the output terminal of the third operational amplifier 2331.
The equalization control signal generation circuit 233 receives the first intermediate signal FB01 and the second intermediate signal FB02, and generates the equalization control signal FB03 from the received first intermediate signal FB01 and second intermediate signal FB 02.
Fig. 4 is a timing diagram of the equalization control circuit of fig. 3 at power-on. The voltage waveforms of the first intermediate signal FB01, the second intermediate signal FB02, and the equalization control signal FB03 are shown in fig. 4 from top to bottom, respectively.
Referring to fig. 4, the first intermediate signal FB01 is powered on earlier than the second intermediate signal FB02 between the time periods t0-t3, so that the waveform of the equalization control signal FB03 is abnormal and a valley occurs at the time t 1. The first intermediate signal FB01 and the second intermediate signal FB02 are both powered up at time t2, so the equalization control signal FB03 waveform returns to normal after time t 2.
It should be noted that the protrusion of the equalization control signal FB03 between the time periods t2-t3 is caused by a default value when the digital common mode voltage unit 2311 is powered up.
Fig. 5 shows a timing diagram of the equalization control circuit of fig. 3 when it is turned off. The voltage waveforms of the first intermediate signal FB01, the second intermediate signal FB02, and the equalization control signal FB03 are shown in fig. 5 from top to bottom, respectively.
Referring to fig. 5, the second intermediate signal FB02 is powered down earlier than the first intermediate signal FB01 between time periods t4-t6, so that the waveform of the equalization control signal FB03 is abnormal and a valley occurs at time t 5. At time t6, the first intermediate signal FB01 and the second intermediate signal FB02 have both completed powering down, so the equalization control signal FB03 waveform returns to normal after time t 6.
As shown in fig. 4 and 5, since the equalization control signal FB03 is generated by the first intermediate signal FB01 and the second intermediate signal FB02 through reverse bias amplification of the operational amplifier, and the power-on speed and the power-off speed of the first intermediate signal FB01 and the second intermediate signal FB02 are different when the liquid crystal display device is turned on or turned off, the waveform of the equalization control signal FB03 has abnormal peaks and/or troughs when the liquid crystal display device is turned on or turned off, so that the flicker phenomenon is more serious when the liquid crystal display device is turned on or turned off.
Fig. 6 shows a circuit configuration diagram of the correction circuit in fig. 2. As shown in fig. 6, the correction circuit 280 includes a first switching signal generation unit 281, a second switching signal generation unit 282, and a switching unit 283.
The first switching signal generating unit 281 receives the backlight supply voltage Vled, the first voltage signal VGH, and the power supply voltage AVdd, and generates a first switching signal C1 according to the received backlight supply voltage Vled, the first voltage signal VGH, and the power supply voltage AVdd.
The first switching signal generating unit 281 includes resistors R1 to R4 and a comparator 2811. The backlight supply voltage Vled is connected to the non-inverting input terminal of the comparator 2811 through the resistor R1, the first voltage signal VGH is connected to the inverting input terminal of the comparator 2811 through the resistor R2, the power supply voltage AVdd is connected to the positive power terminal of the comparator 2811, the negative power terminal is grounded, the resistor R3 is connected between the positive power terminal and the output terminal of the comparator 2811, the output terminal of the comparator 2811 outputs the first switch signal C1, one end of the resistor R4 is connected to the backlight supply voltage Vled, and the other end is grounded.
When the backlight supply voltage Vled is greater than the first voltage signal VGH, the first switching signal C1 output by the output terminal of the comparator is at a high level, and when the backlight supply voltage Vled is less than the first voltage signal VGH, the first switching signal C1 output by the comparator is at a low level.
The second switching signal generating unit 282 receives the backlight enable signal EN and the power voltage AVdd, and generates a second switching signal C2 according to the received backlight enable signal EN and the power voltage AVdd.
The second switching signal generating unit 282 includes a resistor R5, an inverter INV1, and a D flip-flop 2821. The backlight enable signal EN is connected to the clock terminal of the D flip-flop 2821 through an inverter INV1, the power voltage AVdd is connected to the data terminal D of the D flip-flop 2821, the output terminal Q of the D flip-flop 2821 outputs a second switch signal C2, and the output terminal of the D flip-flop 2821
Set terminal of null, D flip-flop 2821
And a reset terminal
And (4) grounding. One end of the resistor R5 is connected to the input end of the inverter INV1, and the other end is grounded.
When the backlight enable signal EN is switched from low level to high level, the signal passing through the inverter INV1 is switched from high level to low level, a falling edge is generated, the clock terminal of the D flip-flop 2821 receives the falling edge, and the D flip-flop 2821 does not operate; when the backlight enable signal EN is switched from high level to low level, the signal passing through the inverter INV1 is switched from low level to high level to generate a rising edge, the clock terminal of the D flip-flop 2821 receives the rising edge, and the output terminal Q outputs high level, that is, outputs the second switching signal C2 with the same amplitude as the voltage represented by the power voltage AVdd.
The switch unit 283 is connected to the first and second switch signal generating units 281 and 282, respectively, to generate the synchronization control signal EQ according to the equalization control signal FB03 under the control of the first and second switch signals C1 and C2.
The switch unit 283 includes a resistor R6, a resistor R7, a first switch S1 and a second switch S2. The first switch S1, the second switch S2 and the resistor R7 are sequentially connected in series between the equalization control signal FB03 and the ground, the first terminal of the first switch S1 receives the equalization control signal FB03, the first control terminal of the first switch S1 receives the first switch signal C1, the second terminal of the first switch S1 is connected with the second control terminal of the first switch S1, and the resistor R6 is connected between the second control terminal of the first switch S1 and the ground. A first terminal of the second switch S2 is connected to a second terminal of the first switch S1, a first control terminal of the second switch S2 receives the second switch signal C2, a second control terminal of the second switch S2 is grounded, and an intermediate node between the second switch S2 and the seventh resistor R7 is configured to output the synchronous control signal EQ.
The first switch S1 is turned on when the first switch signal C1 is high, and the first switch S1 is turned off when the first switch signal C1 is low. When the second switching signal C2 is high, the second switch S2 is in an off state, and when the second switching signal C2 is low, the second switch S2 is in an on state.
Fig. 7 shows a timing diagram of the correction circuit according to an embodiment of the present invention when the computer is turned on. The voltage waveforms of the backlight supply voltage Vled, the backlight enable signal EN, the equalization control signal FB03 and the synchronization control signal EQ are shown in sequence from top to bottom. The operation principle of the correction circuit of the present embodiment will be described in detail with reference to fig. 6 and 7.
As shown in fig. 7, in the time period t7-t8, the backlight enable signal EN is switched from low level to high level, the backlight supply voltage Vled is maintained at low level, the signal state is switched from high level to low level after passing through the inverter INV1, the clock terminal of the D flip-flop 2821 receives the falling edge signal, the D flip-flop 2821 does not operate, the output terminal Q still outputs low level, that is, the second switch signal C2 is still low level, and the second switch S2 remains on. Since the backlight power supply voltage Vled is at a low level, and the voltage value (e.g. 0V) thereof is smaller than the voltage value (e.g. 18V) of the first voltage signal VGH, the output terminal of the comparator 2811 outputs a low level, i.e. the first switch signal C1 is at a low level, and the first switch S1 is in an off state, the switch unit 283 is in an off state at this time, and thus the synchronous control signal EQ is maintained at a low level.
At time t8, the backlight supply voltage Vled is switched from low level to high level, the backlight circuit 220 is turned on, and meanwhile, the voltage value (e.g. 26V) of the backlight supply voltage Vled is greater than the voltage value (e.g. 18V) of the first voltage signal VGH, the output of the comparator 2811 is inverted to high level, that is, the first switch signal C1 is high level, and the first switch S1 is turned on. From time t8, the signal path between the input and output terminals of switch unit 283 is turned on, and synchronization control signal EQ is synchronously changed following equalization control signal FB 03.
The correction circuit of the embodiment disconnects the signal path from the equalization control signal to the source electrode driving circuit before the backlight power supply voltage is not electrified, and switches on the signal path from the equalization control signal to the source electrode driving circuit after the backlight power supply voltage is electrified, so that the source electrode driving circuit is provided with the synchronous control signal according to the equalization control signal, and the influence of waveform abnormality of the equalization control signal on a rear-stage circuit caused by different electrifying speeds of the first intermediate signal and the second intermediate signal when the liquid crystal display device is started can be effectively avoided, and the problem of screen flashing caused by waveform abnormality of the equalization control signal when the liquid crystal display device is switched on and switched off is solved. In addition, the correction circuit provides a synchronous control signal to the source electrode driving circuit after the backlight power supply voltage is electrified, so that the backlight circuit and the display panel can be simultaneously opened during starting, and the screen flashing phenomenon during starting can be further improved.
Fig. 8 shows a timing diagram of the correction circuit according to an embodiment of the present invention when the power is off. The voltage waveforms of the backlight supply voltage Vled, the backlight enable signal EN, the equalization control signal FB03 and the synchronization control signal EQ are shown in sequence from top to bottom. The operation principle of the correction circuit of the present embodiment when the liquid crystal display device is turned off will be described in detail with reference to fig. 6 and 8.
As shown in fig. 8, at time t9, the backlight enable signal EN is switched from high level to low level, the backlight circuit 220 is turned off, the signal state passing through the inverter INV1 is switched from low level to high level, the clock receiving terminal of the D flip-flop 2521 receives a rising edge signal, the output terminal Q outputs high level, that is, outputs a level signal having an amplitude equal to the voltage value (e.g., 10V) represented by the power voltage AVdd, that is, the second switch signal C2 is switched to high level, the second switch S2 is turned off, the signal path between the input terminal and the output terminal of the switch unit 283 is disconnected, and the synchronization control signal EQ is maintained at low level.
The correction circuit of the embodiment disconnects the signal path between the equalization control signal and the source electrode driving circuit after the power failure of the backlight enabling signal, so that the influence of abnormal waveform of the equalization control signal on a rear-stage circuit caused by different power failure speeds of the first intermediate signal and the second intermediate signal when the liquid crystal display device is shut down can be effectively avoided, and the problem of screen flashing caused by abnormal waveform of the equalization control signal when the liquid crystal display device is switched on and switched off is solved. Meanwhile, the backlight circuit and the display panel are simultaneously closed when the computer is turned off, and the phenomenon of screen flashing when the computer is turned off is further improved.
It should be noted that as used herein, the words "during", "when" and "when … …" in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
In accordance with the present invention, as set forth above, these embodiments do not set forth all of the details nor limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The scope of the present invention should be determined by the appended claims and their equivalents.
Claims (10)
1. A liquid crystal display device comprises a display panel, a time sequence control circuit, a grid drive circuit and a source drive circuit, and is characterized by further comprising:
a backlight circuit providing a backlight to the display panel;
the backlight driving circuit is connected with the backlight circuit and used for providing a backlight enabling signal and a backlight power supply voltage for the backlight circuit so as to control the power-on and power-off of the backlight circuit;
the equalization control circuit is used for generating an equalization control signal; and
and the correction circuit is connected with the equalization control circuit, the backlight driving circuit and the source electrode driving circuit and is used for generating a synchronous control signal according to the backlight power supply voltage, the backlight enabling signal and the equalization control signal, and the synchronous control signal is used for controlling the power-on and power-off of an equalizer of the source electrode driving circuit so that the equalizer of the source electrode driving circuit and the backlight circuit are synchronously powered on and powered off.
2. The liquid crystal display device according to claim 1, wherein the correction circuit comprises:
the first switching signal generating unit receives the backlight power supply voltage and a first voltage signal and generates a first switching signal according to the backlight power supply voltage and the first voltage signal;
a second switching signal generating unit receiving the backlight enable signal and generating a second switching signal according to the backlight enable signal; and
and the switching unit is connected with the first switching signal generation unit and the second switching signal generation unit, receives the first switching signal, the second switching signal and the balance control signal, and generates the synchronous control signal according to the balance control signal under the control of the first switching signal and the second switching signal.
3. The liquid crystal display device according to claim 2, wherein the first switching signal generating unit includes first to fourth resistors and a comparator,
wherein a non-inverting input terminal of the comparator is connected with a first terminal of a first resistor, a second terminal of the first resistor is connected with the backlight supply voltage,
the inverting input end of the comparator is connected with the first end of a second resistor, the second end of the second resistor is connected with the first voltage signal,
the third resistor is connected between the output end of the comparator and a power supply voltage, the fourth resistor is connected between the backlight power supply voltage and the ground, and the output end of the comparator is used for outputting the first switching signal.
4. The liquid crystal display device according to claim 3,
the first switching signal generating unit is configured to output the first switching signal at a low level when the received backlight power supply voltage is at a low level,
and outputting the first switching signal to be at a high level when the received backlight power supply voltage is at the high level.
5. The liquid crystal display device according to claim 4, wherein the second switching signal generating unit includes a D flip-flop, an inverter, and a fifth resistor,
wherein the input end of the phase inverter is connected with the backlight enabling signal, the output end of the phase inverter is connected with the clock end of the D trigger,
the fifth resistor is connected between the input terminal of the inverter and ground,
and the data end of the D trigger is connected with the power supply voltage, the position end and the reset end are grounded, and the output end is used for outputting the second switching signal.
6. The liquid crystal display device according to claim 5,
the second switching signal generating unit is configured to output the second switching signal to a high level when the received backlight enable signal is switched from a high level to a low level.
7. The liquid crystal display device according to claim 6, wherein the switching unit comprises:
the first switch, the second switch and the seventh resistor are connected between the equalization control signal and the ground in series; and
a sixth resistor connected between the second control terminal of the first switch and ground,
the first control end of the first switch receives the first switching signal, the first control end of the second switch receives the second switching signal, the second control end of the second switch is grounded, and an intermediate node between the second switch and the seventh resistor is used for outputting the synchronous control signal.
8. The liquid crystal display device according to claim 7, wherein the first switch is turned on when receiving a high level and turned off when receiving a low level, and
the second switch is switched on when receiving a low level and switched off when receiving a high level.
9. The liquid crystal display device according to claim 1, wherein the equalization control circuit comprises:
a first intermediate signal generation circuit that receives a source voltage and generates a first intermediate signal from the source voltage;
a second intermediate signal generation circuit that receives a power supply voltage and generates a second intermediate signal from the power supply voltage; and
and an equalization control signal generation circuit connected to the first intermediate signal generation circuit and the second intermediate signal generation circuit, receiving the first intermediate signal and the second intermediate signal, and generating the equalization control signal based on the first intermediate signal and the second intermediate signal.
10. The liquid crystal display device according to claim 9, wherein the equalization control signal generation circuit comprises:
a comparator, an inverting input terminal of the comparator is connected with a first resistor, the other terminal of the first resistor receives the first intermediate signal,
the non-inverting input end of the comparator is connected with a second resistor, the other end of the second resistor is grounded,
the output end of the comparator outputs the equalization control signal;
and the third resistor and the fourth resistor are sequentially connected in series with the second intermediate signal input end and the output end of the comparator, and intermediate nodes of the third resistor and the fourth resistor are connected with the inverting input end of the comparator.
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| CN202022976558.7U CN214203168U (en) | 2020-12-08 | 2020-12-08 | Liquid crystal display device having a plurality of pixel electrodes |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113851094A (en) * | 2021-09-18 | 2021-12-28 | 深圳创维－Rgb电子有限公司 | Drive circuit and drive method for LCD startup display |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113851094A (en) * | 2021-09-18 | 2021-12-28 | 深圳创维－Rgb电子有限公司 | Drive circuit and drive method for LCD startup display |
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