CN214099626U

CN214099626U - Semiconductor packaging structure

Info

Publication number: CN214099626U
Application number: CN202022927541.2U
Authority: CN
Inventors: 金水来
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2020-12-07
Filing date: 2020-12-07
Publication date: 2021-08-31
Anticipated expiration: 2030-12-07

Abstract

The embodiment of the application relates to a semiconductor packaging structure. A semiconductor package structure according to an embodiment includes: a first die having a first surface; a second die bonded to the first die, the second die having a second surface facing the first surface; a first magnetic element disposed on one of the first die or the second die; and a second magnetic element disposed at a respective location of one of the first die or the second die and at least partially overlapping the first magnetic element. The semiconductor packaging structure provided by the embodiment of the application has the advantages of simple and efficient manufacturing process, good product quality and higher production efficiency.

Description

Semiconductor packaging structure

Technical Field

The embodiment of the application relates to the field of semiconductors, in particular to a semiconductor packaging structure.

Background

In order to obtain a semiconductor package structure with a Hybrid bonding pad (Hybrid bonding pad) connecting a top die and a bottom die, the prior art uses a vacuum suction method to pick up and move the top die by using a pick arm or a bonding head, and lowers the pick arm or the bonding head to drive the top die to descend, so as to achieve physical contact between the Hybrid bonding surface of the top die and the Hybrid bonding surface of the bottom die. At the same time, a visual assistance system is used to assist in the alignment of the bond pads of the top and bottom dies. However, the accuracy of aligning the bonding pads of the die by means of visual inspection is not high, resulting in a degradation of the product quality of the semiconductor package structure. Moreover, the manufacturing process has low production efficiency.

Therefore, there is a need to find a more efficient and convenient method for improving the bonding process of the semiconductor package structure with the hybrid package.

SUMMERY OF THE UTILITY MODEL

It is an object of the embodiments of the present application to provide a semiconductor package structure, which provides bonding pads with magnetic material on the surface of both the top die and the bottom die, so that when the top die and the bottom die are close enough to each other, the top die and the bottom die can achieve self-alignment, thereby making the alignment of the bonding pads of the semiconductor package structure higher and the bonding process smoother. Therefore, the semiconductor packaging structure provided by the embodiment of the application has better product quality and higher production efficiency.

According to an embodiment of the present application, a semiconductor package structure is provided, which includes: a first die having a first surface; a second die bonded to the first die, the second die having a second surface facing the first surface; a first magnetic element disposed on one of the first die or the second die; and a second magnetic element disposed at a respective location of one of the first die or the second die and at least partially overlapping the first magnetic element.

In some embodiments of the present application, the first magnetic element includes a first set of conductive pads located above the first surface of the first die and including a magnetic material, and the second magnetic element includes a second set of conductive pads located above the second surface of the second die and including a magnetic material, the first and second sets of conductive pads being bonded to each other.

In some embodiments of the present application, the semiconductor package structure further comprises a third set of conductive pads located over the first surface and a fourth set of conductive pads located over the second surface, the third and fourth sets of conductive pads being bonded to each other.

In some embodiments of the present application, the first set of conductive pads and the third set of conductive pads are uniformly distributed in a checkerboard pattern.

In some embodiments of the present application, one of the first set of conductive pads or the second set of conductive pads is ferromagnetic and the other of the first set of conductive pads or the second set of conductive pads is paramagnetic.

In some embodiments of the present application, one of the first or second sets of conductive pads has a first magnetic polarity and the other of the first or second sets of conductive pads has a second magnetic polarity.

In some embodiments of the present application, each of the first set of conductive pads includes a first magnetic layer proximate the first surface of the first die, and each of the second set of conductive pads includes a second magnetic layer proximate the second surface of the second die.

In some embodiments of the present application, the first and second magnetic layers comprise ferromagnetic materials.

In some embodiments of the present application, each of the first set of conductive pads includes a first bonding layer distal to the first surface of the first die, and each of the second set of conductive pads includes a second bonding layer distal to the second surface of the second die, the first bonding layer being at least partially in contact with the second bonding layer.

In some embodiments of the present application, the semiconductor package structure further comprises a dielectric layer surrounding the first set of conductive pads and the second set of conductive pads.

In some embodiments of the present application, the first magnetic element comprises a first split line at least partially deposited with a magnetic material, and the second magnetic element comprises a second split line at least partially deposited with a magnetic material.

The semiconductor packaging structure provided by the embodiment of the application can enable different bare chips to have higher bonding alignment degree and more flexible bonding process in the bonding process. Therefore, the semiconductor packaging structure provided by the embodiment of the application has good product quality and higher production efficiency.

Drawings

The drawings necessary for describing the embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.

FIG. 1A is a schematic longitudinal cross-sectional view of a semiconductor package structure according to an embodiment of the present application

FIG. 1B is a schematic bottom view of the first die in the semiconductor package structure shown in FIG. 1A

FIG. 1C is a schematic top view of the semiconductor package of FIG. 1A with a second die disposed thereon

FIG. 1D is a schematic top view of another arrangement of a second die in the semiconductor package shown in FIG. 1A

FIG. 2 is a schematic longitudinal cross-sectional view of a semiconductor package structure according to another embodiment of the present application

FIG. 3A is a schematic longitudinal cross-sectional view of a semiconductor package structure according to yet another embodiment of the present application

FIG. 3B is a schematic bottom view of the semiconductor package structure of FIG. 3A with a first die disposed thereon

FIG. 3C is a schematic diagram of a top view of an arrangement of a second die in the semiconductor package shown in FIG. 3A

FIG. 3D is a schematic bottom view of another arrangement of the first die in the semiconductor package structure shown in FIG. 3A

FIG. 3E is a schematic top view of another arrangement of a second die in the semiconductor package shown in FIG. 3A

FIG. 4 is a schematic longitudinal cross-sectional view of a semiconductor package structure according to another embodiment of the present application

FIGS. 5A, 5B, 5C and 5D are schematic flow diagrams of manufacturing a semiconductor package structure according to an embodiment of the present application, which can manufacture the semiconductor package structure shown in FIG. 1A

Detailed Description

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The examples of the present application should not be construed as limiting the present application.

As used herein, the terms "about", "substantially", "essentially" are used to describe and describe small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 0.5%, or less than or equal to ± 0.05%. For example, two numerical values may be considered "substantially" the same if the difference between the two values is less than or equal to ± 10% of the mean of the values.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In this application, unless specified or limited otherwise, "disposed," "connected," "coupled," "secured," and words of similar import are used broadly and those skilled in the art will understand that the words used above apply to situations in which, for example, a fixed connection, a removable connection, or an integrated connection; it may also be a mechanical or electrical connection; it may also be directly connected or indirectly connected through intervening structures; or may be internal to both components.

The prior art uses a vacuum suction method to pick up and move the top die by using a pick-up arm or a bonding head, the top die is firmly attached to the pick-up arm or the bonding head, and thus the prior art has insufficient freedom and flexibility. Also, the bond pads that rely on visual inspection to align the top and bottom dies have low production efficiency and less than accurate alignment. Therefore, the quality of the semiconductor structure provided by the prior art is poor and the production efficiency is low.

In view of the above problems, the embodiments of the present application enable self-alignment of the top die and the bottom die when the top die and the bottom die are close enough to each other by correspondingly disposing the bonding pads having the magnetic material on the surfaces of the top die and the bottom die, so that the alignment of the bonding of the semiconductor package structure is higher and the bonding process is more smooth. Furthermore, embodiments of the present application also provide a pick arm or bond head actuated by Bernoulli (Bernoulli) principles to pick and move the top die, so that the movement of the top die can have a greater degree of freedom both during alignment of the top die with the bottom die and before bonding of the top die with the bottom die. Therefore, the semiconductor packaging structure provided by the embodiment of the application can more easily, accurately and efficiently realize the alignment of the bonding pads of the top die and the bottom die, thereby having good product quality and higher production efficiency.

Fig. 1A is a schematic longitudinal cross-sectional view of a semiconductor package structure 10 according to an embodiment of the present application. Fig. 1B is a schematic bottom view of the first die in the semiconductor package structure 10 shown in fig. 1A. Fig. 1C is a schematic top view of an arrangement of a second die in the semiconductor package 10 shown in fig. 1A. Fig. 1D is a schematic top view of another arrangement of the second die in the semiconductor package 10 shown in fig. 1A.

As shown in fig. 1A, 1B, 1C and 1D, a semiconductor package structure 10 according to an embodiment of the present application may include: a first die 101, a second die 103, a first magnetic element 105, and a second magnetic element 107. The semiconductor package structure 10 has a width along the X-direction (i.e., horizontal direction), a thickness along the Y-direction (i.e., vertical direction), and a length along the Z-direction. Note that the term "die" herein may represent a chip or die.

The first die 101 has a first surface 101a and a second surface 101b opposite the first surface 101 a. The first die 101 may be any type of chip or die, such as, but not limited to, the first die 101 may be a memory, a processor, or an interdigital transducer, among others. The width of the first die 101 along the X direction may be, for example, but not limited to, about 2 mm to 10 mm, about 5 mm to 15 mm, about 15 mm to 20 mm. The length of the first die 101 along the Z direction may be, for example, but not limited to, about 2 mm to 10 mm, about 5 mm to 15 mm, about 15 mm to 20 mm.

The second die 103 has a first surface 103a and a second surface 103b opposite the first surface 103 a. Second surface 103b faces first surface 101a of first die 101. The second die 103 may be any type of chip or die, for example, but not limited to, the second die 103 may be a memory, a processor, or an interdigital transducer, among others. The width of the second die 103 along the X direction, the length along the Z direction, and the thickness along the Y direction may be the same or different than the first die 101.

The first magnetic element 105 may be disposed on the first surface 101a of the first die 101. In other embodiments of the present application, the first magnetic element 105 may be disposed on one of the first surface 101a of the first die 101 and the second surface 103b of the second die 103. The first magnetic element 105 may include a first set of conductive pads 105S. The first magnetic element 105 may include a first set of conductive pads 105S located above the first surface 101a of the first die 101 and including a magnetic material. The magnetic material included in the first set of conductive pads 105S may be, for example, but not limited to, an alloy of copper with a weight ratio greater than about 50% and a ferromagnetic material with a weight ratio less than about 50%. The ferromagnetic material may be a ferromagnetic material commonly used in the art, such as, but not limited to, iron, cobalt, or nickel.

The second magnetic elements 107 can be disposed at respective locations on the second surface 103b of the second die 103 that at least partially overlap the first magnetic elements 105. In other embodiments of the present application, the second magnetic element 107 may be disposed at a respective location of one of the first die 101 or the second die 103 and at least partially overlapping the first magnetic element 105. The second magnetic element 107 can include a second set of conductive pads 107S located above the second surface 103b of the second die 103 and including a magnetic material. The second set of conductive pads 107S may comprise a magnetic material such as, but not limited to, an alloy of copper in a weight ratio greater than about 50% and a ferromagnetic material in a weight ratio less than about 50%. The ferromagnetic material may be a ferromagnetic material commonly used in the art, such as, but not limited to, iron, cobalt, or nickel. The first set of pads 105S and the second set of pads 107S are bonded to each other. Because the first set of conductive pads 105S and the second set of conductive pads 107S each include a magnetic material, when they are sufficiently close to each other, the magnetic force between the first set of conductive pads 105S and the second set of conductive pads 107S will cause them to approach each other and eventually align with each other.

Referring now specifically to fig. 1B and 1C, the first set of conductive pads 105S may be ferromagnetic and the second set of conductive pads 107S may be correspondingly paramagnetic such that when the first set of conductive pads 105S and the second set of conductive pads 107S are brought into proximity, the second set of conductive pads 107S made of a paramagnetic material is magnetized by the first set of conductive pads 105S made of a ferromagnetic material such that the first set of conductive pads 105S and the second set of conductive pads 107S may be brought into proximity to enable self-alignment between the first set of conductive pads 105S and the second set of conductive pads 107S. In other embodiments of the present application, one of the first set of conductive pads 105S and the second set of conductive pads 107S can be a ferromagnetic material and the other of the first set of conductive pads 105S and the second set of conductive pads 107S can be a paramagnetic material.

Referring now specifically to fig. 1B and 1D, the first set of conductive pads 105S may have a first magnetic polarity and the second set of conductive pads 107S may correspondingly have a second magnetic polarity, the second magnetic polarity being opposite the first magnetic polarity, such that when the first set of conductive pads 105S and the second set of conductive pads 107S are brought into proximity with each other, the first set of conductive pads 105S and the second set of conductive pads 107S are capable of attracting each other to enable self-alignment between the first set of conductive pads 105S and the second set of conductive pads 107S. The first magnetic polarity may be a positive magnetic pole and the second magnetic polarity may be a negative magnetic pole. In other embodiments of the present application, one of the first set of conductive pads 105S and the second set of conductive pads 107S may have a first magnetic polarity and the other of the first set of conductive pads 105S and the second set of conductive pads 107S may have a second magnetic polarity.

Semiconductor package structure 10 may also include a third set of conductive pads 109S located over the first surface 101a of the first die 101 and a fourth set of conductive pads 111S located over the second surface 103b of the second die 103. The third set of pads 109S and the fourth set of pads 111S are bonded to each other. The third and fourth sets of

conductive pads

109S and 111S may not have magnetic properties and may be made of a commonly used bonding pad material, such as, but not limited to, copper. The third set of conductive pads 109S and the first set of conductive pads 105S have substantially the same thickness along the Y-direction. The fourth set of conductive pads 111S and the second set of conductive pads 107S have substantially the same thickness along the Y-direction. For the first die 101, a third set of conductive pads 109S may first be formed at the first surface 101a of the first die 101 using a Photoresist (Photoresist) etching process. Then, another step of the photoresist etching process may be performed to dispose the first magnetic component 105 including the first set of conductive pads 105S on the first surface 101a of the first die 101. Similarly, for the second die 103, a photoresist etch process may be used to first form a fourth set of conductive pads 111S on the second surface 103b of the second die 103. Next, another step of a photoresist etching process may be performed to dispose the second magnetic component 107 including the second set of conductive pads 107S on the second surface 103b of the second die 103. The first set of conductive pads 105S, the third set of conductive pads 109S, the second set of conductive pads 107S, and the fourth set of conductive pads 111S may also be formed using any suitable process in the art. In one embodiment, the first Magnetic element 105 and the second Magnetic element 107 may perform a Magnetic plating (Magnetic plating) operation to directionally align the Magnetic moment of the first Magnetic element 105 and the Magnetic moment of the second Magnetic element 107 when the plating is completed.

Referring now specifically to fig. 1B, 1C, and 1D, the first set of pads 105S and the third set of pads 109S may be uniformly distributed in a checkerboard pattern. The second set of pads 107S and the fourth set of pads 111S may be uniformly distributed in a checkerboard pattern and disposed corresponding to the first set of pads 105S and the third set of pads 109S, respectively. Pads with magnetic properties may not be adjacently disposed to prevent accuracy from being affected when aligning the first set of conductive pads 105S of the first die 101 and the second set of conductive pads 107S of the second die 103.

The semiconductor package structure 10 may also include a dielectric layer 113 surrounding the first set of conductive pads 105S, the second set of conductive pads 107S, the third set of conductive pads 109S, and the fourth set of conductive pads 111S. The material of the dielectric layer 113 may be a dielectric material commonly used in the art. Conventional bonding pressing and annealing processes may be performed to bond the pads of the first die 101 and the corresponding pads of the second die 103, and to cause the dielectric layer 113 to surround the first set of conductive pads 105S, the second set of conductive pads 107S, the third set of conductive pads 109S, and the fourth set of conductive pads 111S. Since the curie temperature of the ferromagnetic material including iron, nickel, and cobalt is greater than 500 degrees celsius, and the maximum temperature of the bonding pressing and annealing process is about 300 degrees celsius, the magnetic properties of the first and second sets of

conductive pads

105S and 107S are not affected after the bonding pressing and annealing process is performed, and the magnetic moments of the first and second sets of

conductive pads

105S and 107S are still directionally aligned in the final semiconductor package structure 10.

The embodiment of the application enables the dies needing to be bonded to each other to be automatically aligned due to magnetic force by arranging the conductive pads with the magnetic materials on the surfaces of the dies needing to be bonded to each other. Therefore, the semiconductor package structure provided by the embodiment of the application has higher precision of the alignment of the conductive pad. Therefore, the semiconductor packaging structure provided by the embodiment of the application has better packaging quality.

Fig. 2 is a schematic longitudinal cross-sectional view of a semiconductor package structure 10' according to another embodiment of the present application. The semiconductor package structure 10 'shown in fig. 2 differs from the semiconductor package structure 10 shown in fig. 1 in that the first set of conductive pads 105S and the second set of conductive pads 107S of the semiconductor package structure 10' shown in fig. 2 are in a multi-layer form.

In particular, each of the first set of conductive pads 105S includes a first magnetic layer 105a proximate to the first surface 101a of the first die 101 and a first bonding layer 105b distal to the first surface 101a of the first die 101. Each of the second set of conductive pads 107S includes a second magnetic layer 107b proximate the second surface 103b of the second die 103 and a second bonding layer 107a distal from the second surface 103b of the second die 103. The first bonding layer 105b and the second bonding layer 107a may comprise copper such that the material at the interface where the first die 101 and the second die 103 are bonded is copper to facilitate the bonding process. The first and second

magnetic layers

105a and 107b may include ferromagnetic materials. The ferromagnetic material may be a ferromagnetic material commonly used in the art, such as, but not limited to, iron, cobalt, or nickel. To form a magnetic domain, the first and second

magnetic layers

105a and 107b are required to have a thickness or more than 2 to 3 μm. In one embodiment, the first Magnetic layer 105a and the second Magnetic layer 107b may perform a Magnetic plating (Magnetic plating) operation to directionally align the Magnetic moment of the first Magnetic layer 105a and the Magnetic moment of the second Magnetic layer 107b when the plating is completed.

Fig. 3A is a schematic longitudinal cross-sectional view of a semiconductor package structure 20 according to yet another embodiment of the present application. Fig. 3B is a bottom view of the semiconductor package 20 of fig. 3A illustrating an arrangement of first dies. Fig. 3C is a schematic top view of the semiconductor package 20 of fig. 3A with a second die disposed thereon. Fig. 3D is a bottom view of another arrangement of the first die in the semiconductor package 20 shown in fig. 3A. Fig. 3E is a schematic top view of another arrangement of the second die in the semiconductor package 20 shown in fig. 3A.

As shown in fig. 3A, 3B, 3C, 3D and 3E, a semiconductor package structure 20 according to still another embodiment of the present application may include: a first die 201, a second die 203, a first magnetic element 205, and a second magnetic element 207. The semiconductor package structure 20 has a width along the X-direction (i.e., horizontal direction), a thickness along the Y-direction (i.e., vertical direction), and a length along the Z-direction. Note that the term "die" herein may represent a chip or die.

The first die 201 has a first surface 201a and a second surface 201b opposite the first surface 201 a. The first die 201 may be any type of chip or die, for example, but not limited to, the first die 201 may be a memory, a processor, or an interdigital transducer, among others. The width of the first die 201 along the X direction may be, for example, but not limited to, about 2 mm to 10 mm, about 5 mm to 15 mm, about 15 mm to 20 mm. The length of the first die 101 along the Z direction may be, for example, but not limited to, about 2 mm to 10 mm, about 5 mm to 15 mm, about 15 mm to 20 mm.

The second die 203 has a first surface 203a and a second surface 203b opposite the first surface 203 a. The second surface 203b faces the first surface 201a of the first die 201. The second die 203 may be any type of chip or die, for example, but not limited to, the second die 203 may be a memory, processor, or interdigital transducer, and the like. The width of the second die 203 along the X-direction, the length along the Z-direction, and the thickness along the Y-direction may be the same or different than the first die 201.

The first magnetic element 205 may be disposed on the first surface 201a of the first die 201. In other embodiments of the present application, the first magnetic element 205 can be disposed on one of the first surface 201a of the first die 201 and the second surface 203b of the second die 203. The first magnetic element 205 may include a first split line 205S at least partially deposited with a magnetic material. The magnetic material may be, for example, but not limited to, an alloy form having a weight ratio of greater than about 50% copper and a weight ratio of less than about 50% ferromagnetic material. The ferromagnetic material may be a ferromagnetic material commonly used in the art, such as, but not limited to, iron, cobalt, or nickel.

The second magnetic elements 207 may be disposed at respective locations of the second surface 203b of the second die 203 that at least partially overlap the first magnetic elements 205. In other embodiments of the present application, the second magnetic element 207 may be disposed at a respective location of one of the first die 201 or the second die 203 that at least partially overlaps the first magnetic element 205. The second magnetic element 207 may comprise a second dividing line 207S at least partially deposited with magnetic material. The magnetic material may be, for example, but not limited to, an alloy form having a weight ratio of greater than about 50% copper and a weight ratio of less than about 50% ferromagnetic material. The ferromagnetic material may be a ferromagnetic material commonly used in the art, such as, but not limited to, iron, cobalt, or nickel.

In other embodiments of the present application, the first dividing line 205S may be ferromagnetic and the second dividing line 207S may be correspondingly paramagnetic, such that when the first dividing line 205S and the second dividing line 207S are close to each other, the second dividing line 207S made of a paramagnetic material is magnetized by the first dividing line 205S made of a ferromagnetic material, so that the first dividing line 205S and the second dividing line 207S may be close to each other, such that self-alignment between the first dividing line 205S and the second dividing line 207S is enabled. In other embodiments of the present application, one of the first split line 205S and the second split line 207S may be a ferromagnetic material and the other of the first split line 205S and the second split line 207S may be a paramagnetic material.

The semiconductor package structure 20 may also include a first set of conductive pads 209S located above the first surface 201a of the first die 201 and a second set of conductive pads 211S located above the second surface 203b of the second die 203. The first set of pads 209S and the second set of pads 211S are bonded to each other. The first set of conductive pads 209S and the second set of conductive pads 211S may not be magnetic and may be made of common bonding pad materials, such as, but not limited to, copper. The first set of conductive pads 209S and the second set of conductive pads 211S may be formed using any suitable process in the art.

Referring now particularly to fig. 3B and 3C, first separation lines 205S may be disposed around the peripheral edges of the first dies 201, respectively, and second separation lines 207S may be disposed corresponding to the first separation lines 205S.

Referring now specifically to fig. 3D and 3E, first dividing lines 205S may be disposed around four right angles of the periphery of the first die 201, respectively, and second dividing lines 207S may be disposed corresponding to the first dividing lines 205S.

The semiconductor package structure 20 may also include a dielectric layer 213 surrounding the first set of conductive pads 209S and the second set of conductive pads 211S. The material of the dielectric layer 213 may be a dielectric material commonly used in the art. A conventional bonding press and anneal process may be performed such that the first set of conductive pads 209S of the first die 201 and the second set of conductive pads 211S of the second die 203 are bonded, and such that the dielectric layer 213 surrounds the first set of conductive pads 209S and the second set of conductive pads 211S. Since the curie temperature of the ferromagnetic material including iron, nickel, and cobalt is greater than 500 degrees celsius and the maximum temperature of the bonding pressing and annealing process is about 300 degrees celsius, the magnetism of the first and

second dividing lines

205S and 207S is not affected after the bonding pressing and annealing process is performed, and the magnetic moments of the first and

second dividing lines

205S and 207S are still directionally aligned in the final semiconductor package structure 20.

The embodiment of the application enables the dies needing to be bonded to each other to be automatically aligned due to magnetic force by arranging the separation line with the magnetic material on the surface of the dies needing to be bonded to each other. Therefore, the semiconductor package structure provided by the embodiment of the application has higher precision of the alignment of the conductive pad. Therefore, the semiconductor packaging structure provided by the embodiment of the application has better packaging quality.

Fig. 4 is a schematic longitudinal cross-sectional view of a semiconductor package structure 20' according to another embodiment of the present application. The semiconductor package 20 'shown in fig. 4 differs from the semiconductor package 20 shown in fig. 3A in that the first magnetic element 205 in the semiconductor package 20' shown in fig. 4 may include a first set of conductive pads 205X in addition to the first dividing line 205S at least partially deposited with the magnetic material. The first set of conductive pads 205X includes conductive pads containing magnetic material located above the first surface 201a of the first die 201, and the second magnetic element 207 may include a second set of conductive pads 207X including conductive pads containing magnetic material located above the first surface 201a of the first die 201, in addition to the second split line 207S at least partially deposited with magnetic material. The magnetic material may be, for example, but not limited to, an alloy form having a weight ratio of greater than about 50% copper and a weight ratio of less than about 50% ferromagnetic material. The ferromagnetic material may be a ferromagnetic material commonly used in the art, such as, but not limited to, iron, cobalt, or nickel. A dielectric layer 213 surrounds the first set of conductive pads 205X, the second set of conductive pads 207X, and the third and fourth sets of

conductive pads

209S and 211S. In an embodiment of the present application, the third set of conductive pads 209S and the fourth set of conductive pads 211S may not comprise ferromagnetic material.

Fig. 5A, 5B, 5C, and 5D are schematic flow diagrams of manufacturing a semiconductor package structure according to an embodiment of the present application, which can manufacture the semiconductor package structure 10 shown in fig. 1A.

As shown in fig. 5A, first die 101 is first provided. The first die 101 has a first surface 101a and a second surface 101b opposite the first surface 101 a. The first die 101 may be any type of chip or die, such as, but not limited to, the first die 101 may be a memory, a processor, or an interdigital transducer, among others. The width of the first die 101 along the X direction may be, for example, but not limited to, about 2 mm to 10 mm, about 5 mm to 15 mm, about 15 mm to 20 mm. The length of the first die 101 along the Z direction may be, for example, but not limited to, about 2 mm to 10 mm, about 5 mm to 15 mm, about 15 mm to 20 mm.

Next, a third set of conductive pads 109S may first be formed at the first surface 101a of the first die 101 using a Photoresist (Photoresist) etch process. The third set of conductive pads 109S may not have magnetic properties and may be made of a material commonly used for bond pads, such as, but not limited to, copper. Next, a first set of conductive pads 105S can be formed at the first surface 101a of the first die 101 using another step of a photoresist etch process. In other embodiments of the present application, magnetic material may also be deposited on the first dividing line 205S (not shown in fig. 5A) at this time.

The first set of conductive pads 105S may include conductive pads located above the first surface 101a of the first die 101 and comprising a magnetic material. The magnetic material included in the first set of conductive pads 105S may be, for example, but not limited to, an alloy of copper with a weight ratio greater than about 50% and a ferromagnetic material with a weight ratio less than about 50%. The ferromagnetic material may be a ferromagnetic material commonly used in the art, such as, but not limited to, iron, cobalt, or nickel. The third set of conductive pads 109S and the first set of conductive pads 105S have substantially the same thickness along the Y-direction.

Next, the pick arm 30 of a mechanism (not shown) actuated by the Bernoulli principle approaches the first die 101 from the second surface 101b of the first die 101. Since the pick arm 30 picks up the first die 101 by Bernoulli's principle, the second surface 101b of the first die 101 is not in direct contact with the pick arm 30, which enables the first die 101 to have a greater freedom of movement or rotation relative to vacuum suction of the first die 101 to facilitate easier alignment of the subsequent first die 101 and second die 103 with each other due to magnetic attraction.

The width of the pick arm 30 along the X direction may be, for example, but not limited to, about 2 mm to 10 mm, about 5 mm to 15 mm, about 15 mm to 20 mm. The length of the pick arm 30 along the Z direction may be, for example, but not limited to, about 2 mm to 10 mm, about 5 mm to 15 mm, about 15 mm to 20 mm. The width and length of pick arm 30 may be substantially the same as the width and length of first die 101, for example, but not limited to, about 10 millimeters each.

As shown in fig. 5B, a second die 103 is provided. The second die 103 has a first surface 103a and a second surface 103b opposite the first surface 103 a. Second surface 103b faces first surface 101a of first die 101. The second die 103 may be any type of chip or die, for example, but not limited to, the second die 103 may be a memory, a processor, or an interdigital transducer, among others. The width of the second die 103 along the X direction, the length along the Z direction, and the thickness along the Y direction may be the same or different than the first die 101.

Next, a photoresist etch process may be used to first form a fourth set of conductive pads 111S at the second surface 103b of the second die 103. The fourth set of conductive pads 111S may not have magnetic properties and may be made of a material commonly used for bonding pads, such as, but not limited to, copper. A second set of conductive pads 107S may be formed at the second surface 103b of the second die 103 using a photoresist etch process. In other embodiments of the present application, a magnetic material may also be deposited on the second dividing line 207S (not shown in fig. 5B).

Next, the pick arm 30 brings the first die 101 proximate to the temporarily fixed second die 103, and the first die 101 and the second die 103 are automatically aligned with a high degree of accuracy by the attraction of the first set of conductive pads 105S and the second set of conductive pads 107S to each other. In some embodiments of the present application, the high precision alignment formed by the magnetic conductive pad dimension as a self-alignment unit contributes to the quality of the subsequent hybrid bonded semiconductor package structure. In other embodiments of the present application, a vision assistance system may also be used to assist in alignment. When the pick arm is close enough to the second die 103, the mechanism actuated by the bernoulli principle will be turned off. The first die 101 will automatically fall on the second die 103 due to the magnetic force with the second die 103. As such, the first set of conductive pads 105S of the first die 101 and the second set of conductive pads 107S of the second die 103 are aligned, and the third set of conductive pads 109S of the first die 101 and the fourth set of conductive pads 111S of the second die 103 are aligned.

To improve production efficiency, a wafer having the same composition and configuration as the second die 103 may be provided, with the first set of conductive pads 105S of the first die 101 aligned with a second set of conductive pads 107S on the wafer corresponding to the first set of conductive pads 105S in the manner described above.

Next, as shown in fig. 5C, the pick arm 30 may be subjected to a conventional bonding pressing and annealing operation to bond the corresponding conductive pads and to cause a dielectric layer (not shown in fig. 5C) to surround the first set of conductive pads 105S, the second set of conductive pads 107S, the third set of conductive pads 109S and the fourth set of conductive pads 111S, thereby obtaining the semiconductor package structure 10 shown in fig. 1A. Since the curie temperature of the ferromagnetic material including iron and nickel is greater than 500 degrees celsius and the temperature of the bonding pressing and annealing operation is about 300 degrees celsius, after the bonding pressing and annealing operation is performed, the magnetic properties of the first and second sets of

conductive pads

105S and 107S are not affected, and the magnetic moments are still directionally aligned in the finally obtained semiconductor package structure 10.

The embodiment of the application enables the dies to be bonded to each other to be automatically aligned by magnetic force by arranging the conductive pads or the separation lines with the magnetic materials on the surfaces of the dies to be bonded to each other. At the same time, the die is picked up and moved by a mechanism actuated using the bernoulli principle, so that the die has a higher degree of freedom to facilitate alignment of the die. Therefore, the semiconductor packaging structure provided by the embodiment of the application can be manufactured more easily and more efficiently. Furthermore, since the dies required to be bonded to each other can be aligned by the mutually attractive magnetic materials, the semiconductor package structure provided by the embodiment of the application has higher accuracy in aligning the conductive pads. Therefore, the semiconductor packaging structure provided by the embodiment of the application has the advantages of better packaging quality, higher production efficiency and simple manufacturing process.

The technical content and technical features of the present application have been disclosed as above, however, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present application without departing from the spirit of the present application. Therefore, the protection scope of the present application should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the scope of the present application, which is encompassed by the claims of the present application.

Claims

1. A semiconductor package, comprising:

a first die having a first surface;

a second die bonded to the first die, the second die having a second surface facing the first surface;

a first magnetic element disposed on one of the first die or the second die; and

a second magnetic element disposed at a respective location of one of the first die or the second die and at least partially overlapping the first magnetic element.

2. The semiconductor package structure of claim 1, wherein the first magnetic element includes a first set of conductive pads located above the first surface of the first die and including a magnetic material, and the second magnetic element includes a second set of conductive pads located above the second surface of the second die and including a magnetic material, the first and second sets of conductive pads being bonded to each other.

3. The semiconductor package structure of claim 2, further comprising a third set of conductive pads located over the first surface and a fourth set of conductive pads located over the second surface, the third and fourth sets of conductive pads being bonded to each other.

4. The semiconductor package structure of claim 3, wherein the first set of conductive pads and the third set of conductive pads are uniformly distributed in a checkerboard pattern.

5. The semiconductor package structure of claim 2, wherein one of the first set of conductive pads or the second set of conductive pads is ferromagnetic and the other of the first set of conductive pads or the second set of conductive pads is paramagnetic.

6. The semiconductor package structure of claim 2, wherein one of the first set of conductive pads or the second set of conductive pads has a first magnetic polarity and the other of the first set of conductive pads or the second set of conductive pads has a second magnetic polarity.

7. The semiconductor package structure of claim 2, wherein each of the first set of conductive pads comprises a first magnetic layer proximate the first surface of the first die and each of the second set of conductive pads comprises a second magnetic layer proximate the second surface of the second die.

8. The semiconductor package structure of claim 7, wherein the first magnetic layer and the second magnetic layer comprise a ferromagnetic material.

9. The semiconductor package structure of claim 7, wherein each of the first set of conductive pads includes a first bonding layer distal from the first surface of the first die, and each of the second set of conductive pads includes a second bonding layer distal from the second surface of the second die, the first bonding layer being at least partially in contact with the second bonding layer.

10. The semiconductor package structure of any one of claims 2-9, further comprising a dielectric layer surrounding the first set of conductive pads and the second set of conductive pads.

11. The semiconductor package structure of claim 1, wherein the first magnetic element comprises a first split line at least partially deposited with a magnetic material, and the second magnetic element comprises a second split line at least partially deposited with a magnetic material.