CN214070226U

CN214070226U - Circuit board

Info

Publication number: CN214070226U
Application number: CN202022608717.8U
Authority: CN
Inventors: 魏兆璟; 吴沁玥; 李世川
Original assignee: Chipbond Technology Corp
Current assignee: Chipbond Technology Corp
Priority date: 2020-11-02
Filing date: 2020-11-12
Publication date: 2021-08-27
Anticipated expiration: 2030-11-12
Also published as: TWI732706B; CN114449730A; TW202220518A

Abstract

The utility model relates to a circuit board. The circuit board comprises a carrier plate, a circuit layer, a reinforcing layer, a flow choking piece and a protective layer, wherein the circuit layer, the reinforcing layer and the flow choking piece are arranged on the carrier plate, the reinforcing layer is provided with a containing groove, the flow choking piece is arranged in the containing groove, the protective layer covers the circuit layer and the reinforcing layer, and the flow choking piece is used for blocking the protective layer so as to prevent the protective layer from overflowing out of an allowable overflow boundary.

Description

Circuit board

Technical Field

The present invention relates to a circuit board, and more particularly to a circuit board having a reinforcing layer and a choke member disposed outside a wafer mounting area.

Background

Referring to fig. 1, a conventional circuit board 10 is provided with a chip-mounting area 11a and a circuit-mounting area 11b on a carrier 11, a first axis X extends along a first side 11c of the chip-mounting area 11a, a second axis Y extends along a second side 11d of the chip-mounting area 11a, and a blank area 11e is formed between the first axis X and the second axis Y.

Referring to fig. 1, a plurality of circuits 12 are disposed in the circuit disposing region 11b, and the circuits 12 and the blank region 11e are covered by a protection layer 13, in the prior art, a solder mask material with fluidity is printed on the circuit 12 and the blank region 11e by a screen printing technique to form the passivation layer 13, the passivation layer 13 exposes the inner lead 12a and the outer lead 12b of each of the wires 12, the inner leads 12a are disposed on the wafer mounting region 11a, the inner leads 12a are used for bonding a wafer, however, since the passivation layer 13 has fluidity before being cured, thereby causing the uncured protective layer 13 to overflow toward the chip mounting region 11a, the protective layer 13 overflowing toward the chip-mounting region 11a will affect the subsequent processes or cause the circuit board 10 to be out of specification.

Referring to fig. 1, since the blank area 11e is only covered by the protection layer 13, the blank area 11e will warp during the process of baking and curing the protection layer 13, or the blank area 11e will warp during the process of hot-pressing the circuit board 10 and the chip, which will not facilitate the alignment, bonding and cutting processes of the chip and the inner leads 12a when the blank area 11e warps.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a main objective sets up the strengthening layer and the choker that have the storage tank on the support plate, and this choker sets up in this storage tank, and this strengthening layer and this choker can avoid this support plate to take place the warpage, and this storage tank is used for holding uncured and excessive protective layer, and sets up this choker in this storage tank and can prevent to hold this protective layer overflow that is uncured in this storage tank and flow out and allow the overflow boundary.

The utility model relates to a circuit board, which comprises a carrier plate, a circuit layer, a reinforcing layer, a flow resisting piece and a protective layer, wherein the carrier plate is provided with a surface, the surface comprises a wafer setting area, a circuit setting area and a protective layer setting area, the wafer setting area is provided with a first boundary and a second boundary, the first boundary is connected with the second boundary at a corner, the circuit setting area and the protective layer setting area are positioned at the outer side of the wafer setting area, the protective layer setting area is partially overlapped with the circuit setting area, the protective layer setting area is provided with a third boundary, a fourth boundary and a corner boundary, two ends of the corner boundary are respectively connected with the third boundary and the fourth boundary, the third boundary corresponds to the first boundary, the fourth boundary corresponds to the second boundary, the corner boundary corresponds to the corner, an exposure area is arranged between the wafer setting area and the protective layer setting area, an allowable overflow boundary is defined between the corner boundary and the corner, a virtual axis passing through the corner, the overflow-allowable boundary and the corner boundary, the wiring layer being disposed in the wiring-disposing region, the circuit layer has a plurality of circuits, the inner leads of each circuit are located in the exposed region and the wafer setting region, the reinforcing layer is disposed in the passivation layer disposing region and the exposing region, the reinforcing layer has a receiving groove exposing the surface of the carrier, the strengthening layer is projected to the surface to form a strengthening layer projection area, the virtual axis passes through the strengthening layer projection area, the flow resisting piece is arranged in the containing groove, and the projection of the flow resisting piece to the surface forms a flow resisting piece projection area, the protective layer covers the circuit layer and the reinforcing layer, and the protective layer exposes the inner pin and the flow choking element in the accommodating groove, the flow blocking member is used for blocking the protection layer to prevent the protection layer from overflowing out of the allowable overflow boundary.

Preferably, wherein the spoiler projection area is located between the overflow-allowing boundary and the corner boundary.

Preferably, the spoiler projection has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the second side edge is located between the corner and the overflow-allowing boundary.

Preferably, the spoiler projection area has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the first side edge overlaps the overflow-allowing boundary.

Preferably, the spoiler projection area has a first side edge and a second side edge, the first side edge being located between the corner boundary and the second side edge, the second side edge overlapping the overflow-allowing boundary.

Preferably, the accommodating groove has a notch facing the wafer installation area, and the notch is located between the flow resisting element and the wafer installation area.

Preferably, wherein the virtual axis passes through the spoiler projection zone.

Preferably, wherein the virtual axis passes through the gap.

Preferably, the choke element has at least one blocking groove, and the blocking groove comprises at least one flow guiding opening facing the protective layer.

Preferably, the distance between the corner boundary and the overflow-allowing boundary is not more than 300 μm.

Preferably, the minimum distance between the outer sidewall of the choke piece and the inner sidewall of the receiving groove is not greater than 900 microns.

Preferably, the flow-blocking element is selected from various solid geometries.

The utility model discloses a region that is not equipped with this circuit layer sets up this strengthening layer and this choked flow piece, borrow by this strengthening layer and this choked flow piece increase the intensity that is not equipped with the region on this circuit layer, in order to avoid this support plate to take place the warpage, and borrow this storage tank by this strengthening layer and hold uncured and excessive this protective layer, and block this protective layer that is located this storage tank uncured with this choked flow piece that sets up in this storage tank, make this protective layer of uncured be detained in this storage tank, in order to avoid this protective layer overflow of uncured to flow out this allowable overflow border, in order to make this circuit board accord with the specification requirement, in order to facilitate follow-up wafer counterpoint joint and cutting the processing procedure.

Drawings

FIG. 1: a conventional circuit board is shown in a top view.

FIG. 2: the utility model discloses a top view of circuit board.

FIG. 3: the utility model discloses a cross-sectional view of circuit board.

FIG. 4: the utility model discloses a top view of strengthening layer and choked flow piece of circuit board.

FIG. 5: the utility model discloses a partial enlargement of an embodiment of circuit board.

FIG. 6: the utility model discloses a partial enlarged view of another embodiment of circuit board.

FIG. 7: the utility model discloses a top view of strengthening layer and choked flow piece of circuit board.

FIG. 8: the utility model discloses a top view of strengthening layer and choked flow piece of circuit board.

FIG. 9: the utility model discloses a top view of strengthening layer and choked flow piece of circuit board.

FIG. 10: the utility model discloses a top view of strengthening layer and choked flow piece of circuit board.

[ description of main element symbols ]

10: circuit board 11: carrier board

11a wafer setting region 11b a wiring setting region

11c first side 11d second side

11e blank area 12 line

12a inner lead 12b outer lead

13 protective layer 100 Circuit Board

110 carrier plate 111 surface

112a wafer-setting region 112a first boundary

112b, second boundary 112c, corner

113 a wiring setting region 114a protective layer setting region

114a, a third boundary 114b, a fourth boundary

114c corner boundary 115 show area

116 allowed overflow boundary 117 projection region of enhanced layer

118 spoiler projection area 118a first side edge

118b second side edge 120 line layer

121, line 122, inner pin

130 reinforcing layer 131 accommodating groove

131a inner side wall 132 gap

140 spoiler 141 outer sidewall

142a retarding groove 142a and a flow guide opening

150 protective layer L virtual axis

X is a first axis and Y is a second axis

Detailed Description

Referring to fig. 2 and fig. 3, a circuit board 100 of the present invention includes a carrier board 110, a circuit layer 120, a reinforcing layer 130, a choke element 140 and a protection layer 150, the carrier board 110 has a surface 111, the surface 111 includes a wafer setting area 112, a circuit setting area 113 and a protection layer setting area 114, the circuit setting area 113 and the protection layer setting area 114 are located outside the wafer setting area 112, in this embodiment, the circuit setting area 113 partially overlaps the wafer setting area 112, the protection layer setting area 114 partially overlaps the circuit setting area 113, and an exposed area 115 is located between the wafer setting area 112 and the protection layer setting area 114.

Referring to fig. 2, the wafer installation area 112 has a first boundary 112a and a second boundary 112b, the first boundary 112a connects the second boundary 112b to a corner 112c, the passivation layer installation area 114 has a third boundary 114a, a fourth boundary 114b and a corner boundary 114c, two ends of the corner boundary 114c connect the third boundary 114a and the fourth boundary 114b, the third boundary 114a corresponds to the first boundary 112a, the fourth boundary 114b corresponds to the second boundary 112b, the corner boundary 114c corresponds to the corner 112c, an overflow-allowing boundary 116 is defined between the corner boundary 114c and the corner 112c, a distance between the corner boundary 114c and the overflow-allowing boundary 116 is not more than 300 μm, and a virtual axis L passes through the corner 112c, the overflow-allowing boundary 116 and the corner boundary 114 c.

Referring to fig. 2 and 3, the circuit layer 120 is disposed in the circuit disposing region 113, the circuit layer 120 has a plurality of circuits 121, and the inner leads 122 of each circuit 121 are disposed in the exposed region 115 and the wafer disposing region 112.

Referring to fig. 2 and 4, the stiffening layer 130 is disposed in a region where the circuit layer 120 is not disposed, in the present embodiment, the stiffening layer 130 is disposed in the passivation layer disposing region 114 and the exposed region 115, the appearance of the stiffening layer 130 is selected from various solid geometries, the stiffening layer 130 has a receiving groove 131, the receiving groove 131 exposes the surface 111 of the carrier substrate 110, the stiffening layer 130 projects onto the surface 111 to form a stiffening layer projection region 117, the virtual axis L passes through the stiffening layer projection region 117, in the present embodiment, the receiving groove 131 has a gap 132, the gap 132 faces the wafer disposing region 112, the gap 132 is located between the choke element 140 and the wafer disposing region 112, and in the present embodiment, the virtual axis L passes through the gap 132.

Referring to fig. 2 and 4, the spoiler 140 is disposed in the accommodating groove 131, preferably, a minimum distance between an outer sidewall 141 of the spoiler 140 and an inner sidewall 131a of the accommodating groove 131 is not greater than 900 micrometers, and the spoiler 140 is projected onto the surface 111 to form a spoiler projection area 118, the spoiler projection area 118 is located between the overflow allowing boundary 116 and the corner boundary 114c, in one embodiment, the spoiler projection area 118 has a first side edge 118a and a second side edge 118b, the first side edge 118a is located between the corner boundary 114c and the second side edge 118b, the second side edge 118b is located between the corner 112c and the overflow allowing boundary 116, and in the embodiment, the virtual axis L passes through the spoiler projection area 118.

Referring to fig. 5, in another embodiment, similarly, the spoiler projection area 118 has the first side edge 118a and the second side edge 118b, the first side edge 118a is located between the corner boundary 114c and the second side edge 118b, the first side edge 118b overlaps the overflow allowing boundary 116, and in the present embodiment, the virtual axis L passes through the spoiler projection area 118.

Referring to fig. 6, in another embodiment, similarly, the spoiler projection area 118 has the first side edge 118a and the second side edge 118b, the first side edge 118a is located between the corner boundary 114c and the second side edge 118b, the second side edge 118b overlaps the overflow allowing boundary 116, and in the present embodiment, the virtual axis L passes through the spoiler projection area 118.

Referring to fig. 2, 3 and 4, the passivation layer 150 covers the circuit layer 120 and the reinforcing layer 130, and the passivation layer 150 exposes the inner leads 122 and the dam 140 located in the receiving groove 131. in the process of forming the passivation layer 150, the receiving groove 131 is used to receive the uncured and excessive passivation layer 150, and the dam 140 is used to stop the uncured passivation layer 150 to prevent the passivation layer 150 from overflowing the overflow-allowable boundary 116.

Referring to fig. 4 and 7 to 10, the spoiler 140 is selected from various solid geometries, and referring to fig. 7 to 10, preferably, the spoiler 140 has at least one retarding groove 142, the retarding groove 142 includes at least one flow guiding opening 142a, the flow guiding opening 142a faces the passivation layer 150, and the retarding groove 142 is used for accommodating the passivation layer 150 overflowing toward the wafer mounting region 112.

The utility model discloses borrow and increase the intensity that is not equipped with the region of this circuit layer 120 by setting up in this strengthening layer 130 and this choker 140 in the region that is not equipped with this circuit layer 120, in order to avoid this support plate 110 to take place the warpage, and borrow this storage tank 131 of this strengthening layer 130 to hold uncured and excessive this protective layer 150, and block a position overflow to this storage tank 131 and this protective layer 150 of uncured with this choker 140 that sets up in this storage tank 131, make this protective layer 150 of uncured be detained in this storage tank 131, in order to avoid this protective layer 150 of uncured overflow to flow out this permission overflow border 116, so that this circuit board 100 accords with the specification requirement, in order to carry out processes such as follow-up wafer counterpoint joint and cut.

The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above description, and although the present invention has been disclosed with the preferred embodiment, it is not limited to the present invention, and any skilled person in the art can make modifications or changes equivalent to the equivalent embodiment of the above embodiments without departing from the scope of the present invention, but all the modifications, changes and modifications of the above embodiments by the technical spirit of the present invention are within the scope of the present invention.

Claims

1. A circuit board, comprising:

a carrier having a surface including a chip mounting region, a circuit mounting region and a passivation layer mounting region, the chip setting area has a first boundary and a second boundary, the first boundary connects the second boundary to the corner, the circuit setting area and the protection layer setting area are located outside the chip setting area, and the protection layer setting area is partially overlapped with the circuit setting area, the protection layer setting region has a third boundary, a fourth boundary and a corner boundary, two ends of the corner boundary are connected to the third boundary and the fourth boundary respectively, the third boundary corresponds to the first boundary, the fourth boundary corresponds to the second boundary, the corner boundary corresponds to the corner, an exposed region is arranged between the chip setting region and the protection layer setting region, an overflow-allowable boundary is defined between the corner boundary and the corner, and a virtual axis passes through the corner, the overflow-allowable boundary and the corner boundary;

the circuit layer is arranged in the circuit arrangement area and provided with a plurality of circuits, and inner pins of the circuits are positioned in the exposure area and the wafer arrangement area;

the reinforcing layer is arranged in the protective layer arrangement area and the exposure area, the reinforcing layer is provided with a containing groove, the surface of the carrier plate is exposed by the containing groove, the reinforcing layer is projected to the surface to form a reinforcing layer projection area, and the virtual axis passes through the reinforcing layer projection area;

the flow choking piece is arranged in the accommodating groove, and the projection of the flow choking piece to the surface forms a flow choking piece projection area; and

the protective layer covers the circuit layer and the reinforcing layer, the inner pin and the flow choking piece located in the accommodating groove are exposed out of the protective layer, and the flow choking piece is used for blocking the protective layer so as to prevent the protective layer from overflowing out of the allowable overflow boundary.

2. The circuit board of claim 1, wherein the spoiler projection is located between the overflow allowance boundary and the corner boundary.

3. The circuit board of claim 1, wherein the spoiler projection area has a first side edge and a second side edge, the first side edge being located between the corner boundary and the second side edge, the second side edge being located between the corner and the overflow-allowing boundary.

4. The circuit board of claim 1, wherein the spoiler projection area has a first side edge and a second side edge, the first side edge being located between the corner boundary and the second side edge, the first side edge overlapping the overflow-allowing boundary.

5. The circuit board of claim 1, wherein the spoiler projection area has a first side edge and a second side edge, the first side edge being located between the corner boundary and the second side edge, the second side edge overlapping the overflow-allowing boundary.

6. The circuit board of any one of claims 1 to 5, wherein the receiving slot has a gap facing the wafer mounting region, the gap being located between the flow-resisting element and the wafer mounting region.

7. The circuit board of any one of claims 1 to 5, wherein the virtual axis passes through the spoiler projection area.

8. The circuit board of claim 6, wherein the virtual axis passes through the gap.

9. The circuit board of any one of claims 1 to 5, wherein the spoiler has at least one blocking groove comprising at least one flow guiding opening facing the protective layer.

10. The circuit board of any one of claims 1 to 5, wherein the spacing between the corner boundary and the overflow-tolerant boundary is no greater than 300 μm.

11. The circuit board of any one of claims 1 to 5, wherein a minimum distance between an outer sidewall of the choke element and an inner sidewall of the receiving groove is not greater than 900 μm.

12. The circuit board of any one of claims 1 to 5, wherein the flow-blocking element is selected from various solid geometries.