TWI732706B - Circuit board - Google Patents

Abstract

A circuit board includes a substrate, a circuit layer, a stiffening layer, a choke element and a protective layer. The circuit layer, the stiffening layer and the choke element are disposed on the substrate. The protective layer covers the circuit layer and the stiffening layer. The choke element is located in an accommodation notch of the stiffening layer to block the protective layer so as to stop the protective layer from flowing beyond a permitted margin of overflow.

Description

Circuit board

The invention relates to a circuit board, in particular to a circuit board provided with a reinforcing layer and a baffle on the outer side of a wafer setting area.

Please refer to FIG. 1, a conventional circuit board 10 has a chip arrangement area 11a and a circuit arrangement area 11b predetermined on a carrier board 11, and a first side 11c extends along a first side 11c of the chip arrangement area 11a. An axis X extends along a second side 11d of the wafer setting area 11a and a second axis Y, and a blank area 11e is formed between the first axis X and the second axis Y.

Please refer to Fig. 1, a plurality of lines 12 are arranged in the line setting area 11b, and a protective layer 13 covers the lines 12 and the blank area 11e. In the conventional technology, a screen printing technique is used to A fluid solder mask is printed on the circuits 12 and the blank area 11e to form the protective layer 13. The protective layer 13 also exposes an inner lead 12a and an outer lead 12b of each circuit 12, the The inner pins 12a are arranged in the chip setting area 11a, and the inner pins 12a are used to join a chip. However, since the protective layer 13 is still fluid before being cured, it will cause the protective layer to be uncured. 13 overflow in the direction of the wafer setting area 11a, and the protective layer 13 overflowing in the direction of the wafer setting area 11a will affect the subsequent manufacturing process, or cause the circuit board 10 to fail to meet the specification requirements.

Please refer to Figure 1. In addition, since the blank area 11e is only covered by the protective layer 13, a process of baking and curing the protective layer 13 will cause the blank area 11e to warp, or the blank area 11e may be warped during a hot pressing process. During the manufacturing process of the circuit board 10 and the chip, the blank area 11e will also be warped. When the blank area 11e is warped, it will be unfavorable for the chip and the inner leads 12a to align, bond, and cut. .

The main purpose of the present invention is to provide a reinforcing layer with an accommodating groove and a baffle on a carrier plate. The baffle is arranged in the accommodating groove, and the reinforcing layer and the baffle can avoid the The carrier board is warped, the accommodating groove is used for accommodating an uncured and excessive protective layer, and the baffle provided in the accommodating groove can prevent the uncured protective layer from being accommodated in the accommodating groove Overflow is an allowable overflow boundary.

A circuit board of the present invention includes a carrier, a circuit layer, a reinforcement layer, a baffle, and a protective layer. The carrier has a surface that includes a chip setting area, a circuit setting area, and a protection layer. Layer placement area, the wafer placement area has a first boundary and a second boundary, the first boundary connects the second boundary to a corner, the circuit placement area and the protective layer placement area are located outside the wafer placement area, and The protective layer setting area partially overlaps the line setting area. The protective layer setting area has a third boundary, a fourth boundary, and a corner boundary. Two ends of the corner boundary connect the third boundary and the fourth boundary, respectively , The third boundary corresponds to the first boundary, the fourth boundary corresponds to the second boundary, the corner boundary corresponds to a corner, and there is an exposed area between the wafer setting area and the protective layer setting area, and the corner boundary is An allowable overflow boundary is defined between the corners, and a virtual axis passes through the corner, the allowable overflow boundary and the corner boundary. The circuit layer is arranged in the circuit installation area, and the circuit layer has a plurality of circuits, each of which An inner pin of the circuit is located in the exposed area and the chip placement area, the reinforcing layer is placed in the protective layer placement area and the exposed area, the reinforcing layer has a accommodating groove, the accommodating groove reveals the carrier board On the surface, the reinforcement layer is projected onto the surface to form a reinforcement layer projection area, the virtual axis passes through the reinforcement layer projection area, the baffle is disposed in the accommodating groove, and the baffle is projected onto the surface to form a In the projection area of the baffle, the protective layer covers the circuit layer and the reinforcing layer, and the protective layer exposes the inner lead and the baffle in the accommodating groove, and the baffle is used to stop the The protective layer prevents the protective layer from overflowing the allowable overflow boundary.

The present invention is to provide the reinforcing layer and the baffle in the area where the circuit layer is not provided, and the reinforcement layer and the baffle increase the strength of the area where the circuit layer is not provided to avoid the occurrence of the carrier board. Warped, and the accommodating groove of the reinforcing layer accommodates the uncured and excessive protective layer, and the baffle arranged in the accommodating groove blocks the uncured protection in the accommodating groove Layer, so that the uncured protective layer stays in the accommodating groove to prevent the uncured protective layer from overflowing the permissible overflow boundary, so that the circuit board meets the specification requirements and facilitates subsequent wafer alignment bonding And cutting and other processes.

Referring to FIGS. 2 and 3, a circuit board 100 of the present invention includes a carrier 110, a circuit layer 120, a reinforcing layer 130, a baffle 140, and a protective layer 150. The carrier 110 has a surface 111 The surface 111 includes a wafer setting area 112, a circuit setting area 113, and a protection layer setting area 114. The circuit setting area 113 and the protection layer setting area 114 are located outside the wafer setting area 112. In this embodiment, The circuit arrangement area 113 and the wafer arrangement area 112 partially overlap, and the protection layer arrangement area 114 and the circuit arrangement area 113 partially overlap, and there is an exposed area 115 between the wafer arrangement area 112 and the protection layer arrangement area 114.

Referring to FIG. 2, the chip placement area 112 has a first boundary 112a and a second boundary 112b. The first boundary 112a connects the second boundary 112b to a corner 112c, and the protection layer placement area 114 has a third boundary. A boundary 114a, a fourth boundary 114b, and a corner boundary 114c. The two ends of the corner boundary 114c respectively connect the third boundary 114a and the fourth boundary 114b. The third boundary 114a corresponds to the first boundary 112a. The boundary 114b corresponds to the second boundary 112b, and the corner boundary 114c corresponds to the corner 112c. An allowable overflow boundary 116 is defined between the corner boundary 114c and the corner 112c. A distance between them is not greater than 300 microns, and a virtual axis L passes through the corner 112c, the allowable overflow boundary 116, and the corner boundary 114c.

Please refer to Figures 2 and 3, the circuit layer 120 is disposed in the circuit arrangement area 113, the circuit layer 120 has a plurality of circuits 121, and an inner pin 122 of each circuit 121 is located in the exposed area 115 and the chip arrangement area 112.

Please refer to Figures 2 and 4, the reinforcing layer 130 is disposed in an area where the circuit layer 120 is not provided. In this embodiment, the reinforcing layer 130 is disposed in the protective layer setting area 114 and the exposed area 115. The appearance of the layer 130 is selected from various three-dimensional geometric shapes. The reinforcing layer 130 has a receiving groove 131 that exposes the surface 111 of the carrier 110, and the reinforcing layer 130 is projected onto the surface 111 to form a Reinforcement layer projection area 117. The virtual axis L passes through the reinforcement layer projection area 117. In this embodiment, the accommodating groove 131 has a notch 132 facing the wafer setting area 112, and the notch 132 is located in the resistance Between the flow element 140 and the wafer setting area 112, in this embodiment, the virtual axis L passes through the gap 132.

Please refer to FIGS. 2 and 4, the baffle 140 is disposed in the accommodating groove 131. Preferably, the space between an outer side wall 141 of the baffle 140 and an inner side wall 131a of the accommodating groove 131 A minimum distance is not greater than 900 microns, and the baffle 140 is projected onto the surface 111 to form a baffle projection area 118, and the baffle projection area 118 is located between the allowable overflow boundary 116 and the corner boundary 114c, In one embodiment, the spoiler projection area 118 has a first side edge 118a and a second side edge 118b. The first side edge 118a is located between the corner boundary 114c and the second side edge 118b. The second side edge 118b is located between the corner 112c and the allowable overflow boundary 116. In this embodiment, the virtual axis L passes through the spoiler projection area 118.

Referring to FIG. 5, in another embodiment, similarly, the spoiler projection area 118 has the first side edge 118a and the second side edge 118b, and the first side edge 118a is located at the corner boundary 114c and Between the second side edges 118b, the first side edge 118b overlaps the allowable overflow boundary 116. In this embodiment, the virtual axis L passes through the spoiler projection area 118.

Please refer to FIG. 6, in another embodiment, similarly, the spoiler projection area 118 has the first side edge 118a and the second side edge 118b, and the first side edge 118a is located at the corner boundary 114c and Between the second side edges 118b, the second side edge 118b overlaps the allowable overflow boundary 116. In this embodiment, the virtual axis L passes through the spoiler projection area 118.

Please refer to FIGS. 2, 3, and 4, the protective layer 150 covers the circuit layer 120 and the reinforcing layer 130, and the protective layer 150 exposes the inner pin 122 and the blocking member located in the accommodating groove 131 140, in shape In the process of forming the protective layer 150, the accommodating groove 131 is used to contain the uncured and excessive amount of the protective layer 150, and the baffle member 140 is used to block the uncured protective layer 150 to avoid the protective layer 150. The overflow flows out of the allowable overflow boundary 116.

Please refer to Figures 4, 7 to 10, the baffle 140 is selected from various three-dimensional geometric shapes, please refer to Figures 7 to 10, preferably, the baffle 140 has at least one blocking groove 142, the The blocking groove 142 includes at least one diversion opening 142 a facing the protection layer 150, and the blocking groove 142 is used to accommodate the protection layer 150 overflowing toward the chip placement area 112.

The present invention increases the strength of the area where the circuit layer 120 is not provided by the reinforcing layer 130 and the baffle 140 provided in the area where the circuit layer 120 is not provided, so as to avoid warping of the carrier board 110, and The accommodating groove 131 of the reinforcing layer 130 accommodates the uncured and excess protective layer 150, and the baffle 140 arranged in the accommodating groove 131 prevents overflow into the accommodating groove 131 And the uncured protective layer 150 makes the uncured protective layer 150 stay in the accommodating groove 131 to prevent the uncured protective layer 150 from overflowing the allowable overflow boundary 116, so that the circuit board 100 Meet the specification requirements to facilitate subsequent wafer alignment bonding and cutting processes.

The scope of protection of the present invention shall be determined by the scope of the attached patent application. Anyone who is familiar with the art and makes any changes and modifications without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention. .

10: Circuit board

11: Carrier board

11a: Wafer setting area

11b: Line setting area

11c: first side

11d: second side

11e: blank area

12: Line

12a: inner pin

12b: External pin

13: protective layer

100: circuit board

110: carrier board

111: Surface

112: Wafer setting area

112a: first boundary

112b: second boundary

112c: corner

113: Route Setting Area

114: Protective layer setting area

114a: third boundary

114b: Fourth boundary

114c: corner border

115: Exposure Area

116: allowable overflow boundary

117: Reinforcement layer projection area

118: spoiler projection area

118a: first side edge

118b: second side edge

120: circuit layer

121: Line

122: inner pin

130: reinforcement layer

131: Containment Slot

131a: inner wall

132: Gap

140: spoiler

141: Outer wall

142: Blocking Groove

142a: Diversion opening

150: protective layer

L: virtual axis

X: first axis

Y: second axis

Figure 1: Top view of a conventional circuit board.

Figure 2: Top view of the circuit board of the present invention.

Figure 3: A cross-sectional view of the circuit board of the present invention.

Figure 4: The top view of the reinforcing layer and the baffle of the circuit board of the present invention.

Figure 5: A partial enlarged view of an embodiment of the circuit board of the present invention.

Figure 6: A partial enlarged view of another embodiment of the circuit board of the present invention.

Figure 7: The top view of the reinforcing layer and the baffle of the circuit board of the present invention.

Figure 8: The top view of the reinforcing layer and the baffle of the circuit board of the present invention.

Figure 9: The top view of the reinforcing layer and the baffle of the circuit board of the present invention.

Figure 10: The top view of the reinforcing layer and the baffle of the circuit board of the present invention.

100: circuit board

110: carrier board

112: Wafer setting area

112a: first boundary

112b: second boundary

112c: corner

113: Route Setting Area

114: Protective layer setting area

114a: third boundary

114b: Fourth boundary

114c: corner border

115: Exposure Area

116: allowable overflow boundary

117: Reinforcement layer projection area

118: spoiler projection area

118a: first side edge

118b: second side edge

120: circuit layer

121: Line

122: inner pin

130: reinforcement layer

131: Containment Slot

131a: inner wall

132: Gap

140: spoiler

150: protective layer

L: virtual axis

Claims (12)

A circuit board includes: a carrier board with a surface including a chip setting area, a circuit setting area, and a protective layer setting area. The chip setting area has a first boundary and a second boundary. A boundary connects the second boundary at a corner, the circuit setting area and the protection layer setting area are located outside the chip setting area, and the protection layer setting area partially overlaps the circuit setting area, and the protection layer setting area has a first Three borders, a fourth border and a corner border, the two ends of the corner border respectively connect the third border and the fourth border, the third border corresponds to the first border, and the fourth border corresponds to the second border, The corner boundary corresponds to the corner, and there is an exposed area between the chip placement area and the protective layer placement area. An allowable overflow boundary is defined between the corner boundary and the corner. A virtual axis passes through the corner and the corner. The overflow boundary and the corner boundary are allowed; a circuit layer is arranged in the circuit arrangement area, the circuit layer has a plurality of circuits, and an inner pin of each circuit is located in the exposed area and the chip arrangement area; a reinforcement layer, Is disposed in the protective layer setting area and the exposed area, the reinforcing layer has an accommodating groove, the accommodating groove reveals the surface of the carrier board, the reinforcing layer is projected onto the surface to form a reinforcing layer projection area, the virtual The axis passes through the projection area of the reinforcement layer; a baffle is arranged in the accommodating groove, and the baffle is projected onto the surface to form a projection area of the baffle; and a protective layer covering the circuit layer and the reinforcement The protective layer exposes the inner pin and the baffle in the containing groove, and the baffle is used to block the protective layer to prevent the protective layer from overflowing the allowable overflow boundary. Such as the circuit board of claim 1, wherein the baffle projection area is located between the allowable overflow boundary and the corner boundary. The circuit board of claim 1, wherein the projection area of the spoiler has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the second side The edge is located between the corner and the allowable overflow boundary. The circuit board of claim 1, wherein the projection area of the spoiler has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the first side The edge overlaps the allowable overflow boundary. The circuit board of claim 1, wherein the projection area of the spoiler has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the second side The edge overlaps the allowable overflow boundary. For example, the circuit board of any one of claims 1 to 5, wherein the accommodating groove has a notch, the notch faces the chip placement area, and the notch is located between the baffle and the chip placement area. Such as the circuit board of any one of claims 1 to 5, wherein the virtual axis passes through the spoiler projection area. Such as the circuit board of claim 6, wherein the virtual axis passes through the gap. The circuit board according to any one of claims 1 to 5, wherein the blocking member has at least one blocking groove, the blocking groove includes at least one diversion opening, and the diversion opening faces the protective layer. The circuit board according to any one of claims 1 to 5, wherein a distance between the corner boundary and the allowable overflow boundary is not greater than 300 micrometers. The circuit board of any one of claims 1 to 5, wherein a minimum distance between an outer side wall of the baffle member and an inner side wall of the accommodating groove is not greater than 900 microns. The circuit board according to any one of claims 1 to 5, wherein the baffle member is selected from various three-dimensional geometric shapes.

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