CN214043684U

CN214043684U - Back contact battery

Info

Publication number: CN214043684U
Application number: CN202023280509.6U
Authority: CN
Inventors: 安欣睿; 沈雯; 张临安; 邓伟伟
Original assignee: CSI Cells Co Ltd; Atlas Sunshine Power Group Co Ltd
Current assignee: Canadian Solar Inc; CSI Cells Co Ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2021-08-24
Anticipated expiration: 2030-12-30

Abstract

The application provides a back contact cell, which comprises a silicon substrate, wherein the silicon substrate is provided with a first area and a second area which are adjacent, and a first doped layer is formed on the back surface of the first area; the back contact cell further comprises a doped polycrystalline silicon layer, wherein the doped polycrystalline silicon layer is covered on the back surface of the second region and the first doped layer, and the doping type of the doped polycrystalline silicon layer is opposite to that of the first doped layer. The back contact cell is characterized in that the whole doped polycrystalline silicon layer is arranged on the back surface of the silicon substrate, the doped polycrystalline silicon layer is used for simultaneously realizing the collection and transmission of different current carriers, the electrical isolation design of the back surface of the silicon substrate is not needed, the cell structure and the process are more concise, and the industrialized implementation and popularization are facilitated.

Description

Back contact battery

Technical Field

The application relates to the technical field of solar power generation, in particular to a back contact battery.

Background

With the rapid development of the photovoltaic industry, the requirements of domestic and foreign markets on the efficiency and performance of solar cells are higher and higher, which also promotes a plurality of manufacturers to actively research novel cell structures and production processes so as to obtain industrial advantages. The Interdigitated Back Contact (IBC) cell is a solar cell in which P and N regions are arranged in a cross manner on the back surface of the cell, and can thoroughly avoid optical loss caused by shielding of a front electrode grid line, maximally utilize incident light, and improve short-circuit current.

With the increasing lifetime of silicon substrate materials and passivation level of battery surface, the structural design of the IBC battery has received more and more attention in the industry. Generally, a mask method is adopted for the IBC cell to precisely align and prepare films of different doping types on the back surface of a silicon substrate, and currently, a relatively complicated process is the biggest problem that the industrial application and popularization of the IBC cell are limited.

In view of the above, there is a need for a new back contact battery.

SUMMERY OF THE UTILITY MODEL

The back contact battery is simple in structure, can effectively overcome the electric leakage abnormity between doped layers of different types, and improves the battery performance.

In order to achieve the above object, the present application provides a back contact cell, including a silicon substrate having a first region and a second region adjacent to each other, a first doped layer formed on a back surface of the first region; the back contact cell further comprises a doped polycrystalline silicon layer, wherein the doped polycrystalline silicon layer is covered on the back surface of the second region and the first doped layer, and the doping type of the doped polycrystalline silicon layer is opposite to that of the first doped layer.

As a further improvement of the embodiment of the application, the thickness of the doped polycrystalline silicon layer is set to be 10-50 nm.

As a further improvement of the embodiment of the application, the sheet resistance of the doped polysilicon layer is set to be 1000-10000 ohm/sq.

As a further improvement of the embodiment of the present application, the back contact cell further includes a back passivation layer disposed on a back surface of the doped polysilicon layer, and a first electrode and a second electrode penetrating through the back passivation layer and contacting the doped polysilicon layer; the first electrode is arranged on the back of the first area, and the second electrode is arranged on the back of the second area.

As a further improvement of the embodiment of the application, the distance between the boundary position of the first region and the second region and the first electrode is set to be 50-200 μm.

As a further improvement of the embodiment of the application, the first electrode includes a plurality of first finger-shaped gate lines, the second electrode includes a plurality of second finger-shaped gate lines, the first finger-shaped gate lines and the second finger-shaped gate lines are alternately arranged in sequence, and the width of the first finger-shaped gate lines is set to be between 0.1 mm and 0.5 mm.

As a further improvement of the embodiment of the present application, a coverage area of the first electrode is set smaller than a coverage area of the second electrode.

As a further improvement of the embodiment of the present application, the back contact cell further includes a tunneling layer disposed between the doped polysilicon layer and the silicon substrate.

As a further improvement of the embodiment of the application, the thickness of the tunneling layer is set to be 0.5-3 nm.

As a further improvement of the embodiment of the application, the silicon substrate is an N-type silicon wafer, and the resistivity of the silicon substrate is set to be 0.3-7 omega-cm; the doped polycrystalline silicon layer is a P-type doped polycrystalline silicon layer.

The beneficial effect of this application is: adopt this application back of body contact battery, through silicon substrate back sets up the doping polycrystalline silicon layer of whole face formula, the doping polycrystalline silicon layer can regard as the transmission layer of the first current carrier that first doping layer collected, also can realize the collection and the transmission of second current carrier simultaneously, need not to carry out the electrical isolation design, and battery structure and technology are more succinct, do benefit to implementation and popularization.

Drawings

FIG. 1 is a schematic structural diagram of a preferred embodiment of a back contact cell of the present application;

fig. 2 is a schematic view of a back side partial structure of a back contact cell of the present application;

fig. 3 is a schematic structural diagram of another preferred embodiment of the back contact cell of the present application.

100-back contact cell; 1-a silicon substrate; 11-a first doped layer; 12-a front surface field layer; 2-doping a polysilicon layer; 3-back passivation layer; 4-an anti-reflection layer; 51-a first electrode; 52-a second electrode; 510-a first finger gate line; 520-a second finger gate line; 6-tunneling layer.

Detailed Description

The present application will be described in detail below with reference to embodiments shown in the drawings. The present invention is not limited to the above embodiments, and structural, methodological, or functional changes made by one of ordinary skill in the art according to the present embodiments are included in the scope of the present invention.

Referring to fig. 1, a back contact cell 100 provided in the present application includes a silicon substrate 1, where the silicon substrate 1 has a first region and a second region adjacent to each other, and a first doped layer 11 is formed on a back surface of the first region. The first doping layer 11 is a local heavily doped layer formed on the back surface of the silicon substrate 1 to achieve better carrier collection and transmission effects, and the doping type of the first doping layer is consistent with that of the silicon substrate 1. The back contact cell 100 further comprises a doped polysilicon layer 2 arranged on the back surface of the silicon substrate 1, wherein the doped polysilicon layer 2 is designed in a whole surface manner, namely the doped polysilicon layer 2 covers the back surface of the second region and the first doped layer 11, and the doping type of the doped polysilicon layer 2 is opposite to that of the first doped layer 11.

In the embodiment, the silicon substrate 1 is an N-type silicon wafer, the resistivity of the silicon substrate 1 is set to be 0.3-7 omega-cm, and the thickness of the silicon wafer is 50-300 mu m; the first doped layer 11 is an N-type doped layer, and the doped polysilicon layer 2 is a P-type doped polysilicon layer. The front surface of the silicon substrate 1 is further formed with a front surface field layer 12, and the front surface field layer 12 is used for improving the front surface passivation performance. Here, the first doping layer 11 and the front surface field layer 12 are both phosphorus doping layers; the second doped layer 12 is a boron-doped polysilicon layer.

The doped polysilicon layer 2 can be used as a transmission layer of the first carriers collected by the first doped layer 11, and can also realize the collection and transmission of the second carriers. In order to achieve the above purpose, the film structure, thickness and doping concentration of the doped polysilicon layer 2 need to be adjusted correspondingly, where the doping concentration of the doped polysilicon layer 2 is relatively small, and the sheet resistance thereof is controlled to be 1000-10000 ohm/sq, so as to avoid the lateral transmission of carriers; the thickness of the doped polysilicon layer 2 is preferably 10 to 50nm, for example, the thickness of the doped polysilicon layer 2 is 10nm, 15nm, 30nm, or the like.

The back contact cell 100 further includes a back passivation layer 3 disposed on the back surface of the doped polysilicon layer 2 and an anti-reflection layer 4 disposed on the front surface of the silicon substrate 1. The back passivation layer 3 comprises at least one of an aluminum oxide film, a silicon nitride film and a silicon carbide film; the antireflection layer 4 can be a silicon nitride film, and the thickness is set to be 70-100 nm. The back passivation layer 3 and the antireflection layer 4 can be adjusted by technological parameters such as gas flow, reaction time, temperature and the like, so that the film performance and the antireflection effect of the antireflection layer 4 are improved; moreover, the back passivation layer 3 and the antireflection layer 4 may be configured in a stacked film or a graded film structure according to actual requirements, which is not described in detail herein.

The back contact cell 100 further comprises a first electrode 51 and a second electrode 52 penetrating through the back passivation layer 3 and contacting the doped polysilicon layer 2, wherein the first electrode 51 is correspondingly disposed on the back surface of the first region, and the second electrode 52 is correspondingly disposed on the back surface of the second region. The first electrode 51 and the second electrode 52 are obtained by screen printing and sintering a predetermined conductive paste.

Since the sheet resistance of the doped polysilicon layer 2 is large and the lateral current conduction capability is weak, the coverage area of the first electrode 51 and the second electrode 52 is also set to be large, so as to fully realize the effective collection of carriers. Referring to fig. 2, the first region and the second region respectively have a plurality of strip regions (indicated by dotted lines in fig. 2) alternately arranged in sequence, and the overall width L of each adjacent strip region is set to be 0.5-2 mm. Here, the area ratio of the first region is preferably set larger than that of the second region. The first electrode 51 includes a plurality of first finger-shaped gate lines 510, the second electrode 52 includes a plurality of second finger-shaped gate lines 520, the first finger-shaped gate lines 510 and the second finger-shaped gate lines 520 are disposed at corresponding stripe regions and are alternately arranged in sequence, the width of the first finger-shaped gate lines 510 is set to be 0.1-0.5 mm, and the width of the first finger-shaped gate lines 510 is generally greater than that of the second finger-shaped gate lines 520. In order to realize the effective collection of the carriers in the first region, the distance d between the boundary position of the first region and the second region and the first electrode 51 is set to be 50-200 μm. As an example, the width of the first finger gate line 510 may be set to 150 μm, 200 μm, 300 μm, 400 μm, 500 μm; the aforementioned distance d may be set to 50 μm, 100 μm, 150 μm, 200 μm.

The preparation process of the back contact battery 100 mainly comprises the following steps: firstly, carrying out surface treatment on a silicon substrate 1, and then diffusing local areas (the back of a first area) on the front surface and the back surface of the silicon substrate 1 to form a first doping layer 11 and a front surface field layer 12; depositing and preparing a doped polycrystalline silicon layer 2 on the back surface of the silicon substrate 1, wherein the doped polycrystalline silicon layer 2 can be deposited by an LPCVD method or an HWCVD method generally; then, a back passivation layer 3 and an anti-reflection layer 4 are formed on the two side surfaces of the silicon substrate 1 by film plating, a predetermined conductive paste is printed on the surface of the back passivation layer 3, and a first electrode 51 and a second electrode 52 burning through the back passivation layer 3 are obtained by sintering. According to the product requirement, the conductive pastes used for the first electrode 51 and the second electrode 52 may be the same or different, and are not described in detail here.

Fig. 3 shows another embodiment of the present application, which is different from the previous embodiment in that: the back contact cell 100 further comprises a tunneling layer 6 disposed between the doped polysilicon layer 2 and the silicon substrate 1. The tunneling layer 6 can be generally configured as a silicon oxide film or a silicon oxynitride film, and the thickness of the tunneling layer 6 is set to be 0.5-3 nm.

In addition, since the coverage area of the first electrode 51 and the second electrode 52 is set to be large, a layer of transparent conductive oxide (not shown) may be disposed on the back surface of the first region and/or the second region to reduce recombination loss. In other words, the first electrode 51 and/or the second electrode 52 may also be provided as a stacked structure of a transparent conductive oxide and a metal.

This application back contact battery 100 is through silicon substrate 1 back sets up whole face formula doping polycrystalline silicon layer 2, doping polycrystalline silicon layer 2 can regard as the transmission layer of the first current carrier that first doping layer 11 was collected, also can realize the collection and the transmission of second current carrier simultaneously, need not to carry out the electrical isolation design, and battery structure and technology are more succinct, do benefit to the industry and implement and promote.

It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.

The above list of details is only for the concrete description of the feasible embodiments of the present application, they are not intended to limit the scope of the present application, and all equivalent embodiments or modifications that do not depart from the technical spirit of the present application are intended to be included within the scope of the present application.

Claims

1. A back contact cell comprising a silicon substrate having adjacent first and second regions, wherein: a first doping layer is formed on the back surface of the first region; the back contact cell further comprises a doped polycrystalline silicon layer, wherein the doped polycrystalline silicon layer is covered on the back surface of the second region and the first doped layer, and the doping type of the doped polycrystalline silicon layer is opposite to that of the first doped layer.

2. The back contact battery of claim 1, wherein: the thickness of the doped polycrystalline silicon layer is set to be 10-50 nm.

3. The back contact battery of claim 1, wherein: the sheet resistance of the doped polycrystalline silicon layer is set to be 1000-10000 ohm/sq.

4. The back contact battery of claim 1, wherein: the back contact cell also comprises a back passivation layer arranged on the back surface of the doped polycrystalline silicon layer, and a first electrode and a second electrode which penetrate through the back passivation layer and are in contact with the doped polycrystalline silicon layer; the first electrode is arranged on the back of the first area, and the second electrode is arranged on the back of the second area.

5. The back contact battery of claim 4, wherein: the distance between the boundary position of the first region and the second region and the first electrode is set to be 50-200 μm.

6. The back contact battery of claim 4 or 5, wherein: the first electrode comprises a plurality of first finger-shaped grid lines, the second electrode comprises a plurality of second finger-shaped grid lines, the first finger-shaped grid lines and the second finger-shaped grid lines are sequentially and alternately arranged, and the width of each first finger-shaped grid line is set to be 0.1-0.5 mm.

7. The back contact battery of claim 4, wherein: the coverage area of the first electrode is smaller than that of the second electrode.

8. The back contact battery of claim 1, wherein: the back contact cell also includes a tunneling layer disposed between the doped polysilicon layer and the silicon substrate.

9. The back contact battery of claim 8, wherein: the thickness of the tunneling layer is set to be 0.5-3 nm.

10. The back contact battery of claim 1, wherein: the silicon substrate is an N-type silicon wafer, and the resistivity of the silicon substrate is set to be 0.3-7 omega cm; the doped polycrystalline silicon layer is a P-type doped polycrystalline silicon layer.