CN213991159U - Spliced circuit board structure - Google Patents

Abstract

The embodiment of the application provides a spliced circuit board structure, which comprises a first spliced board and a second spliced board, wherein the first spliced board comprises a first single board and a second single board which are arranged side by side, the first single board comprises a first edge area which is positioned on one side of the board, which is far away from the second single board, the second single board comprises a second edge area, the first edge area is a component distribution forbidding area, and the first edge area and the second edge area are in central symmetry or mirror symmetry relative to the center of the first spliced board; the second jointed board comprises a third single board and a fourth single board, the third single board is jointed with the first single board and the fourth single board and comprises a third edge area, the fourth single board is jointed with the third single board and the second single board and comprises a fourth edge area, the first edge area and the fourth edge area are centrosymmetric, and the second edge area and the third edge area are centrosymmetric. The spliced circuit board structure provided by the embodiment of the application can utilize the edge area in the board as the clamping edge, thereby saving the process edge, improving the utilization rate of the board and reducing the cost.

Description

Spliced circuit board structure

Technical Field

The application relates to the technical field of circuit boards, in particular to a spliced circuit board structure.

Background

A Printed Circuit Board (PCB) jointed Board refers to a Board produced by the electronic manufacturing industry, which is designed to be a multi-connection Board, i.e. a jointed Board, by splicing PCB single boards when producing small-sized Circuit boards, so as to be suitable for mass production, save cost, improve production efficiency, and the like. In the related art, a process edge is added to two sides or four sides of the whole jointed board when the PCB jointed board is designed, and SMT (Surface mount Technology) equipment fixes the PCB jointed board for reflow by clamping the process edge when the board is Mounted. However, the width of the process edge is greater than a certain value to meet the clamping requirement of the SMT equipment, and at least one process edge needs to be designed on each of the two sides of the jointed board, so that the utilization rate of the PCB board is low, the board is wasted, and the manufacturing cost of the circuit board is increased.

SUMMERY OF THE UTILITY MODEL

An object of the present application is to provide a spliced circuit board structure to solve the above-mentioned problems. The present application achieves the above object by the following technical solutions.

The embodiment of the application provides a spliced circuit board structure, which comprises a first spliced board and a second spliced board, wherein the first spliced board comprises a first single board and a second single board which are arranged side by side, the first single board comprises a first edge area, the first edge area is positioned on one side, deviating from the second single board, in the first single board, the second single board comprises a second edge area, the first edge area is a component layout forbidding area, and the first edge area and the second edge area are arranged in a central symmetry or mirror symmetry mode about the center of the first spliced board; the second jointed board comprises a third veneer and a fourth veneer, the third veneer is jointed with the first veneer and the fourth veneer, the third veneer comprises a third edge area, the fourth veneer is jointed with the third veneer and the second veneer, the fourth veneer comprises a fourth edge area, the first edge area and the fourth edge area are arranged in a central symmetry mode about the center of the jointed circuit board structure, and the second edge area and the third edge area are arranged in a central symmetry mode about the center of the jointed circuit board structure.

Compared with the prior art, the spliced circuit board structure provided by the embodiment of the application can utilize the first edge area and the third edge area which are positioned on the same side as clamping edges for patch processing, and utilize the second edge area and the fourth edge area which are positioned on the same side as another clamping edge for patch processing, so that a process edge is saved, the utilization rate of a board is improved, and the processing and manufacturing cost of the circuit board is reduced; meanwhile, the first edge area, the second edge area, the third edge area and the fourth edge area are the same in structure, and processing and manufacturing are facilitated.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a tiled circuit board structure provided in an embodiment of the present application.

Fig. 2 is another schematic structural diagram of the tiled circuit board structure provided in the embodiment shown in fig. 1.

Fig. 3 is a schematic structural diagram of a tiled circuit board structure according to another embodiment of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.

The printed circuit board can be respectively processed with a technical edge at two sides or the periphery of the whole jointed board when the board is jointed, and the SMT equipment clamps the technical edges to carry out reflux when the board is pasted. The width of the process edge is typically required to be greater than or equal to 5mm to meet the clamping requirements of the SMT equipment, which reduces the available area of the printed circuit board, resulting in increased manufacturing costs. In the related art, a smelting tool reflow process is adopted for carrying out surface mounting on the printed circuit board, and a process edge can be omitted, but certain conditions are required for the use of the smelting tool reflow, the cost is high, and the use is limited. In order to solve this problem, the inventors have studied and proposed a tiled circuit board structure in the embodiment of the present application.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, a tiled circuit board structure 100 provided in the embodiment of the present application includes a first tiled board 110 and a second tiled board 120, where the first tiled board 110 includes a first single board 130 and a second single board 140 that are arranged side by side, the first single board 130 includes a first edge region 131, the first edge region 131 is located on a side of the first single board 130 that faces away from the second single board 140, the second single board 140 includes a second edge region 141, the second edge region 141 is located on a side of the second single board 140 that faces away from the first single board 130, the first edge region 131 is a device layout prohibition region, and the first edge region 131 and the second edge region 141 are arranged in a central symmetry or mirror symmetry with respect to a center (e.g., point a) of the first tiled board 110. As can be seen from the symmetrical relationship, the second edge region 141 and the first edge region 131 have the same structure and are also device layout prohibition regions.

The second jointed board 120 includes a third board 150 and a fourth board 160, the third board 150 is jointed with the first board 130 and the fourth board 160, the third board 150 includes a third edge region 151, the fourth board 160 is jointed with the third board 150 and the second board 140, and the fourth board 160 includes a fourth edge region 161, the first edge region 131 and the fourth edge region 161 are arranged in a central symmetry manner with respect to the center (for example, point C) of the jointed circuit board structure 100, and the second edge region 141 and the third edge region 151 are arranged in a central symmetry manner with respect to the center (for example, point C) of the jointed circuit board structure 100.

As can be seen from the symmetrical relationship, the third edge region 151 and the fourth edge region 161 are regions where devices are forbidden to be arranged, the third edge region 151 is located on one side of the third single board 150 that is away from the fourth single board 160, the fourth edge region 161 is located on one side of the fourth single board 160 that is away from the third single board 150, so that the first edge region 131 and the third edge region 151 are located on one side of the tiled circuit board structure 100, and the second edge region 141 and the fourth edge region 161 are located on the other side of the tiled circuit board structure 100.

In this embodiment, the component distribution prohibiting region is an un-mounted region, which can avoid interference with the SMT equipment during mounting processing, so that the first edge region 131, the second edge region 141, the third edge region 151, and the fourth edge region 161 can all be used as edge clamping regions of the SMT equipment.

The tiled circuit board structure 100 can use the first edge region 131 and the third edge region 151 located on the same side as a clamping edge of the SMT equipment during the chip mounting process, and use the second edge region 141 and the fourth edge region 161 located on the same side as another clamping edge during the chip mounting process, thereby saving a process edge, improving the board utilization rate, and reducing the manufacturing cost of the circuit board. And because of the symmetrical relation, the structures of all the edge areas are the same, and the processing and the manufacturing are convenient.

Referring to FIG. 2, the first edge region 131 and the second edge region 141 can be disposed in a central symmetry with respect to the center (e.g., point A) of the first panel 110. From the symmetry, the third edge region 151 and the fourth edge region 161 are disposed in central symmetry with respect to the center (e.g., point B) of the second panel 120. The central symmetrical jointed board can be suitable for two circuit boards with relatively irregular shapes, and the shapes of the jointed boards become regular.

The first board 130 may further include a first mounting region 132, the first mounting region 132 is connected to the first edge region 131, the second board 140 further includes a second mounting region 142, the second mounting region 142 is connected to the second edge region 141 and is spliced with the first mounting region 132, and the first mounting region 132 and the second mounting region 142 are arranged in a central symmetry manner with respect to a center (e.g., point a) of the first jointed board 110.

Correspondingly, the third board 150 further includes a third mounting region 152, the third mounting region 152 is connected to the third edge region 151, the fourth board 160 further includes a fourth mounting region 162, the fourth mounting region 162 is connected to the fourth edge region 161 and is spliced with the third mounting region 152, the third mounting region 152 and the fourth mounting region 162 are arranged in a central symmetry manner with respect to the center (for example, point B) of the second board 120, and the first mounting region 132 and the fourth mounting region 162 are arranged in a central symmetry manner with respect to the center (for example, point C) of the tiled circuit board structure 100. The mounting area and the edge area are both parts in the single plate, and the mounting area and the edge area form the whole plate surface of the single plate.

Therefore, the structural design (including the edge area and the mounting area) of the first single board 130, the second single board 140, the third single board 150 and the fourth single board 160 can be completely the same, which facilitates the manufacturing process.

Referring to FIG. 3, in some embodiments, first edge region 131 and second edge region 141 are mirror images of the center (e.g., point A) of first panel 110. From the symmetry, third edge region 151 and fourth edge region 161 are mirror images of the center (e.g., point B) of second panel 120.

The first edge region 131 may be located on the TOP surface of the first single board 130, the second edge region 141 may be located on the bottom surface of the second single board 140, the third edge region 151 may be located on the bottom surface of the third single board 150, and the fourth edge region 161 may be located on the TOP surface of the fourth single board 160. The mirror-symmetrical panel arrangement (male-female) can also be such that the first edge region 131 and the third edge region 151 are located on one side of the tiled circuit board structure 100, and the second edge region 141 and the fourth edge region 161 are located on the other side of the tiled circuit board structure 100. When the circuit board has mounted components on both sides, a mirror symmetry splicing mode can be adopted.

The first board 130 may further include a first mounting region 132, the first mounting region 132 is connected to the first edge region 131, the second board 140 further includes a second mounting region 142, the second mounting region 142 is connected to the second edge region 141 and is spliced with the first mounting region 132, and the first mounting region 132 and the second mounting region 142 are arranged in mirror symmetry with respect to a center (e.g., point a) of the first jointed board 110.

The third board 150 may further include a third mounting region 152, the third mounting region 152 is connected to the third edge region 151, the fourth board 160 further includes a fourth mounting region 162, the fourth mounting region 162 is connected to the fourth edge region 161 and is relatively spliced with the third mounting region 152, and the third mounting region 152 and the fourth mounting region 162 are arranged in mirror symmetry with respect to the center (e.g., point B) of the second jointed board 120. And the first mounting region 132 and the fourth mounting region 162 are disposed in central symmetry with respect to the center (e.g., point C) of the tiled circuit board structure 100, and the second edge region 141 and the third edge region 151 are disposed in central symmetry with respect to the center (e.g., point C) of the tiled circuit board structure 100. Therefore, the first single board 130, the second single board 140, the third single board 150 and the fourth single board 160 have the same structure, which facilitates the design of layout and the manufacturing process.

Still referring to fig. 2, the first edge region 131 and the second edge region 141 may be rectangular, a length of a connecting edge of the first edge region 131 and the first mounting region 132 is equal to a length of the first single board 130, and a length of a connecting edge of the second edge region 141 and the second mounting region 142 is equal to a length of the second single board 140.

As can be determined from the symmetry relationship, the third edge region 151 and the fourth edge region 161 are rectangular, the length of the connecting edge between the third edge region 151 and the third mounting region 152 is equal to the length of the third board 150, and the length of the connecting edge between the fourth edge region 161 and the fourth mounting region 162 is equal to the length of the fourth board 160. Therefore, the spliced circuit board structure 100 can ensure enough clamping area during the surface mounting process, improve the stability and avoid abnormal phenomena such as displacement.

The tiled circuit board structure 100 has a length direction X and a width direction Y, and the first edge region 131 and the third edge region 151 are arranged along the length direction X, and as can be seen from the symmetry relationship, the second edge region 141 and the fourth edge region 161 are also arranged along the length direction X. Since the transfer direction of the tiled circuit board structure 100 is generally the length direction X thereof during packaging, the first edge region 131 and the third edge region 151, and the second edge region 141 and the fourth edge region 161 can be arranged along the transfer direction, so as to facilitate the clamping of the tiled circuit board structure 100 during soldering.

In this embodiment, the tiled circuit board structure 100 is substantially a rectangular plate-shaped structure, the first single board 130, the second single board 140, the third single board 150, and the fourth single board 160 are all rectangular boards, the long sides of the first single board 130, the second single board 140, the third single board 150, and the fourth single board 160 are all located in the length direction X, and the wide sides of the first single board 130, the second single board 140, the third single board 150, and the fourth single board 160 are all located in the width direction Y.

The length directions of the first edge region 131, the second edge region 141, the third edge region 151 and the fourth edge region 161 are consistent with the length direction X of the tiled circuit board structure 100, and the width directions of the first edge region 131, the second edge region 141, the third edge region 151 and the fourth edge region 161 are consistent with the width direction Y of the tiled circuit board structure 100, so that the clamping area of the tiled circuit board structure 100 and SMT equipment during mounting can be increased, and the clamping stability is improved.

The width of the first edge region 131 is greater than or equal to 5mm, and it can be determined from the symmetry relationship that the widths of the second edge region 141, the third edge region 151, and the fourth edge region 161 are all greater than or equal to 5mm, so as to ensure that the distance from the chip component in the board to the board edge is far enough, and meet the clamping requirement of the SMT equipment. As an example, the widths of the first edge region 131, the second edge region 141, the third edge region 151, and the fourth edge region 161 may all be 5 mm.

The first single plate 130 may further have a first positioning hole 133, the first positioning hole 133 is located at an end of the first edge region 131 away from the second jointed plate 120, the second single plate 140 has a second positioning hole 143, and the second positioning hole 143 and the first positioning hole 133 are centrally and symmetrically disposed with respect to a center (e.g., point a) of the first jointed plate 110, such that the first positioning hole 133 and the second positioning hole 143 are located at diagonal regions of the first jointed plate 110, respectively. The first positioning hole 133 and the second positioning hole 143 are used for positioning during the molding and testing process of the circuit board, and the positioning accuracy can be improved by arranging the first positioning hole 133 and the second positioning hole 143 in the diagonal area of the first jointed board 110, and meanwhile, the foolproof effect can be achieved.

Correspondingly, the third single board 150 is further provided with a third positioning hole 153, the third positioning hole 153 is located at one end of the third edge region 151 close to the first jointed board 110, the fourth single board 160 is provided with a fourth positioning hole 163, the third positioning hole 153 and the fourth positioning hole 163 are arranged in central symmetry with respect to the center (for example, point B) of the second jointed board 120, and the first positioning hole 133 and the fourth positioning hole 163 are arranged in central symmetry with respect to the center (for example, point C) of the circuit board structure 100, so that the third positioning hole 153 and the fourth positioning hole 163 are located in diagonal regions of the second jointed board 120, respectively.

In this embodiment, the first positioning hole 133, the second positioning hole 143, the third positioning hole 153 and the fourth positioning hole 163 are all non-metalized through holes, and the diameters thereof are all between 2mm and 4 mm. Illustratively, the diameters of the first positioning hole 133, the second positioning hole 143, the third positioning hole 153, and the fourth positioning hole 163 are all 3 mm.

In some embodiments, the first positioning hole 133 may also be disposed in the first mounting region 132, or a part of the first positioning hole 133 is located in the first mounting region 132, and another part is located in the first edge region 131. For example, half of the first positioning hole 133 is located in the first mounting region 132, and half of the first positioning hole 133 is located in the first edge region 131.

Referring to FIG. 3, when the mirror-symmetrical plate splicing manner is adopted, the first positioning hole 133 can be located at an end of the first edge region 131 away from the second plate 120, and the second positioning hole 143 and the first positioning hole 133 are arranged in mirror symmetry with respect to the center (e.g., point A) of the first plate 110. The third positioning hole 153 is located at an end of the third edge region 151 away from the first jointed board 110, the third positioning hole 153 and the fourth positioning hole 163 are arranged in mirror symmetry with respect to a center (e.g., point B) of the second jointed board 120, and the first positioning hole 133 and the fourth positioning hole 163 are arranged in central symmetry with respect to a center (e.g., point C) of the circuit board structure 100, such that the first positioning hole 133 and the fourth positioning hole 163 are located at one diagonal of the circuit board structure 100, and the second positioning hole 143 and the third positioning hole 153 are located at the other diagonal.

Still referring to fig. 2, the first single board 130 may further have a first mark point 134, the first mark point 134 is located at an end of the first edge region 131 away from the second jointed board 120, the second single board 140 has a second mark point 144, and the second mark point 144 and the first mark point 134 are centrally symmetrically disposed with respect to a center (e.g., point a) of the first jointed board 110, so that the first mark point 134 and the second mark point 144 are located at diagonal regions of the first jointed board 110.

The first mark point 134 and the second mark point 144 are also called optical identification points, the SMT device usually needs to use the optical identification points for alignment, the first mark point 134 and the second mark point 144 are disposed in diagonal regions of the first jointed board 110 to meet the design requirements of the optical identification points, and the first mark point 134 and the second mark point 144 are both located in the edge region to avoid occupying the space of the mounting region.

Corresponding to the first jointed board 110, the third board 150 is provided with a third marked point 154, the third marked point 154 is located at one end of the third edge region 151 close to the first jointed board 110, the fourth board 160 is provided with a fourth marked point 164, the third marked point 154 and the fourth marked point 164 are arranged in central symmetry with respect to the center (for example, point B) of the second jointed board 120, and the first marked point 134 and the fourth marked point 164 are arranged in central symmetry with respect to the center (for example, point C) of the jointed circuit board structure 100, so that the third marked point 154 and the fourth marked point 164 are located in diagonal regions of the second jointed board 120.

In this embodiment, the mark points are all solid circular pad structures, and the diameters may be all 1mm, 1.5mm, 2mm, or the like. In other embodiments, the marking points may be cross-shaped, square-shaped, etc., and can be identified by the SMT device as well.

The centers of the first mark point 134 and the second mark point 144 may be located on the diagonal of the first panel 110, the centers of the third mark point 154 and the fourth mark point 164 may be located on the diagonal of the second panel 120, so that the first mark point 134 and the second mark point 144 are separated as much as possible in the length direction X of the tiled circuit board structure 100, and the third mark point 154 and the fourth mark point 164 are separated as much as possible in the length direction X of the tiled circuit board structure 100, thereby ensuring that the SMT device can accurately position the panels.

In some embodiments, the first mark 134 may also be disposed in the first mounting region 132, or a part of the first mark 134 is located in the first mounting region 132, and another part is located in the first edge region 131, for example, half of the first mark 134 is located in the first mounting region 132, and half of the first mark 134 is located in the first edge region 131.

Referring to fig. 3, when the mirror-symmetric panel splicing manner is adopted, the first mark point 134 may be located at an end of the first edge region 131 away from the second panel 120, the second mark point 144 and the first mark point 134 are arranged in mirror symmetry with respect to a center (e.g., point a) of the first panel 110, the third mark point 154 is located at an end of the third edge region 151 away from the first panel 110, the third mark point 154 and the fourth mark point 164 are arranged in center symmetry with respect to a center (e.g., point B) of the second panel 120, and the first mark point 134 and the fourth mark point 164 are arranged in mirror symmetry with respect to a center (e.g., point C) of the tiled circuit board structure 100, such that the first mark point 134 and the fourth mark point 164 are located on one diagonal of the tiled circuit board structure 100, and the third mark point 154 and the fourth mark point 164 are located on the other diagonal.

As an example, the centers of the first and second marker points 134, 144 may be located on one diagonal of the tiled circuit board structure 10, and the centers of the third and fourth marker points 154, 164 may be located on the other diagonal of the tiled circuit board structure 10.

Still referring to fig. 2, the distance between the center of the first mark point 134 and the edge of the first single board 130 is greater than the distance between the center of the first positioning hole 133 and the edge of the first single board 130, so that the first mark point 134 and the first positioning hole 133 are staggered in the length direction X of the tiled circuit board structure 100, which is convenient for an operator to distinguish the mark point and the positioning hole. When the length direction of the first edge area 131 is the same as the length direction of the first single board 130, the edge of the first single board 130 refers to the long edge of the first single board 130.

In this embodiment, the distance between the edge of the first mark point 134 and the edge of the first board 130 is greater than or equal to 3mm, so as to avoid that the mark point is easily clamped by the SMT device, which may result in that the mark point cannot be captured by the camera of the SMT device. The distance between the edge of the first positioning hole 133 and the edge of the first single plate 130 is greater than or equal to 1mm, so that the hole can be prevented from being broken. Wherein, the edge of the first single board 130 includes a long edge and a wide edge thereof. The positions and shapes of the remaining marks and positioning holes on the tiled circuit board structure 100 can be referred to the first mark 134 and the first positioning hole 133, and are not described herein again.

In this embodiment, the edge area of each single board has no other openings or gaps except for the mark points and the positioning holes, so that the structural strength of the single board in the edge area can be ensured, and deformation in the clamping process of the SMT equipment is avoided.

In some embodiments, the edge region of each single plate may be provided with screw holes in addition to the mark points and positioning holes, and other positioning holes for production, such as riveting positioning holes for preventing the production plate from deviating during pressing, or drilling positioning holes for positioning during drilling, etc., as long as the patch is not affected. It should be noted that the screw hole may be used as the positioning hole when the hole diameter of the screw hole satisfies the hole diameter requirement of the positioning hole.

Tiled circuit board structure 100 can further include tile tie bars 170, and tile tie bars 170 are connected between first tile 110 and second tile 120. When the boards are separated, only the jointed board connecting ribs 170 need to be disconnected, so that the board separation operation can be facilitated, and a large amount of burrs generated on the edges of each single board can be avoided.

In this embodiment, two joint ribs 170 may be included, one of which is connected between first single plate 130 and third single plate 150, and the other of which is connected between second single plate 140 and fourth single plate 160. Stamp holes may be formed at the joints of the panel connecting ribs 170 and the first and second panels 110 and 120, so that the panels can be easily separated.

In some embodiments, other types of connection between the first panel 110 and the second panel 120, such as V-cut, stamp hole, solid connection, etc., can be used.

The tiled circuit board structure 100 may further include a board connecting rib 180, the board connecting rib 180 is connected between the first board 130 and the second board 140, the board connecting rib 180 is further connected between the third board 150 and the fourth board 160, so that the first board 130 and the second board 140, and the third board 150 and the fourth board 160 can be separated conveniently, and a large amount of burrs can be prevented from being generated on the edge of each board.

In this embodiment, the veneer connecting ribs 180 may include four, two of which are connected between the first veneer 130 and the second veneer 140, and the other two of which are connected between the third veneer 150 and the fourth veneer 160. Stamp holes can be arranged at the joints of the single board connecting ribs 180 and the single boards, so that the boards can be conveniently separated. The panel connector ribs 170 and the veneer connector ribs 180 may be identical connector ribs, with only positional differences in their distribution.

In some embodiments, other connection manners, such as V-cut, stamp hole, and solid connection, may be used between the first single plate 130 and the second single plate 140, and between the third single plate 150 and the fourth single plate 160.

The above example only illustrates the case where the tiled circuit board structure 100 has two panels, and of course, the tiled circuit board structure 100 may further include a greater number of panels such as a third panel and a fourth panel, where the third panel may be tiled on one side of the second panel 120 away from the first panel 110, the fourth panel may be tiled on one side of the third panel away from the second panel 120, the first panel 110 may be referred to as the structure of the third panel, and the second panel 120 may be referred to as the structure of the fourth panel, so as to ensure that the edge regions of the individual boards may be located on both sides of the whole of the tiled circuit board structure 100.

Although the present application has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A tiled circuit board structure, comprising:

the first jointed board comprises a first single board and a second single board which are arranged side by side, the first single board comprises a first edge area, the first edge area is positioned on one side, deviating from the second single board, of the first single board, the second single board comprises a second edge area, the first edge area is a component distribution prohibition area, and the first edge area and the second edge area are arranged in a central symmetry or mirror symmetry mode about the center of the first jointed board; and

the second makeup, the second makeup includes third veneer and fourth veneer, the third veneer with first veneer with the concatenation of fourth veneer, and include third border area, the fourth veneer with the third veneer with the concatenation of second veneer, and include fourth border area, first border area with the fourth border area about the center of concatenation formula circuit board structure is central symmetry setting, the second border area with the third border area about the center of concatenation formula circuit board structure is central symmetry setting.

2. The structure of a splicing circuit board of claim 1, wherein the first board further comprises a first mounting area, the first mounting area is connected to the first edge area, the second board further comprises a second mounting area, the second mounting area is connected to the second edge area and is spliced with the first mounting area, and the first mounting area and the second mounting area are arranged in a central symmetry manner with respect to the center of the first jointed board.

3. The structure of a spliced circuit board as claimed in claim 1, wherein the first board further comprises a first mounting area, the first mounting area is connected to the first edge area, the second board further comprises a second mounting area, the second mounting area is connected to the second edge area and is spliced with the first mounting area, and the first mounting area and the second mounting area are arranged in mirror symmetry with respect to the center of the first jointed board.

4. The tiled circuit board structure according to claim 2 or 3, wherein the first edge area and the second edge area are rectangular, the length of the connecting edge of the first edge area and the first mounting area is equal to the length of the first board, and the length of the connecting edge of the second edge area and the second mounting area is equal to the length of the second board.

5. The tiled circuit board structure of claim 4 wherein the width of the first edge area is greater than or equal to 5 mm.

6. The tiled circuit board structure of claim 1, wherein the first single board is provided with a first positioning hole at an end of the first edge region away from the second tiled board, the second single board is provided with a second positioning hole, and the second positioning hole and the first positioning hole are arranged in central symmetry with respect to the center of the first tiled board.

7. The tiled circuit board structure of claim 6, wherein the distance between the edge of the first positioning hole and the edge of the first single board is greater than or equal to 1 mm.

8. The tiled circuit board structure of claim 6, wherein the first single board is provided with a first marking point, the first marking point is located at an end of the first edge region away from the second tiled board, the second single board is provided with a second marking point, and the second marking point and the first marking point are arranged in a central symmetry manner with respect to the center of the first tiled board.

9. The tiled circuit board structure of claim 8, wherein the distance between the center of the first mark point and the edge of the first single board is greater than the distance between the center of the first positioning hole and the edge of the first single board.

10. The tiled circuit board structure of claim 1, wherein the tiled circuit board structure has a length direction, the first edge region and the third edge region being aligned along the length direction.

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