CN213906812U

CN213906812U - Detection circuit for computer video signal

Info

Publication number: CN213906812U
Application number: CN202023292760.4U
Authority: CN
Inventors: 崔凯
Original assignee: Baoding Sanjin Electronic Technology Co ltd
Current assignee: Baoding Sanjin Electronic Technology Co ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2021-08-06
Anticipated expiration: 2030-12-30

Abstract

The utility model discloses a detection circuit of computer video signals, which comprises a D trigger for acquiring single-path video signals, a CPLD logic device for acquiring multi-path video signals and a singlechip for reading the acquired signals; the clock input end of the D trigger is connected with an H signal input by a video signal, the data input end of the D trigger is connected with a high level, and the output end and the zero clearing end of the D trigger are connected with an IO port of the single chip microcomputer; the CPLD logic device comprises eight D triggers connected in parallel, the clock input end of each D trigger is connected with an H signal input by a plurality of paths of video signals, and the output end and the zero clearing end of each D trigger are connected to the IO port of the single chip microcomputer. The utility model discloses can adopt 74HC74 chip or CPLD programmable logic device to build and form, can realize video signal's one way and multichannel detection, the circuit is simple, and the reliability is high, and response time is fast, has not only reduced the procedure work burden of singlechip, has still improved the degree of accuracy that detects and the work efficiency of system.

Description

Detection circuit for computer video signal

Technical Field

The utility model relates to a computer signal processing technology field, especially a computer video signal's detection circuitry.

Background

VGA (video graphics array), which decomposes the video signal into R, G, B three primary colors and H, V horizontal field signals for transmission.

In the current market, a general VGA video matrix does not have the input state detection and indication functions of VGA signals. The video matrix with the function is basically detected by software, and the accuracy and the corresponding time are not ideal. Because R, G, B in the VGA signal is an analog signal, the amplitude is generally not higher than 1V, and the detection is easily disturbed, which results in low accuracy. H. The V-line field signal is a digital synchronous signal, the frequency of the V-line field signal is basically 60Hz, the corresponding time is slow, the frequency of the H-line signal is basically generally between 30KHz and 200KHz (the frequency of the H-line signal is generally not more than 100KHz in common resolution), the method is suitable for signal detection, the workload of a CPU is increased if software is used for detection, and the corresponding time can not completely meet the requirement.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that needs solve provides a computer video signal's detection circuitry, adopts the circuit that pure hardware detected, improves response time and the degree of accuracy.

In order to solve the technical problem, the utility model adopts the following technical proposal.

A detection circuit of computer video signals comprises a D trigger used for collecting single-channel video signals, a CPLD logic device used for collecting multi-channel video signals and a single chip microcomputer used for reading the collected signals; the clock input end of the D trigger is connected with an H signal input by a video signal, the data input end of the D trigger is connected with a high level, and the output end and the zero clearing end of the D trigger are connected with an IO port of the single chip microcomputer; the CPLD logic device comprises eight D triggers connected in parallel, the clock input end of each D trigger is connected with an H signal input by a plurality of paths of video signals, and the output end and the zero clearing end of each D trigger are connected to the IO port of the single chip microcomputer.

In the detection circuit for the computer video signal, the D flip-flop adopts a 74HC74 chip or a CPLD programmable logic device.

Due to the adoption of the technical scheme, the utility model has the following technical progress.

The utility model discloses a 74HC74 chip or CPLD programmable logic device build and form, can realize video signal's one way and multichannel detection, and the circuit is simple, and the reliability is high, and response time is fast, has not only reduced the procedure work burden of singlechip, has still improved the degree of accuracy that detects and the work efficiency of system.

Drawings

Fig. 1 is a circuit diagram of a single detection circuit of the present invention;

fig. 2 is a circuit diagram of a plurality of detection circuits according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

A detection circuit for computer video signals comprises a D trigger and a single chip microcomputer, wherein the D trigger is used for collecting video signals, and the single chip microcomputer is used for reading the collected signals.

The circuit diagram of a single detection circuit is shown in fig. 1, a clock input end of a D trigger is connected with an H signal input by a video signal, a data input end of the D trigger is connected with a high level, and a data output end and a zero clearing end of the D trigger are connected with an IO port of a single chip microcomputer.

When a video signal is input, a pulse signal with the frequency of dozens of KHz is on the H signal line, a high level signal of the data input end of the D trigger is continuously latched to the data output end, the data output end always has high level signal output, and the high level state can be read by the singlechip through an IO port connected with the singlechip.

When no video signal is input, the H signal line is at a low level, and a signal at the data input end of the flip-flop is not output to the data output end.

When the system works, the single chip microcomputer sends out a data zero clearing signal of the D trigger before reading the output state of the trigger every time, the data output of the trigger becomes low at this time, if no video signal is input, the data output end is always low, and only when an H synchronous signal of the video input signal exists, the data output end of the trigger becomes high, so that the video signal is detected to be input at this time.

The D trigger adopts 74HC74 chips, and when the number of inquired paths is small (N is less than or equal to 4), the D trigger can be realized by adopting 74HC74 chips. When the number of inquired paths is more (N is more than or equal to 5), the method is realized by adopting a CPLD logic device.

The CPLD logic device comprises eight D triggers connected in parallel, the circuit diagram of the CPLD logic device is shown in FIG. 2, the clock input end of each D trigger is connected with an H signal input by a plurality of paths of video signals, and the output end and the zero clearing end of each D trigger are connected to the IO port of the single chip microcomputer through buses. The eight input signals form a group to form a group of data of the singlechip, and the read-write operation is carried out in a bus mode, so that the system works more stably and reliably.

Claims

1. A detection circuit for a computer video signal, characterized by: the device comprises a D trigger for acquiring a single-channel video signal, a CPLD logic device for acquiring a plurality of channels of video signals and a singlechip for reading the acquired signals; the clock input end of the D trigger is connected with an H signal input by a video signal, the data input end of the D trigger is connected with a high level, and the output end and the zero clearing end of the D trigger are connected with an IO port of the single chip microcomputer; the CPLD logic device comprises eight D triggers connected in parallel, the clock input end of each D trigger is connected with an H signal input by a plurality of paths of video signals, and the output end and the zero clearing end of each D trigger are connected to the IO port of the single chip microcomputer.

2. A detection circuit for a computer video signal according to claim 1, wherein: the D trigger adopts a 74HC74 chip or a CPLD programmable logic device.