CN213879842U

CN213879842U - Device of B code output module

Info

Publication number: CN213879842U
Application number: CN202023054345.5U
Authority: CN
Inventors: 张建宏
Original assignee: XI'AN HONGTAI TIME-FREQUENCY
Current assignee: XI'AN HONGTAI TIME-FREQUENCY
Priority date: 2020-12-17
Filing date: 2020-12-17
Publication date: 2021-08-03
Anticipated expiration: 2030-12-17

Abstract

The application discloses a device of a B code output module, relates to the technical field of communication, and solves the problems that the application of the existing B code output device is limited and diversified selection can not be carried out according to the specific requirements of users; the system comprises a motherboard, a panel, an FPGA module and an ARM module; the FPGA module completes the input and output control measurement of signals, and the ARM module is used for displaying and controlling the touch screen; the FPGA module receives the 1PPS second signal and the time information of the motherboard, the format is converted, and then a B code format is output, and the motherboard also sends a board card state to the ARM module; the FPGA module outputs a plurality of B code DC code signals and a plurality of B code AC code signals to the B code format through modulation, demodulation and shunt; the multi-channel B code direct current code can be output, the multi-channel B code alternating current code can be output, the DC code is suitable for short-distance transmission, the AC code is suitable for long-distance transmission, the precision of the AC code is different, and different output mode ports can be selected according to specific requirements.

Description

Device of B code output module

Technical Field

The application relates to the technical field of communication, in particular to a device of a B code output module.

Background

The time-of-day technology has been widely used in scientific research, rocket launching, navigation, weapon test, aircraft test, and daily life. Inter-range instrumentation group (IRIG) code is a time standard specified by the united states command of the army command committee, and has 4 parallel binary time code formats and 6 serial binary time code formats, wherein the most common is the united states army instrumentation group B format, i.e. IRIG-B (B code for short) time code format. The B code is used as a standard interface of the time system equipment and the user equipment, so that the reliability and consistency of a measurement and control communication system in the whole electronic equipment test are improved, and the measurement precision of the target range test equipment is directly influenced.

The IRIG-B code usually adopts a serial time code format, the time frame rate is 1 frame/second, each frame consists of 100 code elements, the period of each code element is 10ms, the IRIG-B code has direct current and alternating current, and the direct current code is a pulse width coding mode. The alternating current code is formed by amplitude modulating the direct current code by sine wave carrier frequency of 1 kHz. Compared with the alternating-current code, the direct-current code has higher precision, but because the frequency spectrum of the pulse signal is rich, the narrow-band channel cannot be transmitted, and the direct-current code is only suitable for being transmitted to a closer user through a cable.

The existing B code output device has few output lines and is limited in application, or meets the requirements that an alternating current code and a cable are output to a user far away, but the precision is limited, or outputs a direct current code to meet the precision requirement, but the cable is transmitted to a user near, so that the precision and the users at different distances cannot be simultaneously considered, and diversified selection cannot be performed according to the specific requirements of the users.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a device of B code output module, it is few to have solved B code output device output line among the prior art, use comparatively limited problem, the mother board of this application embodiment receives 1PPS second signal and time information from host system, through modem output multichannel B code DC code and multichannel B code AC code along separate routes, send the integrated circuit board state to host system through the CAN bus simultaneously, it is many to have satisfied output line, use extensively, and CAN select the output mode of direct current code or alternating current code according to concrete demand, satisfy the demand of pluralism.

The embodiment of the utility model provides a device of a B code output module, which comprises a motherboard, a panel, an FPGA module and an ARM module; the FPGA module and the ARM module jointly form a main control module, the FPGA module completes input and output control measurement of signals, and the ARM module is used for displaying and controlling the touch screen.

The FPGA module receives the 1PPS second signal and the time information of the motherboard, converts the format of the 1PPS second signal and the time information and outputs a B code format, and the motherboard also sends a board card state to the ARM module; the FPGA module outputs a plurality of B code DC code signals and a plurality of B code AC code signals to the B code format through modulation and demodulation branches; the panel receives a plurality of the B-code DC codes and a plurality of the B-code AC codes.

In a possible implementation manner, the ARM module is connected to the FPGA module through an RS232 interface and is connected to the motherboard through a CAN bus, and the ARM module further receives processing information from the FPGA module and board card state information sent by the motherboard.

In a possible implementation manner, the FPGA module is further electrically connected to a DAC chip, and the DAC chip receives the B-code digital information modulated by the FPGA module and performs digital-to-analog conversion on the B-code digital information.

In a possible implementation manner, the system further comprises a B code output state detection module, and the B code output state detection module detects a B code state output by the FPGA module.

The output end of the FPGA module is further connected with an LED display screen, and the detected B code output state is displayed through the LED display screen.

In a possible implementation manner, the signal at the output end of the DAC chip is connected to a plurality of operational amplifiers, a plurality of corresponding transformers are coupled to the operational amplifiers, and the operational amplifiers generate a plurality of B-code AC codes with controllable amplitude according to the signal at the output end of the DAC chip and the amplification factor, and input the B-code AC codes to the panel.

In a possible implementation manner, the output end of the FPGA module is connected to the inlet end of the LVTTL to 422 differential module through the LVTTL-DC code, and the LVTTL to 422 differential module outputs a plurality of paths of B code DC codes to the panel.

In one possible implementation, the ARM module employs an LPC1752 chip.

In a possible implementation manner, the FPGA module is connected with the ARM module through an RS232 serial port.

In a possible implementation manner, the system further comprises 4 LED interfaces, 2B-code DC code output interfaces and two B-code AC code output interfaces; the LED interface, the B code DC code output interface and the B code AC code output interface are all connected with the panel;

and a CAN bus interface, an STD _ PPS interface and a voltage interface inside the main control module are arranged between the main control module and the motherboard.

The embodiment of the utility model provides a FPGA module, ARM module constitute host system jointly, and the FPGA module receives 1PPS second signal and the time information of motherboard, carries out the format conversion to 1PPS second signal and time information and then exports B sign indicating number form, and the motherboard still sends the integrated circuit board state to the ARM module; the FPGA module outputs a plurality of B code DC code signals and a plurality of B code AC code signals to the B code format through modulation and demodulation branches, so that a plurality of paths of B code direct current codes can be output, a plurality of paths of B code alternating current codes can be output, the DC codes are suitable for short-distance transmission, the AC codes are suitable for long-distance transmission, the precision is different, and different output mode ports can be selected according to specific requirements.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments of the present invention or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a device of a B-code output module according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a data interface of a B-code output module device according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As shown in fig. 1, an embodiment of the present invention provides a device of a B code output module, which includes a motherboard, a panel, an FPGA module, and an ARM module;

the FPGA module and the ARM module jointly form a main control module, the FPGA module completes input and output control measurement of signals, and the ARM module is used for displaying and controlling the touch screen; the FPGA module receives the 1PPS second signal and the time information of the motherboard, carries out format conversion on the 1PPS second signal and the time information and then outputs a B code format, and the motherboard also sends a board card state to the ARM module; the FPGA module outputs a plurality of B code DC code signals and a plurality of B code AC code signals to the B code format through modulation, demodulation and shunt; the panel receives a multi-way B-code DC code and a multi-way B-code AC code.

Through the scheme, the motherboard transmits the received 1PPS second signal and the time information to the FPGA module and the ARM module, and the FPGA module resolves the received 1PPS second signal and the time information. The FPGA module is also equivalent to a demodulation unit which demodulates a B code DC code, the DC code is used for synchronizing a digital sinusoidal signal, the phase of the sinusoidal signal is consistent with the edge of a DC code pulse, and a 1PPS second signal and time information are output to the next step under the action of the FPGA module and the ARM module.

The connection mode of the FPGA module and the ARM module is as follows: the ARM module is connected with the FPGA module through an RS232 interface and is connected with the motherboard through a CAN bus, and the ARM module also receives processing information from the FPGA module and board card state information sent by the motherboard to form information transmission and feedback circulation.

The FPGA module is also electrically connected with a DAC chip, and the DAC chip receives the B-code digital information modulated by the FPGA module and performs digital-to-analog conversion on the B-code digital information. The common digital-to-analog conversion is to convert a parallel binary digital quantity into a direct current voltage or a direct current, which is commonly used as an output channel of a process control computer system and connected with an actuator to realize the automatic control of the production process.

When digital-to-analog conversion is performed, the B code digital information may generally include a digital controlled oscillator and a modulation signal generator; the digital control oscillator is used for generating a digital sinusoidal signal, and the DC code is used for synchronizing the digital sinusoidal signal after passing through the FPGA, so that the phase of the digital sinusoidal signal is consistent with the edge of the DC code pulse; the modulation signal generator generates an accurate digital level signal according to the DC code and the modulation ratio information, and then inputs the level signal into a DAC chip for digital-to-analog conversion, the DAC chip converts a digital sinusoidal signal generated by the digital controlled oscillator into a sine wave, and the amplitude of the sine wave is controlled by generating the accurate digital level signal according to the DC code and the modulation ratio information, wherein the sine wave is a B-code AC code.

Because a plurality of high-frequency components are mixed in the output signal of the DAC, the signal which is just converted cannot be directly used for power output, otherwise, the power tube can quickly generate heat due to excessive high-frequency signals, and the power consumption is increased; the rear operational amplifier generally forms an LPF circuit, namely an active low-pass filter, so that high-frequency signals can be removed, the signal-to-noise ratio of useful signals is improved, and useless power consumption is reduced. Therefore, the amplifier is connected behind the DAC chip, and according to the 4 sets of SIP communication lines electrically connected to the FPGA, the amplification factor of the 4-way amplifier is accurately controlled, and the amplitude of the output B-code AC code can be accurately controlled.

The embodiment of the utility model also comprises a B code output state detection module which detects the B code state output by the FPGA module; the output end of the FPGA module is also connected with an LED display screen, and the detected B code output state is displayed through the LED display screen.

Continuing to refer to fig. 1, the signal at the output end of the DAC chip is connected to a plurality of operational amplifiers, the operational amplifiers are coupled to a plurality of corresponding transformers, and the operational amplifiers generate a plurality of B-code AC codes with controllable amplitude according to the signal at the output end of the DAC chip and the amplification factor, and input the B-code AC codes to the panel.

The output end of the FPGA module is connected with the inlet end of the LVTTL-to-422 differential module through an LVTTL-DC code, and the LVTTL-to-422 differential module outputs a plurality of paths of B code DC codes to a panel.

Additionally, the utility model discloses the ARM module adopts LPC1752 chip, and the FPGA module passes through RS232 serial ports with the ARM module and is connected.

If the structure of the embodiment of the present invention without the panel and the motherboard becomes a B code output module, as shown in fig. 2, the embodiment of the present invention further includes 4 LED interfaces, 2B code DC code output interfaces and two B code AC code output interfaces; the LED interface, the B code DC code output interface and the B code AC code output interface are all connected with a panel; a CAN bus interface, an STD _ PPS interface and a voltage interface inside the B code output module are arranged between the motherboard and the ARM module of the B code output module.

The embodiments in the present specification are described in a progressive manner, and the same or similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. All or portions of the present application are operational with numerous general purpose or special purpose computing system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet-type devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure.

Claims

1. A device of a B code output module is characterized by comprising a motherboard, a panel, an FPGA module and an ARM module;

the FPGA module and the ARM module jointly form a main control module, the FPGA module completes input and output control measurement of signals, and the ARM module is used for displaying and controlling the touch screen;

the FPGA module receives the 1PPS second signal and the time information of the motherboard, converts the format of the 1PPS second signal and the time information and outputs a B code format, and the motherboard also sends a board card state to the ARM module;

the FPGA module outputs a plurality of B code DC code signals and a plurality of B code AC code signals to the B code format through modulation and demodulation branches;

the panel receives a plurality of the B-code DC codes and a plurality of the B-code AC codes.

2. The apparatus of the B-code output module of claim 1, wherein the ARM module is connected to the FPGA module through an RS232 interface and connected to the motherboard through a CAN bus, and the ARM module further receives the processing information from the FPGA module and receives the board status information sent by the motherboard.

3. The apparatus of the B-code output module according to claim 1, wherein the FPGA module is further electrically connected to a DAC chip, and the DAC chip receives the B-code digital information modulated by the FPGA module and performs digital-to-analog conversion on the B-code digital information.

4. The apparatus of the B-code output module according to claim 3, further comprising a B-code output state detection module, wherein the B-code output state detection module detects a B-code state output by the FPGA module;

5. The apparatus of the B-code output module according to claim 3, wherein the signal at the output end of the DAC chip is connected to a plurality of operational amplifiers, a plurality of corresponding transformers are coupled to the plurality of operational amplifiers, and the operational amplifiers generate a plurality of amplitude-controllable B-code AC codes according to the signal at the output end of the DAC chip and the amplification factor, and input the B-code AC codes to the panel.

6. The apparatus of the B-code output module according to claim 3, wherein the output terminal of the FPGA module is connected to the input terminal of the LVTTL to 422 differential module through the LVTTL-DC code, and the LVTTL to 422 differential module outputs a plurality of B-code DC codes to the panel.

7. The apparatus of the B-code output module of claim 1, wherein the ARM module employs an LPC1752 chip.

8. The apparatus of the B-code output module of claim 1, wherein the FPGA module is connected with the ARM module through an RS232 serial port.

9. The apparatus of the B-code output module according to claim 1, further comprising 4 LED interfaces, 2B-code DC code output interfaces and two B-code AC code output interfaces; the LED interface, the B code DC code output interface and the B code AC code output interface are all connected with the panel;