CN114995235A - Multi-functional general baseband processing apparatus of frequency agility based on ZYNQ - Google Patents
Multi-functional general baseband processing apparatus of frequency agility based on ZYNQ Download PDFInfo
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- CN114995235A CN114995235A CN202210607918.7A CN202210607918A CN114995235A CN 114995235 A CN114995235 A CN 114995235A CN 202210607918 A CN202210607918 A CN 202210607918A CN 114995235 A CN114995235 A CN 114995235A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a frequency agility multifunctional universal baseband processing device based on ZYNQ, which comprises a frequency agility circuit, a clock distribution circuit, an ADC acquisition circuit, a level conversion circuit, a ZYNQ signal processing circuit, a storage circuit, a debugging interface, a back board communication, a power supply management and a panel connector, wherein the frequency agility circuit is connected with the clock distribution circuit; the device can communicate with an upper computer according to the CPCI specification through a CPCI bus interface. The device has the advantages that the ZYNQ chip is used for controlling and achieving generation, receiving and modulation and demodulation of double-channel 70 MHz-6 GHz broadband frequency band agile frequency signals, meanwhile, the device has a single-channel analog signal ADC high-speed acquisition function and a single-channel TTL signal output function, simultaneously supports various serial port communication functions, and has certain advantages of generalization, integration and modularization. The device is mainly applied to the field of measurement and control communication, can be matched with a radio frequency module to realize the ground test function of a measurement and control single machine with various wave bands such as P/L/S/C/X and the like, can communicate with an upper computer through a CPCI interface, and completes the efficient data transmission and control of the module.
Description
Technical Field
The invention relates to the technical field of measurement and control communication, in particular to a frequency agility multifunctional universal baseband processing device based on ZYNQ, which can be used for ground test of a measurement and control single machine of a carrier rocket.
Background
In recent years, with the densification of launch tasks of carrier rockets in China, the defects of traditional ground test equipment of an external security system are increasingly shown, and the ground test equipment mainly has the defects of poor generalization degree, complex system composition, high cost, heaviness and the like, so that a frequency-agile multifunctional universal baseband processing device based on ZYNQ is produced as a part of novel universal ground test equipment.
Patent numbers: 201821180718.3, inventor: populus, zhangpengquan, fangyuijin, zhangjing, sallow, and no, the patent name: a multi-channel wireless signal acquisition device based on ZYNQ is provided, and the multi-channel wireless signal acquisition device based on ZYNQ adopts an FPGA + ZYNQ cooperative framework to acquire wireless signals of a multi-channel ADC, wherein the sampling rate is 112MHz, the multi-channel ADC does not have the function of generating modulation signals, and the multi-channel wireless signal acquisition device is single in function and does not have certain universality and is greatly different from the multi-channel wireless signal acquisition device based on ZYNQ cooperative framework.
Patent numbers: 202023068307.5, inventor: zhangyongjun, cai dynasty, daoming forest, zhuiyinbai, gahongli, yangli, patent names: a miniaturized low-power-consumption multi-channel software radio platform is provided, and belongs to the invention based on ZYNQ, the working frequency range of the software radio platform is 100 kHz-3800 MHz, the frequency range is narrower compared with the invention, the software radio platform does not support network port communication and CPCI communication, compared with the invention, the application scene is also distinguished, meanwhile, the invention also supports high-speed ADC acquisition, TTL output and various serial communication functions, and can be inserted into an industrial control cabinet supporting 3U card slot CPCI communication specification.
Patent numbers: 201920277064.4, inventor: sheet update, patent name: the invention discloses an embedded hardware platform based on AD9361 multichannel spectral analysis, and provides the embedded hardware platform based on AD9361 multichannel spectral analysis, wherein three groups of transceiving channels based on AD9361 are realized, two groups of transceiving channels realized based on AD9364 are distinguished from the scheme, and then the AD9361 has lower isolation between the channels due to higher channel integration level, and in addition, the scheme framework adopts a framework of cooperative work of FPGA + ZYNQ, compared with the scheme, the working scene is distinguished, and the system constitution has certain difference.
In summary, the existing ground testing equipment for external safety systems has increasingly obvious defects, such as poor generalization degree, complex system structure, high cost, heaviness and the like.
Disclosure of Invention
The invention aims to provide a frequency agile multifunctional general baseband processing device based on ZYNQ.
The invention provides a frequency agility multifunctional general baseband processing device based on ZYNQ, which comprises: frequency agility circuit, clock distribution circuit, ADC acquisition circuit, level conversion circuit, memory circuit, debugging interface, backplate communication circuit, power management circuit, the panel connector that is connected with ZYNQ signal processing circuit electricity respectively, wherein:
the frequency agility circuit comprises a first frequency agility chip, a second frequency agility chip, a first impedance matching module and a second impedance matching module; one end of the first impedance matching module is bidirectionally connected with one end of the first frequency agility chip, the other end of the first impedance matching module generates a transceiving signal and is respectively connected with the corresponding ports of the panel connector, and the other end of the first frequency agility chip is electrically connected with the ZYNQ signal processing circuit; one end of the second impedance matching module is bidirectionally connected with one end of the second frequency agile chip, the other end of the second impedance matching module generates a transceiving signal and is respectively connected with the corresponding ports of the panel connector, and the other end of the second frequency agile chip is electrically connected with the ZYNQ signal processing circuit;
the clock distribution circuit comprises a 40MHz internal crystal oscillator, a 250MHz crystal oscillator, a clock selection chip, a first clock distributor and a second clock distributor; the 40MHz crystal oscillator and a 40MHz external reference signal input through the panel connector carry out 1-out-of-2 circuit output 1-path signal through the clock selection chip, the output 1-path signal is electrically connected with the input end of the first clock distributor, the output end of the first clock distributor outputs a first shunt signal, and the first shunt signal is respectively distributed to the frequency agile circuit and the ZYNQ signal processing circuit; the 250MHz crystal oscillator is electrically connected with the second clock distributor, and is shunted through the second clock distributor and outputs a second shunt signal, and the second shunt signal is respectively output to the ADC acquisition circuit and the ZYNQ signal processing circuit;
the ADC acquisition circuit comprises a third impedance matching module and an ADC analog-to-digital converter; the analog signal is electrically connected with the third impedance matching module through a corresponding port of the panel connector, the analog signal is sent to the ADC for data acquisition through the third impedance matching module, and the data acquired by the ADC is received and processed through the ZYNQ signal processing circuit;
the level conversion circuit comprises a driving chip, and two ends of the driving chip are respectively electrically connected with the corresponding port of the panel connector and the ZYNQ signal processing circuit;
the ZYNQ signal processing circuit comprises a ZYNQ chip and a 33.3MHz crystal oscillator, the ZYNQ chip comprises a PL end and a PS end, and the 33.3MHz crystal oscillator is connected with the PS end;
the storage circuit comprises a DDR3, a QSPI Flash and a first EEPROM, the DDR3 and the QSPI Flash are connected with the PS end of the ZYNQ signal processing circuit, and the first EEPROM is connected with the PL end of the ZYNQ signal processing circuit;
the debugging interface comprises an RS232 serial port, a JTAG debugging interface and a PHY gigabit Ethernet interface, and the RS232 serial port, the JTAG debugging interface and the PHY gigabit Ethernet interface are connected with the PS end of the ZYNQ signal processing circuit;
the backboard communication circuit comprises an analog quantity acquisition circuit, an RS422 serial port, a CPCI communication circuit and a second EEPROM, wherein the analog quantity acquisition circuit, the RS422 serial port and the CPCI communication circuit are all connected with a corresponding port of the panel connector and a PL end of the ZYNQ signal processing circuit, and the second EEPROM is electrically connected with the CPCI in a communication way;
the power management circuit comprises a secondary power converter, and two ends of the secondary power converter are respectively connected with corresponding ports of the ZYNQ signal processing circuit and the panel connector.
Preferably, the device is of a board card structure, the device is communicated with an upper computer through a CPCI bus interface to finish efficient data transmission and control of the module, and the overall dimension of the CPCI bus interface is matched with the single-slot 3U board card.
Preferably, the frequency agility chip adopts AD 9364.
Preferably, the first clock distributor and the second clock distributor both use ADCLK846BCPZ as a chip.
Preferably, the ADC chip employs AD 9434.
Preferably, the driving chip is SN74AHC1G 04.
Preferably, the ZYNQ chip is XC7Z100-2FFG 900I.
Preferably, the panel connector includes a first port, a second port, a third port, a fourth port, a fifth port, a sixth port, a seventh port, an eighth port, and a ninth port, where the first port, the second port, the third port, and the fourth port are respectively disposed in the frequency agile circuit and located on a front panel of a board, the fifth port is disposed in the clock distribution circuit and located on the front panel of the board, the sixth port is disposed in the ADC acquisition circuit and located on the front panel of the board, and the seventh port is disposed in the level conversion circuit and located on the front panel of the board; the eighth port and the ninth port are located on a board card rear panel.
Preferably, the first port, the second port, the third port, the fourth port, the fifth port, the sixth port and the seventh port of the panel connector are SMP-JWHD semi-escapement type radio frequency connectors.
Preferably, the ninth port of the panel connector is a J15022101 type connector.
Compared with the prior art, the invention has the following beneficial effects:
the frequency agile universal baseband processing device with the ZYNQ chip as the core processor integrates various board cards such as oscilloscope cards, serial port cards, signal source cards and the like in the traditional ground test equipment, realizes the weight reduction of the equipment, can realize the ground test function of a measurement and control single machine with various wave bands such as P/L/S/C/X and the like by matching with a radio frequency module, has certain universal combinatory advantages, can communicate with an upper computer through a CPCI interface, and completes the efficient data transmission and control of the module. The development time of the equipment can be greatly shortened based on the generalization advantage of the device, and the complexity of the equipment is simplified. The baseband processing device can communicate with an upper computer through a CPCI bus interface according to a CPCI specification, and the overall dimension of a bus interface module meets the requirement of a standard single-slot 3U board card.
Drawings
Fig. 1 is a schematic block diagram of a frequency agile multifunctional general baseband processing apparatus based on ZYNQ according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a frequency agility multifunctional general baseband processing device based on ZYNQ, which comprises: the device comprises a frequency agile circuit, a clock distribution circuit, an ADC acquisition circuit, a level conversion circuit, a storage circuit, a debugging interface, a backboard communication circuit, a power management circuit and a panel connector which are respectively and electrically connected with a ZYNQ signal processing circuit. The development time of the equipment can be greatly shortened based on the generalization advantage, and the complexity of the equipment is simplified. The baseband processing card can be communicated with an upper computer through a CPCI bus interface according to a CPCI specification, and the overall dimension of a bus interface module meets the requirement of a standard single-slot 3U board card. The frequency agile multifunctional general baseband processing card based on the ZYNQ can be inserted into an industrial personal computer box, the size of occupied space is 3U single grooves, and an upper computer can be matched with driving software to communicate with software on a ZYNQ chip, so that the configuration and the operation of functions of a board card are realized.
Wherein:
the frequency agility circuit comprises a first frequency agility chip, a second frequency agility chip, a first impedance matching module and a second impedance matching module; one end of the first impedance matching module is bidirectionally connected with one end of the first frequency agility chip, the other end of the first impedance matching module generates a transceiving signal and is respectively connected with the corresponding ports of the panel connector, and the other end of the first frequency agility chip is electrically connected with the ZYNQ signal processing circuit; one end of the second impedance matching module is bidirectionally connected with one end of the second frequency agile chip, the other end of the second impedance matching module generates a transceiving signal and is respectively connected with the corresponding ports of the panel connector, and the other end of the second frequency agile chip is electrically connected with the ZYNQ signal processing circuit; the first frequency agility chip and the second frequency agility chip are linked with the first impedance matching module and the second impedance matching module to generate two receiving and sending signals to be connected with panel connectors (J1-J4), and the first frequency agility chip and the second frequency agility chip are connected with the ZYNQ signal processing circuit and are configured and processed through the ZYNQ signal processing circuit; the frequency agility chip adopts AD 9364.
As can be understood by those skilled in the art, the frequency agility circuit is connected with the ZYNQ signal processing circuit and is configured by performing the ZYNQ signal processing circuit; the frequency agile circuit adopts an AD9364 frequency agile chip of ADI company, the working frequency is 70MHz to 6GHz, the channel bandwidth of 200KHz to 56MHz is supported, the chip adopts a zero intermediate frequency architecture, the whole radio frequency and intermediate frequency signal circuit is integrated in one chip, the RF2 multiplied by 2 transceiver comprises a radio frequency amplifier, an analog filter, a mixer, a demodulator, a 12 bit ADC and a DAC, the programmable capability is higher, and the modulation precision and the noise are higher. The frequency agile circuit carries out parameter configuration through a PS end of the ZYNQ signal processing circuit, modulation and demodulation of two sending and receiving signals of the frequency agile circuit are achieved through a PL end of the ZYNQ signal processing circuit, and the two sending and receiving signals are connected with a SMP-JWHD type radio frequency connector through an impedance matching network in an impedance matching mode to 50 omega.
The clock distribution circuit comprises a 40MHz internal crystal oscillator, a 250MHz crystal oscillator, a clock selection chip, a first clock distributor and a second clock distributor; the 40MHz crystal oscillator and a 40MHz external reference signal input by the panel connector J5 output 1-channel signal by a 2-to-1 circuit through the clock selection chip, the output 1-channel signal is electrically connected with the input end of the first clock distributor, the output end of the first clock distributor outputs a first shunt signal, and the first shunt signal is respectively distributed to the frequency agile circuit and the ZYNQ signal processing circuit; the 250MHz crystal oscillator is electrically connected with the second clock distributor, and is shunted through the second clock distributor and outputs a second shunt signal, and the second shunt signal is respectively output to the ADC acquisition circuit and the ZYNQ signal processing circuit; the first clock distributor and the second clock distributor both adopt chips ADCLK846 BCPZ.
The clock distribution circuit can complete the selection function of the internal and external reference clocks, namely, the upper computer controls the ZYNQ signal processing circuit to switch the external clock through the clock selection circuit under the condition that the external reference is needed, and controls the enabling pin of the internal 40MHz crystal oscillator to be in an invalid state while switching to the external clock, so that the interference of the same-frequency clock when the board card works is avoided. The internal and external clocks are fed to the clock distributor after passing through one of the two modes, and the internal and external clocks are divided into three paths by the clock distributor: the two signals are respectively provided for two AD9364 modules and a ZYNQ signal processing circuit, and the alternative chip is ADG772 BCPZ; on the other hand, the 250MHz reference crystal oscillator in the circuit is divided into two paths by the clock distributor and respectively provided for the ADC acquisition circuit and the ZYNQ signal processing circuit, and the 250MHz sampling rate of the ADC acquisition circuit can enable the acquisition circuit to obtain a sampling point every 4ns, which has the advantage of obtaining higher signal processing precision, such as: the method has the advantage of being beneficial to improving the measurement precision of the rising edge time and the falling edge time of the pulse signal.
The ADC acquisition circuit comprises a third impedance matching module and an ADC analog-to-digital converter; the analog signal is electrically connected with the third impedance matching module through a port J6 corresponding to the panel connector, the analog signal is sent to the ADC for data acquisition through the third impedance matching module, and the data acquired by the ADC is received and processed through the ZYNQ signal processing circuit; the ADC chip is AD 9434.
The level conversion circuit comprises a driving chip, and two ends of the driving chip are respectively and electrically connected with the corresponding port J7 of the panel connector and the ZYNQ signal processing circuit; the driving chip is SN74AHC1G 04. As can be understood by those skilled in the art, the level conversion is used for converting one I/O port at the PL end of the ZYNQ signal processing circuit from a CMOS level to a TTL level, and the level conversion is mainly used for generating high and low level signals or pulse signals, and the achievable effects are that the rising edge time does not exceed 80ns, the falling edge time does not exceed 100ns, and the level conversion can be used as a switch or for generating a PWM signal.
The ZYNQ signal processing circuit comprises a ZYNQ chip and a 33.3MHz crystal oscillator, wherein the ZYNQ chip comprises a PL terminal (FPGA) and a PS terminal (ARM), an embedded Linux operating system is supported to run at the PS terminal, and the 33.3MHz crystal oscillator is connected with the PS terminal; the ZYNQ chip is XC7Z100-2FFG 900I.
Those skilled in the art can understand that the ZYNQ signal processing circuit comprises a ZYNQ chip and a 33.3MHz crystal oscillator, the ZYNQ chip comprises a PL (field programmable gate array) terminal and a PS (advanced RISC machine) terminal, wherein the PS terminal is the same as a standard ARM development terminal in a software development mode, a Linux operating system can be operated, the PL terminal has fast and efficient parallel processing capability, signal high-speed parallel processing can be realized, and meanwhile, the PL has strong interface expansion capability and can realize various common and high-speed interface designs. And the 33.3MHz crystal oscillator is connected with the PS end and provides a global reference clock for the PS end.
The storage circuit comprises a DDR3, a QSPI Flash and a first EEPROM, the DDR3 and the QSPI Flash are connected with the PS end of the ZYNQ signal processing circuit, and the first EEPROM is connected with the PL end of the ZYNQ signal processing circuit; the DDR3 chip capacity is 4Gb, the QSPI Flash memory capacity is 128Mb, the first EEPROM capacity is 16KB, the DDR3 provides 4Gb data caching capacity for the PS end of the ZYNQ signal processing circuit, the QSPI Flash provides 128Mb software running memory for the PS end of the ZYNQ signal processing circuit, and the first EEPROM is used for storing system configuration files and loading storage configuration during starting.
The debugging interface comprises an RS232 serial port, a JTAG debugging interface and a PHY gigabit Ethernet interface, the interfaces are led out through JL24-20ZJB direct-insertion connectors, and the debugging interface can be used for software debugging and software curing of board cards. The RS232 serial port, the JTAG debugging interface and the PHY gigabit Ethernet interface are connected with the PS end of the ZYNQ signal processing circuit; the serial port chip is MAX3232EUE +, and the PHY chip is 88E1518-A0-NNB2C 000.
The backboard communication circuit comprises an analog quantity acquisition circuit, an RS422 serial port, a CPCI communication circuit and a second EEPROM, wherein the analog quantity acquisition circuit, the RS422 serial port and the CPCI communication circuit are all connected with a port J8 corresponding to the panel connector and a PL end of the ZYNQ signal processing circuit, and the second EEPROM is in communication and electric connection with the CPCI; wherein the second EEPROM capacity is 2 KB. The analog quantity acquisition circuit can realize that 8 paths of analog signals are input through a backboard connector port J8, the switch acquires one path of analog quantity in a time-sharing mode, the acquisition voltage range is 0-5V, and the acquisition chip is ADG1608 BCPZ; the RS422 serial port can simultaneously realize serial port communication between the upper computer and the ZYNQ signal processing circuit through a backboard connector port J8, and an RS422 serial port chip is MAX3490 ESA; the CPCI communication and ZYNQ signal processing circuit PL end is connected to a backplane connector port J9, the CPCI backplane communication can be communicated with an upper computer through a backplane connector port J9, and the CPCI communication bridge is PCI 9054; and the second EEPROM is connected with the CPCI communication circuit and provides a storage space for parameter configuration for the communication bridge chip.
The power management circuit comprises a secondary power converter, and two ends of the secondary power converter are respectively connected with the ZYNQ signal processing circuit and the corresponding port J9 of the panel connector. The power management part acquires a +12V direct-current power supply from a backboard interface, converts the direct-current power supply into working voltage comprising a frequency agile circuit, a clock distribution circuit, an ADC acquisition circuit, a level conversion circuit, a ZYNQ signal processing circuit, a storage circuit, a debugging interface, backboard communication and the like through secondary power supply conversion, converts the +12V into 1V/8.8A through a chip LTM4620, converts the +12V into 1.5V/4A, 2.5V/4A, 1.8V/4A and 3.3V/4A through a chip LTM4644, wherein the 1.5V is converted into 0.75V/0.25A through a 520TPS 0 chip, the 2.5V is converted into 1.2V/1.2A through an ADP1755 chip, the 1.8V is converted into 1.3V/1.2A through two ADP1755 chips, and the converted power supply ripple can meet the whole low-level and stable work of a board card.
Further, the panel connector includes a first port J1, a second port J2, a third port J3, a fourth port J4, a fifth port J5, a sixth port J6, a seventh port J7, an eighth port J8, and a ninth port J9, the first port J1, the second port J2, the third port J3, and the fourth port J4 are respectively disposed in the frequency agile circuit and located on a front panel of a board card, the fifth port J5 is disposed in the clock distribution circuit and located on a front panel of a board card, the sixth port J6 is disposed in the ADC acquisition circuit and located on a front panel of a board card, and the seventh port J7 is disposed in the level conversion circuit and located on a front panel of a board card; the eighth port J8 and the ninth port J9 are located on the rear panel of the board card.
Further, the first port J1, the second port J2, the third port J3, the fourth port J4, the fifth port J5, the sixth port J6 and the seventh port J7 of the panel connector are SMP-JWHD semi-escapement type radio frequency connectors.
Further, the ninth end J9 port of the panel connector is a J15022101 type connector.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. The utility model provides a multi-functional general baseband processing apparatus of frequency agility based on ZYNQ which characterized in that includes: frequency agility circuit, clock distribution circuit, ADC acquisition circuit, level conversion circuit, memory circuit, debugging interface, backplate communication circuit, power management circuit, the panel connector that is connected with ZYNQ signal processing circuit electricity respectively, wherein:
the frequency agility circuit comprises a first frequency agility chip, a second frequency agility chip, a first impedance matching module and a second impedance matching module; one end of the first impedance matching module is bidirectionally connected with one end of the first frequency agility chip, the other end of the first impedance matching module generates a transceiving signal and is respectively connected with the corresponding ports of the panel connector, and the other end of the first frequency agility chip is electrically connected with the ZYNQ signal processing circuit; one end of the second impedance matching module is bidirectionally connected with one end of the second frequency agile chip, the other end of the second impedance matching module generates a transceiving signal and is respectively connected with the corresponding ports of the panel connector, and the other end of the second frequency agile chip is electrically connected with the ZYNQ signal processing circuit;
the clock distribution circuit comprises a 40MHz internal crystal oscillator, a 250MHz crystal oscillator, a clock selection chip, a first clock distributor and a second clock distributor; the 40MHz crystal oscillator and a 40MHz external reference signal input through the panel connector carry out 1-out-of-2 circuit output 1-path signal through the clock selection chip, the output 1-path signal is electrically connected with the input end of the first clock distributor, the output end of the first clock distributor outputs a first shunt signal, and the first shunt signal is respectively distributed to the frequency agile circuit and the ZYNQ signal processing circuit; the 250MHz crystal oscillator is electrically connected with the second clock distributor, and is shunted through the second clock distributor and outputs a second shunt signal, and the second shunt signal is respectively output to the ADC acquisition circuit and the ZYNQ signal processing circuit;
the ADC acquisition circuit comprises a third impedance matching module and an ADC analog-to-digital converter; the analog signal is electrically connected with the third impedance matching module through a corresponding port of the panel connector, the analog signal is sent to the ADC for data acquisition through the third impedance matching module, and the data acquired by the ADC is received and processed through the ZYNQ signal processing circuit;
the level conversion circuit comprises a driving chip, and two ends of the driving chip are respectively electrically connected with the corresponding ports of the panel connector and the ZYNQ signal processing circuit;
the ZYNQ signal processing circuit comprises a ZYNQ chip and a 33.3MHz crystal oscillator, the ZYNQ chip comprises a PL end and a PS end, and the 33.3MHz crystal oscillator is connected with the PS end;
the storage circuit comprises a DDR3, a QSPI Flash and a first EEPROM, the DDR3 and the QSPI Flash are connected with the PS end of the ZYNQ signal processing circuit, and the first EEPROM is connected with the PL end of the ZYNQ signal processing circuit;
the debugging interface comprises an RS232 serial port, a JTAG debugging interface and a PHY gigabit Ethernet interface, and the RS232 serial port, the JTAG debugging interface and the PHY gigabit Ethernet interface are connected with the PS end of the ZYNQ signal processing circuit;
the backboard communication circuit comprises an analog quantity acquisition circuit, an RS422 serial port, a CPCI communication circuit and a second EEPROM, wherein the analog quantity acquisition circuit, the RS422 serial port and the CPCI communication circuit are all connected with a corresponding port of the panel connector and a PL end of the ZYNQ signal processing circuit, and the second EEPROM is electrically connected with the CPCI in a communication way;
the power management circuit comprises a secondary power converter, and two ends of the secondary power converter are respectively connected with the ZYNQ signal processing circuit and the corresponding ports of the panel connector.
2. The ZYNQ-based frequency agile multifunctional general baseband processing device as claimed in claim 1, wherein the device is a board card structure, and communicates with an upper computer through a CPCI bus interface to complete efficient data transmission and control of modules, and the CPCI bus interface has a physical dimension matched with a single-slot 3U board card.
3. The ZYNQ-based frequency agile multifunctional general baseband processing unit according to claim 1, characterized in that the frequency agile chip is AD 9364.
4. The ZYNQ-based frequency agile multi-function general purpose baseband processing unit of claim 1 wherein the first clock distributor and the second clock distributor both use chips of ADCLK846 BCPZ.
5. The ZYNQ-based frequency agile multifunctional general baseband processing unit according to claim 1, wherein the ADC chip is AD 9434.
6. The ZYNQ-based frequency agile multifunctional general baseband processing device as claimed in claim 1, characterized in that the driving chip is SN74AHC1G 04.
7. The ZYNQ-based frequency-agile multifunctional general baseband processing unit as claimed in claim 1, wherein the ZYNQ chip is XC7Z100-2FFG 900I.
8. The ZYNQ-based frequency agile multi-function general baseband processing apparatus of claim 1 wherein the panel connector comprises a first port, a second port, a third port, a fourth port, a fifth port, a sixth port, a seventh port, an eighth port, and a ninth port, the first port, the second port, the third port, and the fourth port are respectively disposed in the frequency agile circuit and located on a panel board front side, the fifth port is disposed in the clock distribution circuit and located on a panel board front side, the sixth port is disposed in the ADC acquisition circuit and located on a panel board front side, and the seventh port is disposed in the level conversion circuit and located on a panel board front side; the eighth port and the ninth port are located on the rear panel of the board card.
9. The ZYNQ-based frequency agile multi-function general baseband processing device according to claim 1, wherein the first port, the second port, the third port, the fourth port, the fifth port, the sixth port and the seventh port of the panel connector are SMP-JWHD semi-escapement type radio frequency connectors.
10. The ZYNQ-based frequency agile multi-function general baseband processing unit of claim 1 wherein the ninth port of the panel connector is a J15022101 type connector.
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| CN202210607918.7A CN114995235A (en) | 2022-05-31 | 2022-05-31 | Multi-functional general baseband processing apparatus of frequency agility based on ZYNQ |
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| CN202210607918.7A CN114995235A (en) | 2022-05-31 | 2022-05-31 | Multi-functional general baseband processing apparatus of frequency agility based on ZYNQ |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116627071A (en) * | 2023-05-27 | 2023-08-22 | 上海垚智电子科技有限公司 | Communication board card subassembly convenient to maintain |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116627071A (en) * | 2023-05-27 | 2023-08-22 | 上海垚智电子科技有限公司 | Communication board card subassembly convenient to maintain |
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