CN213877833U - High-voltage lead ceramic dielectric capacitor - Google Patents
High-voltage lead ceramic dielectric capacitor Download PDFInfo
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- CN213877833U CN213877833U CN202022783265.7U CN202022783265U CN213877833U CN 213877833 U CN213877833 U CN 213877833U CN 202022783265 U CN202022783265 U CN 202022783265U CN 213877833 U CN213877833 U CN 213877833U
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- capacitor
- chip
- layer
- lead wire
- ceramic dielectric
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- 239000003990 capacitor Substances 0.000 title claims abstract description 65
- 239000000919 ceramic Substances 0.000 title claims description 16
- 239000010410 layer Substances 0.000 claims abstract description 30
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000011241 protective layer Substances 0.000 claims abstract description 19
- 238000005538 encapsulation Methods 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 238000010891 electric arc Methods 0.000 abstract description 5
- 229910052573 porcelain Inorganic materials 0.000 abstract description 4
- 238000003466 welding Methods 0.000 abstract description 4
- 239000003292 glue Substances 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000003085 diluting agent Substances 0.000 description 7
- 230000035882 stress Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000011087 paperboard Substances 0.000 description 3
- 238000007598 dipping method Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000003756 stirring Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002845 discoloration Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000005871 repellent Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000013464 silicone adhesive Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Images
Abstract
The utility model relates to a condenser technical field provides a high pressure lead wire porcelain dielectric capacitor, including capacitor chip, welding to capacitor chip upper electrode layer the lead wire and the encapsulated layer of encapsulating capacitor chip and lead wire end, its characterized in that: still be equipped with insulating protective layer between capacitor chip and lead wire and the encapsulated layer, the utility model discloses an insulating protective layer protects high voltage lead wire porcelain dielectric capacitor inner chip to play and prevent electric arc, dampproofing and release mechanical stress's effect.
Description
Technical Field
The utility model relates to a condenser technical field particularly, relates to a high-voltage lead wire porcelain dielectric capacitor.
Background
The high-voltage multilayer ceramic dielectric capacitor has the advantages of high working voltage (more than 3000V), small volume, large capacity, low ESR/ESL and the like, and has the functions of tuning, coupling, impedance matching, direct current blocking, filtering and the like in circuits such as a switching power supply, a high-frequency amplifier, antenna tuning and the like. The lead product is mainly used in a circuit with large space allowance, and the defects of cracks and the like caused by thermal shock are avoided because the capacitor body is not directly contacted with high temperature during installation. As shown in fig. 1, because the conventional high-voltage lead ceramic dielectric capacitor has a single structure, the interior of the capacitor chip is not completely compact after being subjected to epoxy encapsulation molding after a lead is welded, air gaps are caused by shrinkage stress differences of an encapsulating material and a ceramic body in a high-temperature and high-humidity severe environment, and the encapsulation layer is damaged due to flashover easily caused by overhigh electrical stress.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a high voltage lead wire ceramic dielectric capacitor, it protects high voltage lead wire ceramic dielectric capacitor inner chip through insulating protective layer to play and prevent electric arc, dampproofing and release the effect of mechanical stress.
The embodiment of the utility model discloses a realize through following technical scheme: the utility model provides a high pressure lead wire ceramic dielectric capacitor, includes capacitor chip, welds the lead wire to the upper electrode layer of capacitor chip and encapsulates the encapsulation layer of capacitor chip and lead wire end, its characterized in that: an insulating protective layer is arranged between the capacitor chip and the lead and between the capacitor chip and the encapsulating layer.
Further, the thickness of the insulating protection layer is smaller than that of the encapsulating layer.
Furthermore, the insulating protective layer is made of an electric waterproof adhesive.
Further, the insulating layer is a mixture of an electrically-repellent glue and a diluent.
Further, the thickness of the insulating protection layer at the corners of the capacitor chip is not less than the thickness of the insulating protection layer on the remaining planes.
Furthermore, two capacitor chips with the same specification are arranged, the two capacitor chips are adhered into a whole, and the lead is welded at the adhering gap of the two capacitor chips.
Furthermore, the solder on the lead wires is fully distributed on the electrode layers on the end surfaces of the two capacitor chips.
The utility model discloses technical scheme has following advantage and beneficial effect at least: optimize lead wire product inner structure, protect high-voltage lead wire porcelain dielectric capacitor inner chip, through the mode coating protection glue that soaks, form the insulating protective layer of one deck compactness after the thermal treatment solidification, become one deck protection architecture between chip and the encapsulated layer to play the effect of preventing electric arc, dampproofing and release mechanical stress.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a conventional capacitor;
fig. 2 is a schematic structural view of the capacitor before encapsulation according to the present invention;
fig. 3 is a schematic diagram of the cross-sectional structure of the encapsulated capacitor provided by the present invention;
fig. 4 is a schematic structural diagram of two capacitors before encapsulation according to the present invention;
icon: 1-capacitor chip, 11-first capacitor chip, 12-second capacitor chip, 2-lead, 3-encapsulating layer and 4-insulating protective layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the position or positional relationship based on the position or positional relationship shown in the drawings, or the position or positional relationship which is usually placed when the product of the present invention is used, the description is only for convenience of description and simplification, but the indication or suggestion that the device or element to be referred must have a specific position, be constructed and operated in a specific position, and thus, cannot be understood as a limitation of the present invention.
In the description of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Examples
The utility model provides a high-voltage lead 2 ceramic dielectric capacitor, includes capacitor chip 1, welds to capacitor chip 1 on the electrode layer lead wire 2 and encapsulates capacitor chip 1 and the encapsulated layer 3 of lead wire 2 tip, still is equipped with insulating protective layer 4 between capacitor chip 1 and lead wire 2 and the encapsulated layer 3, and it protects high-voltage lead 2 ceramic dielectric capacitor internal chip through insulating protective layer 4 to play and prevent electric arc, dampproofing and release mechanical stress's effect.
Specifically, the insulating protective layer 4 is a mixture of an electric glue and a diluent, such as CE-1171 electronic insulating protective glue and a special diluent thereof, and the thickness of the formed insulating protective layer 4 is smaller than that of the encapsulating layer 3, so that the encapsulating layer 3 provides mechanical support; further, the thickness of the insulating protection layer 4 at the corner of the capacitor chip 1 is not less than that of the insulating protection layer 4 on the rest planes, and due to the viscosity of the fluid, the amount of the insulating protection glue at the corner is often insufficient, so that sharp discharge can be caused under the condition of high pressure, and flash due to penetration; meanwhile, the possibility that air cracks appear on the edges due to expansion caused by heat and contraction caused by cold due to the fact that infiltration is insufficient and combination is not tight because of the spatial relationship can be avoided; for example, in the actual production process, the thickness of the insulating protective layer on the rest plane is generally 0.15 mm-0.2 mm, and too thin thickness can reduce the insulating performance and not achieve the protection effect, whereas too thick thickness can cause the structure of the encapsulating layer 3 to be abnormal due to the viscosity of the fluid.
Specifically, in this embodiment, the step of wrapping the insulating protective adhesive is as follows:
after the chip is welded with the lead 2, the chip and a welding spot are required to be clean, no impurities or flux residues are needed, and if the requirement is not met, the chip needs to be cleaned until the requirement is met.
And step two, preparing protective glue, preparing the protective glue and the diluent according to the proportion of 1: 1, mixing the protective glue and the diluent in a beaker according to the required using amount, putting the paperboard strips into a clean plastic sealing bag, and uniformly stirring the prepared protective glue by using the paperboard strips sleeved with the plastic sealing bag, wherein the stirring time is not less than 1 min.
And step three, orderly arranging and adhering the ends of the product leads 2 to the paperboard strips, and dipping the strips as units. The chip body is downward, the chip is slowly immersed into the protective adhesive, the immersion speed is controlled to be (4-6) cm/s, the immersion time is controlled to be (2-3) s, the distance between the bottom end of the chip and the liquid level of the protective adhesive cannot exceed 2mm, then the product is lifted, and the lifting speed is controlled to be (4-6) cm/s.
And step four, suspending the product on a curing frame in a mode that the chip body faces downwards after dipping, and naturally drying for 60-90 min. And after the protective glue is leveled and solidified, putting the protective glue into an oven for curing the protective glue. The temperature of the oven is required to be (115 +/-10) DEG C, and the curing time is required to be (1.5-2) h. And (5) curing, normally encapsulating and finally forming.
Specifically, in the present embodiment, the criterion of the insulating protective layer 4 formed by mixing the electric resist and the diluent is as follows: moisture resistance: no discoloration, softening, surface tack, chalking, blistering, cracking or loss of adhesion at 160 ° f and 95% relative humidity for 120 days; flexibility: no crack is generated when the material is bent for 1/8 inches; temperature resistance: the crack, the bubble, the wrinkle and the peeling can not be generated in the circulation test at the temperature of-65 ℃ to 125 ℃; flame resistance: self-extinguishing property; solderability: the method is excellent; thickness: 0.15 mm-0.2 mm; dielectric constant: 2.5-3; loss factors: 0.01(100 Hz); volume resistance: 2X 1015Ω/cm。
In some embodiments, in order to increase the capacity of the capacitor, two capacitor chips 1 of the same specification are provided, as shown in fig. 4, including a first capacitor chip 11 and a second capacitor chip 12; the two capacitor chips 1 are adhered into a whole, the lead 2 is welded at the adhering gap of the two capacitor chips 1, and the welding flux on the lead 2 is fully distributed on the electrode layers of the two capacitor chips 1; the specific intermediate adhesive is, but not limited to, silicone adhesive and epoxy resin, and in the present embodiment, the above-mentioned electric waterproof adhesive or a mixture of the electric waterproof adhesive and a diluent is used, and the intermediate adhesive is used to buffer the mechanical stress and the thermal stress during welding, and simultaneously, two capacitors of the same specification are insulated, and two insulating protective layers 4 are used to avoid the influence between the two capacitors and the possibility of electric arc generation.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. The utility model provides a high pressure lead wire ceramic dielectric capacitor, includes capacitor chip, welds the lead wire to the upper electrode layer of capacitor chip and encapsulates the encapsulation layer of capacitor chip and lead wire end, its characterized in that: and an insulating protective layer is arranged between the capacitor chip and the encapsulating layer and between the lead and the encapsulating layer.
2. The high voltage lead ceramic dielectric capacitor of claim 1 wherein the insulating protective layer has a thickness less than the thickness of the encapsulation layer.
3. The high voltage lead ceramic dielectric capacitor of claim 2 wherein said insulating protective layer is an electrical resist.
4. The high voltage lead ceramic dielectric capacitor of claim 3, wherein the thickness of the insulating protective layer at the corners of the capacitor chip is not less than the thickness of the insulating protective layer on the remaining planes.
5. The high voltage lead ceramic dielectric capacitor as claimed in any one of claims 1 to 4, wherein there are two capacitor chips of the same size, the two capacitor chips are bonded together and the lead is soldered at the bonding gap between the two capacitor chips.
6. The high voltage leaded ceramic dielectric capacitor of claim 5 wherein the solder on said leads is spread over the electrode layers on both said capacitor chip end faces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022783265.7U CN213877833U (en) | 2020-11-26 | 2020-11-26 | High-voltage lead ceramic dielectric capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022783265.7U CN213877833U (en) | 2020-11-26 | 2020-11-26 | High-voltage lead ceramic dielectric capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213877833U true CN213877833U (en) | 2021-08-03 |
Family
ID=77039827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022783265.7U Active CN213877833U (en) | 2020-11-26 | 2020-11-26 | High-voltage lead ceramic dielectric capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213877833U (en) |
-
2020
- 2020-11-26 CN CN202022783265.7U patent/CN213877833U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A high voltage lead ceramic dielectric capacitor Effective date of registration: 20230131 Granted publication date: 20210803 Pledgee: Chenghua sub branch of Bank of Chengdu Co.,Ltd. Pledgor: Chengdu Hongke Electronic Technology Co.,Ltd. Registration number: Y2023510000037 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20231205 Granted publication date: 20210803 Pledgee: Chenghua sub branch of Bank of Chengdu Co.,Ltd. Pledgor: Chengdu Hongke Electronic Technology Co.,Ltd. Registration number: Y2023510000037 |