CN213782866U - MOS delay protection circuit - Google Patents
MOS delay protection circuit Download PDFInfo
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- CN213782866U CN213782866U CN202022987260.6U CN202022987260U CN213782866U CN 213782866 U CN213782866 U CN 213782866U CN 202022987260 U CN202022987260 U CN 202022987260U CN 213782866 U CN213782866 U CN 213782866U
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Abstract
The utility model provides a MOS delay protection circuit, which comprises a protection circuit control chip and an MOS tube, wherein the protection circuit control chip is respectively connected with a monitoring signal and a grid electrode of the MOS tube, and a drain electrode and a source electrode of the MOS tube are respectively connected with an input end and an output end of a detection signal; the protection circuit further comprises an MOS protection module, and the MOS protection module is connected with the grid of the MOS tube. The utility model discloses an add MOS protection module at the grid of MOS pipe, make the opening time delay of MOS, the closing time shortens to protection MOS effectively solves the problem that MOS pipe easily damaged among the protective circuit.
Description
Technical Field
The utility model belongs to the technical field of the protection circuit design technique and specifically relates to a MOS delay protection circuit.
Background
With the development of cloud computing applications, informatization gradually covers various fields of society. People's daily life and daily life are more and more communicated through the network, and the network data volume is also increasing continuously. With the improvement of the computing power of the server, the power consumption of the server is larger and larger, and the current on the mainboard is also larger and larger.
The current increase on the mainboard can bring a series of problems, and the whole temperature of system risees, and the local high temperature that the heavy current arouses is too high, causes input circuit's heat accumulation because of input current is too big even, finally leads to the PCB board to burn out.
In order to protect the system power supply, a power supply protection circuit is introduced into the design of the main board, as shown in fig. 1, a protection circuit control chip is connected with an MOS transistor, and the purpose of protecting the circuit is achieved by timely power-off. However, since the load at the back end is very large, the surge current of the protection circuit is too large at the moment of switching, which easily causes damage to the MOS.
SUMMERY OF THE UTILITY MODEL
The utility model provides a MOS delays protection circuit for solve among the current protection circuit the fragile problem of MOS pipe.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
the utility model provides a MOS delay protection circuit, which comprises a protection circuit control chip and an MOS tube, wherein the protection circuit control chip is respectively connected with a monitoring signal and a grid electrode of the MOS tube, and a drain electrode and a source electrode of the MOS tube are respectively connected with an input end and an output end of a detection signal; the protection circuit is characterized by further comprising an MOS protection module, wherein the MOS protection module is connected with the grid of the MOS tube.
Further, the MOS protection module includes a diode D1, a transistor Q, and a capacitor C, the anode of the diode D1 is connected to the gate of the MOS transistor and the base of the transistor Q, the cathode of the diode D1 is connected to the emitter of the transistor Q and one end of the capacitor C, and the collector of the transistor Q and the other end of the capacitor C are both grounded.
Further, the triode is a PNP type triode.
Furthermore, the MOS protection module further includes a current-limiting resistor R, and two ends of the current-limiting resistor R are respectively connected to the anode of the diode D and the base of the triode Q.
Further, the protection circuit further comprises delay capacitors C1 and C2, two ends of the capacitor C1 are respectively connected with the output end of the monitoring signal and the ground, and the capacitor C2 is connected with the capacitor C1 in parallel.
Further, the protection circuit further comprises a diode D2, wherein the anode of the diode D2 is grounded, and the cathode of the diode D2 is connected with the input end of the monitoring signal.
The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:
the utility model discloses an add MOS protection module at the grid of MOS pipe, make the opening time delay of MOS, the closing time shortens to protection MOS effectively solves the problem that MOS pipe easily damaged among the protective circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit schematic of a prior art protection circuit;
fig. 2 is a schematic circuit diagram of the protection circuit of the present invention.
Detailed Description
In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.
As shown in fig. 2, the MOS delay protection circuit of the present invention includes a protection circuit control chip and an MOS transistor, wherein the protection circuit control chip is connected to the monitor signal and the gate of the MOS transistor respectively, and the drain and the source of the MOS transistor are connected to the input and the output of the detection signal respectively; the protection circuit further comprises an MOS protection module, and the MOS protection module is connected with the grid of the MOS tube.
The MOS protection module comprises a diode D1, a triode Q and a capacitor C, wherein the anode of the diode D1 is respectively connected with the grid of the MOS tube and the base of the triode Q, the cathode of the diode D1 is respectively connected with the emitting electrode of the triode Q and one end of the capacitor C, and the collecting electrode of the triode Q and the other end of the capacitor C are both grounded.
The triode Q is a PNP type triode.
In order to protect the circuit safety, the MOS protection module further comprises a current-limiting resistor R, and two ends of the current-limiting resistor R are respectively connected with the anode of the diode D and the base of the triode Q.
The protection circuit further comprises delay capacitors C1 and C2, wherein two ends of the capacitor C1 are respectively connected with the output end of the monitoring signal and the ground, and the capacitor C2 is connected with the capacitor C1 in parallel.
The protection circuit further comprises a diode D2, wherein the anode of the diode D2 is grounded, and the cathode of the diode D2 is connected with the input end of the monitoring signal.
The utility model discloses protection circuit's theory of operation does: when the protection circuit is started, the grid electrode (Gate end) of the MOS tube is at a high level, at the moment, the end b and the end e of the PNP tube are separated by the diode, so Ve is smaller than Vb, the PNP tube is not conducted, the capacitor C is charged through the diode to start time delay for the Gate end of the MOS tube, and the MOS tube is protected from being damaged due to overlarge surge current.
When the protection circuit is closed, the voltage at the Gate end becomes low at the moment, but the voltage at the capacitor end cannot change suddenly, due to the existence of the diode D1, the diode D1 cannot be conducted reversely, Ve > Vb at the moment, the PNP tube is conducted, the electricity at the Gate end can be rapidly discharged in the forward direction through the diode D1, the MOS tube is rapidly closed, the MOS tube is short in closing time, the MOS cannot exceed an SOA (safe operating area) area, and the risk of damage cannot occur.
Although the present invention has been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without inventive work are still within the scope of the present invention.
Claims (6)
1. A MOS delay protection circuit comprises a protection circuit control chip and an MOS tube, wherein the protection circuit control chip is respectively connected with a monitoring signal and a grid electrode of the MOS tube, and a drain electrode and a source electrode of the MOS tube are respectively connected with an input end and an output end of a detection signal; the protection circuit is characterized by further comprising an MOS protection module, wherein the MOS protection module is connected with the grid of the MOS tube.
2. The MOS delay protection circuit of claim 1, wherein the MOS protection module comprises a diode D1, a transistor Q and a capacitor C, the anode of the diode D1 is connected to the gate of the MOS transistor and the base of the transistor Q, respectively, the cathode of the diode D1 is connected to the emitter of the transistor Q and one end of the capacitor C, respectively, and the collector of the transistor Q and the other end of the capacitor C are grounded.
3. The MOS delay protection circuit of claim 2, wherein the transistor is a PNP transistor.
4. The MOS delay protection circuit of claim 2, wherein the MOS protection module further comprises a current limiting resistor R, and both ends of the current limiting resistor R are respectively connected to the anode of the diode D and the base of the transistor Q.
5. The MOS delay protection circuit of claim 1, wherein the protection circuit further comprises delay capacitors C1 and C2, the two terminals of the capacitor C1 are respectively connected to the output terminal of the monitor signal and the ground, and the capacitor C2 is connected in parallel with the capacitor C1.
6. The MOS delay protection circuit of claim 1, wherein the protection circuit further comprises a diode D2, the anode of the diode D2 is grounded, and the cathode of the diode D2 is connected to the input terminal of the monitoring signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022987260.6U CN213782866U (en) | 2020-12-11 | 2020-12-11 | MOS delay protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022987260.6U CN213782866U (en) | 2020-12-11 | 2020-12-11 | MOS delay protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213782866U true CN213782866U (en) | 2021-07-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022987260.6U Active CN213782866U (en) | 2020-12-11 | 2020-12-11 | MOS delay protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213782866U (en) |
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2020
- 2020-12-11 CN CN202022987260.6U patent/CN213782866U/en active Active
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