CN212676883U

CN212676883U - Overcurrent protection and delay recovery circuit and power supply equipment

Info

Publication number: CN212676883U
Application number: CN202021796141.6U
Authority: CN
Inventors: 黄强
Original assignee: Shanghai Tongli Information Technology Co ltd
Current assignee: Shanghai Tongli Information Technology Co ltd
Priority date: 2020-08-25
Filing date: 2020-08-25
Publication date: 2021-03-09
Anticipated expiration: 2030-08-25

Abstract

The utility model provides an overcurrent protection and time delay recovery circuit and power supply unit, include: the current sampling element F1, the overcurrent protection element, the comparator U1A, the MOS tube Q1, the triode Q2 and the reset chip U2; the current sampling element F1, the overcurrent protection element and the MOS tube Q1 are sequentially connected in series in a protected loop; a first input end of the comparator U1A is connected between the overcurrent protection element and the MOS tube Q1, a second input end of the comparator U1A is connected with a reference voltage V _ REF, an output end of the comparator U1A is connected with an MR pin of the reset chip U2, and a reset output pin of the reset chip U2 is connected with a base electrode of the triode Q2; the collector of the transistor Q2 is connected to the gate of the MOS transistor Q1. Utilize the characteristic of chip itself that resets, through the utility model discloses a structural design does not need additionally to increase under the condition of controller like MCU, CPU, can realize overcurrent protection delay recovery.

Description

Overcurrent protection and delay recovery circuit and power supply equipment

Technical Field

The utility model relates to an electronic circuit field specifically relates to an overcurrent protection and time delay recovery circuit and power supply unit.

Background

Overcurrent Protection (Over Current Protection) is a Protection mode for operating a Protection device when a Current exceeds a predetermined maximum value. Common short-circuit protection is generally of two types:

firstly, a self-recovery fuse PPTC: when the circuit works normally, its resistance value is very small, and when the circuit is over-current, its temperature is raised, and its resistance value is sharply increased by several orders of magnitude, so that the current in the circuit can be reduced below safety value, so that the following circuit can be protected, and after the over-current is disappeared, it can automatically recover to low resistance value. Possible failure conditions for the self-healing fuse are: the failure is represented by the performance parameter reduction or the disconnection after a plurality of actions, continuous long-time actions, voltage exceeding the rated working voltage Vmax and fault current exceeding the rated action current Imax. If the overcurrent condition continues for a long time, the self-recovery fuse will continue to generate heat, which will affect the life of the fuse. Meanwhile, long-time heating brings risks to some systems with high heat dissipation requirements.

Secondly, an overcurrent protection circuit consisting of a sampling resistor and an operational amplifier/comparator: the sampling resistor is connected in series in a load loop, current is converted into voltage for sampling, and corresponding comparison processing is carried out through an operational amplifier/comparator, so that a switching circuit connected in series in the loop is controlled to realize protection action after overcurrent. Compared with the PPTC, the circuit has higher precision and faster action, but when the overcurrent state lasts, the switch circuit is always in a closed and opened cyclic state, and the frequency is fast and uncontrollable. This continuous, rapid cycling of the closing and opening actions can affect the stability of the system, particularly the back-end circuitry or components. In some scenarios, software control may also be implemented by using a controller MCU, a CPU, or the like, but if the controller is added separately, the cost will increase a lot.

SUMMERY OF THE UTILITY MODEL

To the defect among the prior art, the utility model aims at providing an overcurrent protection and time delay recovery circuit and power supply unit.

According to the utility model provides a pair of overcurrent protection and time delay recovery circuit, include: the current sampling element F1, the overcurrent protection element, the comparator U1A, the MOS tube Q1, the triode Q2 and the reset chip U2;

the current sampling element F1, the overcurrent protection element and the MOS tube Q1 are sequentially connected in series in a protected loop;

a first input end of the comparator U1A is connected between the overcurrent protection element and the MOS transistor Q1, a second input end of the comparator U1A is connected with a reference voltage V _ REF, an output end of the comparator U1A is connected with an MR pin of the reset chip U2, and a reset output pin of the reset chip U2 is connected with a base electrode of the triode Q2;

the collector of the triode Q2 is connected with the gate of the MOS transistor Q1.

Preferably, the MOS transistor Q1 is a PMOS transistor, and the source of the MOS transistor Q1 is connected to the overcurrent protection element;

the outer end of the current sampling element F1 is used as a voltage input end, and the drain electrode of the MOS transistor Q1 is used as a voltage output end.

Preferably, the method further comprises the following steps: a resistor R1, a resistor R3 and a capacitor C2;

one end of the resistor R1 is connected between the overcurrent protection element and the MOS transistor Q1, the other end of the resistor R1 is grounded through the resistor R3, the capacitor C2 is connected in parallel with the resistor R3, and a first input end of the comparator U1A is connected between the resistor R1 and the resistor R3.

Preferably, the method further comprises the following steps: a resistor R5, a resistor R6 and a capacitor C3;

the resistor R5 is connected in series between the reset output pin of the reset chip U2 and the base of the triode Q2, one end of the resistor R6 and one end of the capacitor C3 are respectively connected between the resistor R5 and the base of the triode Q2, and the other end of the resistor R6 and the base of the triode Q2 are grounded.

Preferably, the emitter of the transistor Q2 is grounded.

Preferably, the method further comprises the following steps: the resistor R4, the resistor R4 is connected between the collector of the triode Q2 and the gate of the MOS tube in series.

Preferably, the device further comprises a resistor R2 and a capacitor C1;

the resistor R2 and the capacitor C1 are connected in parallel, one end of the resistor R2 is connected between the collector of the triode Q2 and the gate of the MOS transistor Q1, and the other end of the resistor R2 is used as a voltage input end.

Preferably, the method further comprises the following steps: a resistor R7 and a resistor R8;

one end of the resistor R7 is used as a voltage input end, the other end is grounded through the resistor R8, and the second input end of the comparator U1A is connected between the resistor R7 and the resistor R8.

Preferably, the overcurrent protection element comprises a self-recovery fuse.

The power supply equipment provided by the invention comprises an overcurrent protection and delay recovery circuit.

Compared with the prior art, the utility model discloses following beneficial effect has:

1. utilize the characteristic of chip itself that resets, through the utility model discloses a structural design does not need additionally to increase under the condition of controller like MCU, CPU, can realize overcurrent protection time delay and resume to alleviate system's power supply pressure, improve the protection component life-span, reduce that the component generates heat, improve system stability.

2. When the load overcurrent phenomenon exists, the front-end circuit is protected from being influenced by the rear-end overcurrent, and the influence of frequent switching of a protection device on a system, particularly a rear-end circuit or parts is reduced.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a circuit diagram of the present invention;

FIG. 2 is a schematic diagram illustrating a manner of obtaining a reference voltage;

FIG. 3 is a schematic circuit diagram of the comparator;

fig. 4 is a reset timing diagram of the reset chip.

Detailed Description

The present invention will be described in detail with reference to the following embodiments. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that various changes and modifications can be made by one skilled in the art without departing from the spirit of the invention. These all belong to the protection scope of the present invention.

As shown in fig. 1 to fig. 3, the utility model provides a pair of overcurrent protection and delay recovery circuit mainly includes: the current sampling element F1, the overcurrent protection element, the comparator U1A, the MOS tube Q1, the triode Q2 and the reset chip U2.

The current sampling element F1, the overcurrent protection element PPTC and the MOS tube Q1 are sequentially connected in series in a protected loop, and the MOS tube Q1 adopts a PMOS tube and is used as a power switch. The source of the MOS transistor Q1 is connected to the overcurrent protection element PPTC (PPTC is a self-recovery fuse, but the present invention is not limited thereto), the outer end of the current sampling element F1 serves as the voltage input terminal 12V, and the drain of the MOS transistor Q1 serves as the voltage output terminal 12V _ OUT. Compared with the method that the sampling is realized by using a resistor, the method has the advantages of lower resistance, higher efficiency and smaller influence on a circuit under the normal working state.

The first input end of the comparator U1A is connected between the overcurrent protection element and the MOS tube Q1, the second input end of the comparator U1A is connected with the reference voltage V _ REF, the output end of the comparator U1A is connected with the MR pin of the reset chip U2, the reset output pin of the reset chip U2 is connected with the base electrode of the triode Q2, the collector electrode of the triode Q2 is connected with the grid electrode of the MOS tube Q1, and the emitter electrode of the triode Q2 is grounded. The positive and negative input ends of the comparator are respectively connected with the front and the back of the fuse, and the action threshold can be more conveniently set by adopting a voltage division circuit.

One end of the resistor R1 is connected between the overcurrent protection element and the MOS transistor Q1, the other end of the resistor R1 is grounded through the resistor R3, the capacitor C2 is connected with the resistor R3 in parallel, and the first input end of the comparator U1A is connected between the resistor R1 and the resistor R3.

The resistor R5 is connected in series between the reset output pin of the reset chip U2 and the base of the triode Q2, one end of the resistor R6 and one end of the capacitor C3 are respectively connected between the resistor R5 and the base of the triode Q2, and the other end of the resistor R6 and the other end of the capacitor C3 are grounded.

The resistor R4 is connected in series between the collector of the transistor Q2 and the gate of the MOS transistor.

As shown in fig. 4, since the reset chips all have a longer reset time (different types of chips have different times and can be selected as required). The invention utilizes the reset time to convert the output signal of the comparator into a control signal with longer time delay to control the opening and closing of the Q1. Therefore, when the overcurrent exists continuously, the PPTC and the MOS tube can recover power supply at a slower speed, the heat generation is reduced, the service life of the element is prolonged, the power supply pressure is relieved, and the system stability is improved.

In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

The foregoing description of the specific embodiments of the invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. An overcurrent protection and delay recovery circuit, comprising: the current sampling element F1, the overcurrent protection element, the comparator U1A, the MOS tube Q1, the triode Q2 and the reset chip U2;

2. The overcurrent protection and delay recovery circuit of claim 1, wherein the MOS transistor Q1 is a PMOS transistor, and the source of the MOS transistor Q1 is connected to the overcurrent protection element;

3. The overcurrent protection and delay recovery circuit of claim 1, further comprising: a resistor R1, a resistor R3 and a capacitor C2;

4. The overcurrent protection and delay recovery circuit of claim 1, further comprising: a resistor R5, a resistor R6 and a capacitor C3;

5. The overcurrent protection and delay recovery circuit of claim 1, wherein an emitter of the transistor Q2 is coupled to ground.

6. The overcurrent protection and delay recovery circuit of claim 1, further comprising: the resistor R4, the resistor R4 is connected between the collector of the triode Q2 and the gate of the MOS tube in series.

7. The overcurrent protection and delay recovery circuit of claim 1, further comprising a resistor R2 and a capacitor C1;

8. The overcurrent protection and delay recovery circuit of claim 1, further comprising: a resistor R7 and a resistor R8;

9. The overcurrent protection and delay recovery circuit of claim 1, wherein the overcurrent protection element comprises a self-healing fuse.

10. A power supply device comprising the overcurrent protection and delay recovery circuit as set forth in any one of claims 1 to 9.