CN214069562U - A power failure protection circuit and integrated chip - Google Patents
A power failure protection circuit and integrated chip Download PDFInfo
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- CN214069562U CN214069562U CN202022655417.5U CN202022655417U CN214069562U CN 214069562 U CN214069562 U CN 214069562U CN 202022655417 U CN202022655417 U CN 202022655417U CN 214069562 U CN214069562 U CN 214069562U
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Abstract
本实用新型实施例公开了一种掉电保护电路与集成芯片，掉电保护电路用于与控制单元的复位信号输入端以及电源端连接，掉电保护电路包括第一调压电路、供电控制电路、第二调压电路与复位控制电路，第一调压电路用于将电压源的输入电压进行转换，以使第一调压电路的输出端输出第一电压，供电控制电路用于根据第一电压控制控制单元得电或失电，第二调压电路用于将第一电压进行转换，以使第二调压电路的输出端输出第二电压，第二电压用于为控制单元提供供电电压，复位控制电路用于根据第二电压输出复位控制信号至控制单元。通过上述方式，能够采用简单的纯硬件电路实现电子产品的掉电保护，且成本较低，体积较小。
The embodiment of the utility model discloses a power failure protection circuit and an integrated chip. The power failure protection circuit is used for connecting with a reset signal input terminal and a power supply terminal of a control unit, and the power failure protection circuit includes a first voltage regulation circuit and a power supply control circuit. , a second voltage regulating circuit and a reset control circuit, the first voltage regulating circuit is used to convert the input voltage of the voltage source so that the output terminal of the first voltage regulating circuit outputs the first voltage, and the power supply control circuit is used to The voltage control control unit is powered on or off, and the second voltage regulating circuit is used to convert the first voltage, so that the output end of the second voltage regulating circuit outputs a second voltage, and the second voltage is used to provide a power supply voltage for the control unit , the reset control circuit is used for outputting a reset control signal to the control unit according to the second voltage. In the above manner, a simple pure hardware circuit can be used to realize the power-off protection of the electronic product, and the cost is low and the volume is small.
Description
Technical Field
The utility model relates to a power electronic technology field especially relates to a power down protection circuit and integrated chip.
Background
In the using process of electronic products, the requirements of users on the stability and safety of the performance of the electronic products are higher and higher. In the use process, when abnormal operation or abnormal power failure occurs, intelligent protection of electronic products is generally required. Therefore, some engineers adopt a dual-power loop power supply scheme in the design of the MCU power supply loop, namely, adopt a power supply loop design in which a main power supply and a standby power supply are mutually compatible, and detect two paths of power supply loops in real time in a software control strategy, so as to ensure the stable and safe operation of an electronic product.
However, although the design scheme of the dual power supply circuit is feasible, both the hardware circuit design and the software control strategy are complex, and the cost is high, the size is large, and the development of low cost and small size of the electronic product is not facilitated.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a aim at providing a power down protection circuit and integrated chip, can adopt simple pure hardware circuit to realize the power down protection of electronic product, and the cost is lower, and the volume is less.
In order to achieve the above object, in a first aspect, the utility model provides a power down protection circuit, power down protection circuit is used for being connected with the reset signal input part and the power end of the control unit, power down protection circuit includes:
the first voltage regulating circuit is connected with a voltage source and used for converting the input voltage of the voltage source so as to enable the output end of the first voltage regulating circuit to output a first voltage;
the power supply control circuit is connected with the first voltage regulating circuit and is used for controlling the control unit to be powered on or powered off according to the first voltage;
the second voltage regulating circuit is respectively connected with the power supply control circuit and a power supply end of the control unit, and is used for converting the first voltage so as to enable an output end of the second voltage regulating circuit to output a second voltage, and the second voltage is used for providing power supply voltage for the control unit;
and the reset control circuit is respectively connected with the second voltage regulating circuit and the reset signal input end of the control unit, and is used for outputting a reset control signal to the control unit according to the second voltage.
In an optional mode, the power supply control circuit includes a first signal generating circuit and a first switching circuit, an input end of the first signal generating circuit is connected with an output end of the first voltage regulating circuit, an output end of the first signal generating circuit is connected with an input end of the first switching circuit, and an output end of the first switching circuit is connected with the second voltage regulating circuit;
the first signal generating circuit is used for outputting a switching signal according to the first voltage so as to control the switching state of the first switching circuit.
In an alternative mode, the first signal generating circuit includes a first comparator and a first zener diode;
the non inverting input end of the first comparator is respectively connected with the cathode of the first voltage stabilizing diode and the voltage source, the inverting input end of the first comparator is connected with the output end of the first voltage regulating circuit, the output end of the first comparator is connected with the input end of the first switch circuit, and the anode of the first voltage stabilizing diode is grounded.
In an optional mode, the first switching circuit includes a first switching tube, a second switching tube and a third switching tube;
the control end of the first switch tube is connected with the output end of the first comparator, the first end of the first switch tube is grounded, and the second end of the first switch tube is connected with the control end of the second switch tube;
the first end of the second switching tube is grounded, and the second end of the second switching tube is connected with the control end of the third switching tube;
the first end of the third switching tube is connected with the input end of the second voltage regulating circuit, and the second end of the third switching tube is connected with the output end of the first voltage regulating circuit.
In an optional manner, the first switching circuit further includes a first capacitor, and two ends of the first capacitor are respectively connected to the control end and the first end of the first switching tube;
the first capacitor is used for controlling the conduction time of the first switch tube.
In an alternative mode, the reset control circuit includes a second switch circuit and a second signal generating circuit;
the input end of the second switch circuit is connected with the output end of the second voltage regulating circuit, the output end of the second switch circuit is connected with the input end of the second signal generating circuit, and the output end of the second signal generating circuit is connected with the reset signal input end of the control unit;
the second switch circuit is used for switching the switch state according to the second voltage so that the second signal generating circuit outputs a reset signal to the control unit.
In an alternative mode, the second switching circuit comprises a fourth switching tube;
the control end of the fourth switch tube is connected with the output end of the second voltage regulating circuit, the first end of the fourth switch tube is grounded, and the second end of the fourth switch tube is connected with the voltage source.
In an alternative form, the second signal generating circuit includes a second comparator;
the in-phase input end of the second comparator is connected with the output end of the second voltage regulating voltage, the reverse phase input end of the second comparator is connected with the second end of the fourth switching tube, and the output end of the second comparator is connected with the reset signal input end of the control unit.
In an optional manner, the second signal generating circuit further includes a second capacitor, a first end of the second capacitor is connected to the output end of the second comparator, and the other end of the second capacitor is grounded;
the second capacitor is used for controlling the duration of the output end of the second comparator for outputting the reset signal.
In a second aspect, an embodiment of the present invention provides an integrated chip, including a control unit and the power down protection circuit as described above;
the power-down protection circuit is connected with the control unit and used for providing power supply voltage for the control unit and providing reset signals for the control unit.
The embodiment of the utility model provides a beneficial effect is: the utility model provides a power-down protection circuit is used for being connected with the reset signal input end and the power end of the control unit, the power-down protection circuit comprises a first voltage regulating circuit, a power supply control circuit, a second voltage regulating circuit and a reset control circuit, wherein, the first voltage regulating circuit is connected with a voltage source, the first voltage regulating circuit is used for converting the input voltage of the voltage source so as to lead the output end of the first voltage regulating circuit to output a first voltage, the power supply control circuit is connected with the first voltage regulating circuit, the power supply control circuit is used for controlling the power-on or power-off of the control unit according to the first voltage, the second voltage regulating circuit is respectively connected with the power supply control circuit and the power end of the control unit, the second voltage regulating circuit is used for converting the first voltage so as to lead the output end of the second voltage regulating circuit to output a second voltage, the second voltage is used for providing the power supply voltage for the control unit, the reset control circuit is respectively connected with the reset signal input end of the second voltage regulating circuit and the control unit, the reset control circuit is used for outputting a reset control signal to the control unit according to the second voltage, namely when the electronic equipment provided with the power-down protection circuit is powered down, the power supply control circuit can control the control unit to lose power, and meanwhile, the reset control circuit can output the reset control signal to the control unit to control the control unit to reset, so that the control unit is powered down, and forced reset of the control unit is realized.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of an integrated chip and a voltage source according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an integrated chip and a voltage source according to another embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a first voltage regulating circuit according to an embodiment of the present invention;
fig. 4 is a schematic circuit structure diagram of a power supply control circuit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a second voltage regulating circuit according to an embodiment of the present invention;
fig. 6 is a schematic circuit structure diagram of a reset control circuit provided in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an integrated chip and a voltage source according to an embodiment of the present invention, as shown in fig. 1, the integrated chip 100 includes a power down protection circuit 10 and a control unit 20, wherein an input end of the power down protection circuit 10 is connected to the voltage source 200, and the power down protection circuit 10 is connected to the control unit 20.
Specifically, the voltage source 200 is configured to provide an input voltage for the power down protection circuit 10, and the power down protection circuit 10 provides both a supply voltage for the control unit 20 and a reset signal for the control unit 20, for example, a reset signal output terminal of the power down protection circuit 10 is connected to a reset signal input terminal of the control unit 20 through a connection L1 to provide a reset signal for the control unit 20; meanwhile, a voltage input end of the power down protection circuit 10 is connected to a power supply end of the control unit 20 through a connection line L2 to provide a power supply voltage for the control unit 20, i.e., a working voltage of the control unit 20, wherein the control unit 20 may be a single chip Microcomputer (MCU) or the like.
Therefore, if the integrated chip 100 is disposed in an electronic product, when an abnormal power failure occurs in the electronic product, for example, a main power switch trips, which results in an abnormal power failure, at this time, the power down protection circuit 10 can disconnect the connection between the voltage source 200 and the control unit 20, and meanwhile, the power down protection circuit 10 can output a reset signal to forcibly reset the control unit 20, so as to prevent the control unit 20 from entering a sleep or dead-run state for protection. Therefore, the intelligent protection of the electronic product is realized when abnormal power failure occurs, and the electronic product is prevented from being abnormal or damaged.
As shown in fig. 2, the power down protection circuit 10 includes a first voltage regulating circuit 11, a power supply control circuit 12, a second voltage regulating circuit 13 and a reset control circuit 14, wherein the first voltage regulating circuit is connected to an external voltage source 200, the power supply control circuit 12 is respectively connected to the first voltage regulating circuit 11 and the second voltage regulating circuit 13, the second voltage regulating circuit is connected to a power supply terminal of the control unit 20, and the reset control circuit 14 is respectively connected to the second voltage regulating circuit 13 and a reset signal input terminal of the control unit.
Specifically, the first voltage regulating circuit 11 is configured to convert the input voltage of the voltage source 200, so that the output terminal of the first voltage regulating circuit 11 outputs the first voltage. Since the voltage source 200 generally cannot be directly used to directly supply power to each module in the power down protection circuit 10 or the control unit 20, a corresponding circuit needs to be provided to convert the voltage of the voltage source 200 to meet the voltage requirements of different circuits, for example, the first voltage regulating circuit 11 is provided as a module circuit that converts direct current into direct current.
The first voltage regulating circuit 11 is formed by using a three-terminal regulator ic.
As shown in fig. 3, an input terminal Vin of the first three-terminal regulated integrated chip U1, that is, the 3 rd pin of the first three-terminal regulated integrated chip U1, is connected to the voltage source 200, and an input voltage V0 of the voltage source 200 passes through the first energy storage capacitor EC1 and the first filter capacitor C1 and then is input to the 3 rd pin of the first three-terminal regulated integrated chip U1, wherein the first energy storage capacitor EC1 is used to store energy and release the energy when necessary to keep the input voltage at the 3 rd pin of the first three-terminal regulated integrated chip U1 stable, and the first filter capacitor C1 is used to filter high-frequency interference in the input voltage V0.
An output terminal Vout of the first three-terminal voltage regulation integrated chip U1, that is, a voltage output by the 2 nd pin of the first three-terminal voltage regulation integrated chip U1 is a converted first voltage V1, the 2 nd pin of the first three-terminal voltage regulation integrated chip U1 is connected to one end of the second energy storage capacitor EC2 and one end of the second capacitor C2, respectively, functions of the second energy storage capacitor EC2 and the second capacitor C2 are similar to those of the first energy storage capacitor EC1 and the first filter capacitor C1, and therefore, details thereof are not repeated within a scope easily understood by those skilled in the art. The ground terminal GND of the three-terminal regulator integrated chip U1 is grounded.
Therefore, the circuit structure shown in fig. 3 can convert the input voltage V0 into the first voltage V1, for example, assuming that the input voltage V0 is 12V and the first voltage V1 is 5V, a three-terminal regulated integrated chip with a model LM7805 can be used as the first three-terminal regulated integrated chip U1, and the LM7805 is a commonly used linear three-terminal regulated integrated chip, and the external package includes a plurality of types but the output voltage is 5V, when the input voltage V0 is connected to the LM7805, the output voltage of the 2 nd pin of the LM7805, that is, the first voltage V1 is 5V. Therefore, the first voltage regulating circuit converts the 12V input power supply into the 5V direct current power supply and inputs the 5V direct current power supply into the power supply control loop 12.
The power supply control loop 12 can control the power-on or power-off of the control unit 20 according to the first voltage. The power supply control loop 12 monitors whether the first voltage V1 has an abnormal condition in real time, and can take corresponding measures to process the abnormal condition when the first voltage V1 has the abnormal condition.
Fig. 4 is a schematic diagram of a possible circuit configuration of the power supply control loop 12, as shown in fig. 4. The power supply control circuit 12 includes a first signal generating circuit 121 and a first switching circuit 122, an input end of the first signal generating circuit 121 is connected to an output end of the first voltage regulating circuit, that is, a first voltage V1 is input to the first signal generating circuit 121, an output end of the first signal generating circuit 121 is connected to an input end of the first switching circuit 122, and an output end of the first switching circuit 122 is connected to the second voltage regulating circuit.
The first signal generating circuit 121 can output a switching signal for controlling the switching state of the first switching circuit 122 according to the variation of the received first voltage V1.
Optionally, the first signal generating circuit 121 includes a first comparator U3A and a first zener diode ZD1, wherein a non-inverting input terminal of the first comparator U3A (i.e., the 3 rd pin of the first comparator U3A) is connected to the cathode of the first zener diode ZD1 and the voltage source, respectively, an inverting input terminal of the first comparator U3A (i.e., the 2 nd pin of the first comparator U3A) is connected to the output terminal of the first voltage regulating circuit 11, an output terminal of the first comparator U3A (i.e., the 1 st pin of the first comparator U3A) is connected to the input terminal of the first switching circuit 122, and the anode of the first zener diode ZD1 is grounded.
Optionally, the first signal generating circuit 121 further includes a first resistor R1, a second resistor R2, a third resistor R3, and a third filter capacitor C3, wherein, namely, the 3 rd pin of the first comparator U3A is connected to the cathode of the first zener diode ZD1, the 3 rd pin of the first comparator U3A is further connected to the voltage source through the second resistor R2, and is grounded through the third resistor R3. The first resistor R1 and the second resistor R2 connected in series are used for dividing the input voltage V0 to provide an input voltage of the 3 rd pin of the first comparator U3A, which serves as the first reference voltage VFA of the first comparator U3A, and meanwhile, the first zener diode ZD1 can clamp the first reference voltage VFA to prevent the first reference voltage VFA from being too large to damage the first comparator U3A when the input voltage V0 fluctuates too much momentarily; the third resistor R3 plays a role of current limiting, and also prevents the first voltage V1 from being too large to cause the first comparator U3A to be damaged.
By setting the resistance values of the first resistor R1 and the second resistor R2 and selecting the appropriate first zener diode ZD1, the first reference voltage VFA can be set to be less than the first voltage V1, and when the abnormal power down condition does not occur, the first reference voltage VFA is set to be less than the first voltage V1, and at this time, the 1 st pin of the first comparator U3A outputs a low-level signal; when an abnormal power down condition occurs, the first voltage V1 decreases and is less than the first reference voltage VFA, and at this time, the 1 st pin of the first comparator U3A outputs a high level signal.
It should be understood that the first reference voltage VFA may be obtained from a voltage source as shown in fig. 4, or in another embodiment, a separate voltage source may be added as the first reference voltage VFA.
Optionally, the first switch circuit 121 includes a first switch Q1, a second switch Q2 and a third switch Q3, the control terminal of the first switch Q1, that is, the 1 st pin of the first switch Q1 is connected to the 1 st pin of the first comparator U3A, the first terminal of the first switch Q1, the 2 nd pin of the first switch Q1 is grounded, the second terminal of the first switch Q1, the 3 rd pin of the first switch Q1 is connected to the control terminal of the second switch Q2 (the 1 st pin of the second switch Q2); a first end (pin 2 of the second switching tube Q2) of the second switching tube Q2 is grounded, and a second end (pin 3 of the second switching tube Q2) of the second switching tube Q2 is connected with a control end (pin 1 of the third switching tube Q3) of the third switching tube Q3; a first terminal of the third switching tube Q3 (pin 2 of the third switching tube Q3) is connected to the input terminal of the second voltage regulator circuit 13, and a second terminal of the third switching tube Q3 (pin 3 of the third switching tube Q3) is connected to the output terminal of the first voltage regulator circuit 11. The switching states of the first switching circuit 122 refer to the on and off states of the three switching tubes, i.e., the first switching tube Q1, the second switching tube Q2 and the third switching tube Q3.
Optionally, the first switch circuit 121 further includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9, and the specific connection manner of each element is as shown in fig. 4, which is not described herein again.
In practical applications, the first switch transistor Q1 and the second switch transistor Q2 are transistors, and the third switch transistor Q3 is a P-channel MOS. At the moment, the base electrode of the triode is the 1 st pin of the switching tube, the emitter electrode of the triode is the 2 nd pin of the switching tube, and the collector electrode of the triode is the 3 rd pin of the switching tube; the grid electrode of the MOS tube is the 1 st pin of the switch tube, the source electrode of the MOS tube is the 2 nd pin of the switch tube, and the drain electrode of the MOS tube is the 3 rd pin of the switch tube.
When the abnormal power failure condition does not occur, the 1 st pin of the first comparator U3A outputs a low level signal, at the moment, the 1 st pin and the 2 nd pin of the first switch tube Q1 are both low level signals, and the first switch tube Q1 is turned off; a 1 st pin of the second switching tube Q2 is connected to the output end of the first voltage regulating circuit 11 through a seventh resistor R7, a voltage at the 1 st pin of the second switching tube Q2 is a first voltage V1, the 1 st pin of the second switching tube Q2 is grounded, a voltage difference exists between the 1 st pin and the 2 nd pin of the second switching tube Q2, and the second switching tube Q2 is turned on; the 1 st pin of the third transistor Q3 is connected to the ground AGND of the power supply through the ninth resistor R9, the 3 rd pin of the second transistor Q2, and the 2 nd pin, and the 1 st pin of the third transistor Q3 is at a low level, so that the third transistor Q3 is turned on. Therefore, the output terminal of the first voltage regulating circuit 11 is connected to the output terminal of the second voltage regulating circuit 13 through the 3 rd pin and the 2 nd pin of the third switching tube Q3, and then the second voltage regulating circuit 13 has the input voltage V1 (i.e., V11), the second voltage regulating circuit 13 can also output the supply voltage for providing the operation of the control unit 20, and the control unit 20 is in the normal operation state.
When abnormal power failure occurs, the 1 st pin of the first comparator U3A outputs a high level signal, at this time, the 1 st pin of the first switch tube Q1 is at a high level, the 2 nd pin of the first switch tube Q1 is grounded, and is also at a low level, so that the first switch tube Q1 is turned on; the 1 st pin of the second switching tube Q2 is connected to the ground AGND of the power supply through the 3 rd pin and the 2 nd pin of the first switching tube Q1, the 1 st pin of the second switching tube Q2 is at a low level, the 2 nd pin of the second switching tube Q2 is also grounded, and the second switching tube Q2 is turned off; the voltage at the connection point between the seventh resistor R7 and the eighth resistor R8 is the voltage at the 1 st pin of the third switching tube Q3, while the voltage at the connection point between the seventh resistor R7 and the eighth resistor R8 is the divided voltage of the first voltage V1, and the third switching tube Q3 is turned off. Thereby, the connection between the first voltage regulating circuit 11 and the second voltage regulating circuit 12 is disconnected, the second voltage regulating circuit 12 loses the input power, that is, the control unit 20 also loses the supply voltage, the control unit 20 stops operating, and the supply loop of the control unit 20 is completely cut off.
Further, the first switch circuit 121 further includes a first capacitor EC3, two ends of the first capacitor EC3 are respectively connected to the 1 st pin and the 2 nd pin of the first switch tube Q1, and the first capacitor is used for controlling the on-time of the first switch tube Q1.
When the 1 st pin of the first switch Q1 changes from low level to high level, the first capacitor EC3 is charged, the first switch Q1 is in a conducting state, then the first capacitor EC3 discharges through the sixth resistor R6, and when the voltage discharged to the 1 st pin of the first switch Q1 is not enough to make the first switch Q1 conduct, the first switch Q1 is turned off. Therefore, the on-time of the first switch Q1 is related to how fast the first capacitor EC3 discharges, and how fast the first capacitor EC3 discharges is related to the capacitance of the first capacitor EC3, i.e. the on-time of the first switch Q1 is determined by the capacitance of the first capacitor EC3, and the on-time of the first switch Q1 can be adjusted by selecting the first capacitor EC3 with different capacitances. Therefore, the power down duration of the control unit 20 may be set by setting the capacitance value of the first capacitor EC3 to be fully reset to power down.
The second voltage regulating circuit 13 is configured to convert the first voltage, so that the output terminal of the second voltage regulating circuit 13 outputs a second voltage, and the second voltage is used to provide a supply voltage for the control unit 20.
Likewise, the second voltage regulating circuit 13 can implement the voltage conversion process with a similar circuit configuration as the first voltage regulating circuit 11.
As shown in fig. 5, the second voltage regulating circuit 13 includes a second three-terminal regulator ic U2, when no abnormal power failure occurs, the input voltage of the second three-terminal regulator ic U2 of the second voltage regulating circuit 13 is a voltage V11, i.e., a first voltage V1, the second three-terminal regulator ic U2 converts the first voltage V1 into a second voltage V2, and the second voltage V2 can be directly used as a supply voltage of the control unit 20. The type of the second three-terminal regulator ic U2 actually used needs to be determined according to the input voltage required by the control unit 20, for example, the control unit 20 requires 3.3V power, and assuming that the first voltage regulating circuit 11 has converted the 12V input voltage into 5V, the second three-terminal regulator ic U2 needs to be able to convert 5V into 3.3V, such as the AMS1117 chip, which is able to convert the input 5V into a stable 3.3V output.
The reset control circuit 14 is configured to output a reset control signal to the control unit 20 according to the second voltage, and the reset control circuit 14 can output the reset signal to the control unit 20 in time when a power failure abnormality occurs, so that the control unit 20 can perform a reset forcibly, and the control unit 20 is prevented from entering a sleep or crash state for protection.
As shown in fig. 6, in one embodiment, the reset control circuit 14 includes a second switch circuit 141 and a second signal generating circuit 142, an input terminal of the second switch circuit 141 is connected to an output terminal of the second voltage regulating circuit 13, an output terminal of the second switch circuit 141 is connected to an input terminal of the second signal generating circuit 142, and an output terminal of the second signal generating circuit 142 is connected to a reset signal input terminal of the control unit 20. The second switch circuit 141 is configured to switch a switching state according to the second voltage, so that the second signal generating circuit 142 outputs a reset signal to the control unit 20.
Optionally, the second switching circuit 141 includes a fourth switching tube Q4, the control terminal of the fourth switching tube Q4 (i.e., pin 1 of the fourth switching tube Q4) is connected to the output terminal of the second voltage regulating circuit 13, the first terminal of the fourth switching tube Q4 (i.e., pin 2 of the fourth switching tube Q4) is grounded, and the second terminal of the fourth switching tube Q4 (i.e., pin 3 of the fourth switching tube Q4) is connected to the voltage source.
Optionally, the second signal generating circuit 142 includes a second comparator U3B, a non-inverting input terminal of the second comparator U3B (i.e., the 5 th pin of the second comparator U3B) is connected to the output terminal of the second regulated voltage 13, an inverting input terminal of the second comparator U3B (i.e., the 6 th pin of the second comparator U3B) is connected to the 3 rd pin of the fourth switch Q4, and an output terminal of the second comparator U3B (i.e., the 7 th pin of the second comparator U3B) is connected to the reset signal input terminal of the control unit 20.
Optionally, the second switch circuit 141 further includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a first diode D1, and the specific connection relationship can be obtained from the circuit structure shown in fig. 6, which is not described herein again.
In practical applications, a triode is taken as an example for the fourth switching tube Q4, and the corresponding relationship of the specific pins is the same as that of the other switching tubes in this embodiment.
When no abnormal power-down condition occurs, the second voltage V2 is divided by the ninth resistor R9 and the tenth resistor R10 and then is used as the voltage on the 1 st pin of the fourth switching tube Q4, the 2 nd pin of the fourth switching tube Q4 is grounded, and a voltage difference exists between the 1 st pin and the 2 nd pin of the fourth switching tube Q4, so that the fourth switching tube Q4 is turned on; the pin 6 of the second comparator U3B is connected to the ground AGND of the power supply through the twelfth resistor R12, the pin 3 and the pin 2 of the fourth switch Q4, the voltage input to the pin 5 of the second comparator U3B is the voltage VFB, the voltage VFB is the voltage of the second voltage V2 after current limiting through the fourteenth resistor R14, the voltage at the non-inverting input terminal of the second comparator U3B is greater than the voltage at the inverting input terminal, the pin 7 of the second comparator U3B outputs a high level, that is, the signal output from the connection REST _ MCU is a high level signal, and the control unit 20 does not perform the reset process and is in the normal operating state.
When an abnormal power-down condition occurs, the second voltage V2 is reduced, and the fourth switching tube Q4 can be disconnected by arranging a ninth resistor R9 and a tenth resistor R10; the 6 th pin of the second comparator U3B is connected to the voltage source through the twelfth resistor R12 and the eleventh resistor R11, the voltage at the 6 th pin of the second comparator U3B is pulled high and is higher than the voltage at the 5 th pin of the second comparator U3B, at this time, the voltage at the non-inverting input terminal of the second comparator U3B is lower than the voltage at the inverting input terminal, the 7 th pin of the second comparator U3B outputs a low level, that is, the signal output from the connection REST _ MCU is a low level signal, and the control unit 20 forcibly performs the reset process.
Likewise, the voltage VFB may be derived from the second voltage as shown in fig. 6, or in another embodiment, a separate voltage source may be added as the voltage VFB.
In an embodiment, the second signal generating circuit 142 further includes a second capacitor EC6, a first end of the second capacitor EC6 is connected to the 7 th pin of the second comparator U3B, and the other end of the second capacitor EC6 is connected to ground, wherein the second capacitor EC6 is configured to control a duration of the 7 th pin of the second comparator U3B outputting the reset signal (i.e., a low-level signal).
When the 7 th pin of the second comparator U3B outputs a low level, the second capacitor EC6 starts to be charged, during the charging process, the reset signal is gradually increased by the low level signal, when the charging is performed until the reset signal cannot meet the requirement of the control unit 20 for resetting, the resetting of the control unit 20 is completed, that is, the time for resetting the control unit 20 is determined by the charging time of the second capacitor EC6, the charging time of the second capacitor EC6 is determined by the capacitance value of the second capacitor EC6, when the capacitance of the second capacitor EC6 is increased, the charging time is increased, the resetting time is correspondingly increased, and otherwise, the resetting time is shortened. Therefore, by setting the capacitance value of the second capacitor EC6, the forced reset time of the control unit 20 can be adjusted, ensuring that the control unit 20 completes the reset.
It should be noted that in this embodiment, each switching tube may be a transistor, a MOS tube, or an IGBT switching tube, and the first switching tube Q1, the second switching tube Q2, the third switching tube Q3, and the fourth switching tube Q4 may be the same or different, for example, the first switching tube Q1, the second switching tube Q2, the third switching tube Q3, and the fourth switching tube Q4 are MOS tubes at the same time.
The utility model provides a power down protection circuit 10 and integrated chip 100, power down protection circuit 10 is used for being connected with reset signal input end and power end of control unit 20, power down protection circuit 10 includes first regulator circuit 11, power supply control circuit 12, second regulator circuit 13 and reset control circuit 14, wherein, first regulator circuit 11 is connected with voltage source 200, first regulator circuit 11 is used for converting the input voltage of voltage source 200, so that the output of first regulator circuit 11 outputs the first voltage, power supply control circuit 12 is connected with first regulator circuit 11, power supply control circuit 12 is used for controlling power on or power off of control unit 20 according to the first voltage, second regulator circuit 13 is connected with power end of power supply control circuit 12 and control unit 20 respectively, second regulator circuit 13 is used for converting the first voltage, so that the output of second regulator circuit 13 outputs the second voltage, the second voltage is used for providing a supply voltage for the control unit 20, the reset control circuit 14 is respectively connected with the second voltage regulating circuit 13 and a reset signal input terminal of the control unit 20, the reset control circuit 14 is used for outputting a reset control signal to the control unit 20 according to the second voltage, i.e., when the electronic device provided with the power down protection circuit 10 is powered down, the power supply control circuit 12 can control the control unit 20 to be powered down, at the same time, the reset control circuit 14 can output a reset control signal to the control unit 20, to control the control unit 20 to reset, thereby realizing not only the power loss of the control unit 20, but also the forced reset of the control unit 20, therefore, when the electronic product is powered off, the control unit 20 can be prevented from entering the sleep or dead halt state protection, the power failure protection of the electronic product is realized, and a pure hardware circuit is adopted, so that the cost is low, and the volume is small.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments can be combined, steps can be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022655417.5U CN214069562U (en) | 2020-11-16 | 2020-11-16 | A power failure protection circuit and integrated chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022655417.5U CN214069562U (en) | 2020-11-16 | 2020-11-16 | A power failure protection circuit and integrated chip |
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| CN214069562U true CN214069562U (en) | 2021-08-27 |
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| CN202022655417.5U Withdrawn - After Issue CN214069562U (en) | 2020-11-16 | 2020-11-16 | A power failure protection circuit and integrated chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112271704A (en) * | 2020-11-16 | 2021-01-26 | 深圳市德兰明海科技有限公司 | A power failure protection circuit and integrated chip |
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2020
- 2020-11-16 CN CN202022655417.5U patent/CN214069562U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112271704A (en) * | 2020-11-16 | 2021-01-26 | 深圳市德兰明海科技有限公司 | A power failure protection circuit and integrated chip |
| CN112271704B (en) * | 2020-11-16 | 2024-11-26 | 深圳市德兰明海新能源股份有限公司 | A power-off protection circuit and integrated chip |
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Address after: 518000 19th floor, building 1, kaidar group center building, No. 168, Tongsha Road, Xinwei community, Xili street, Nanshan District, Shenzhen, Guangdong Patentee after: Shenzhen Delian Minghai New Energy Co.,Ltd. Address before: 701-3, building 2, kaidar group center building, 168 Tongsha Road, Xili street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Poweroak Newener Co.,Ltd. |
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