CN213754540U - Single-bus communication circuit - Google Patents
Single-bus communication circuit Download PDFInfo
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- CN213754540U CN213754540U CN202023095706.0U CN202023095706U CN213754540U CN 213754540 U CN213754540 U CN 213754540U CN 202023095706 U CN202023095706 U CN 202023095706U CN 213754540 U CN213754540 U CN 213754540U
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Abstract
The utility model discloses a single bus communication circuit, triode Q1 collecting electrode is connected to first data receiving terminal, first mains voltage end is connected to triode Q1 base, triode Q3 collecting electrode is connected to triode Q1 projecting electrode, triode Q3 projecting electrode is connected to first data sending terminal, first mains voltage end is connected to triode Q3 base, triode Q2 collecting electrode is connected to the second data receiving terminal, second mains voltage end is connected to triode Q2 base, triode Q2 base is connected triode Q4's base, triode Q4 collecting electrode is connected to triode Q2 projecting electrode, second circuit voltage end is connected to triode Q2 projecting electrode, triode Q4 projecting electrode is connected to the second data sending terminal; the emitting electrode of the triode Q1 is connected with the emitting electrode of the triode Q2, and the collecting electrode of the triode Q3 is connected with the collecting electrode of the triode Q4, so that the communication circuit can be compatible with different communication level voltages and has better anti-noise and interference performance.
Description
Technical Field
The utility model relates to a communication circuit technical field especially relates to a can realize single bus communication circuit of full duplex communication.
Background
A Universal Asynchronous Receiver/Transmitter (UART) is a serial Asynchronous Receiver/Transmitter protocol, and is widely used. The UART operating principle is to transmit the binary bit of data one bit by one bit, the high level of the status bit on the signal line represents '1' and the low level represents '0' in the UART communication protocol, certainly, when two devices use the UART serial port for communication, the transmission rate and some data bits must be specified first, when the UART is used for communication, the hardware connection is simple, 3 communication connection lines are needed, the connection mode of the traditional communication circuit is shown in fig. 1, the data transmitting terminal TX of the first MCU is connected to the data receiving terminal RX of the second MCU, the data receiving terminal RX of the first MCU is connected to the data transmitting terminal TX of the second MCU, the GND terminal of the first MCU and the GND terminal of the second MCU are grounded simultaneously, if the levels of the two devices are not consistent during connection, the two devices need to be connected after level conversion, which results in a complex circuit structure and increases the production cost.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a single bus communication circuit, if need the problem that the circuit structure is complicated, manufacturing cost increases that reconnection leads to after the level transition when two equipment UART level scope are inconsistent when having solved traditional communication circuit and connecting for communication circuit can compatible different communication level voltage, and has better antinoise and interference performance.
In order to achieve the above object, the technical solution of the present invention is specifically realized as follows:
the utility model discloses a single bus communication circuit, include: the device comprises a triode Q1, a triode Q2, a triode Q3 and a triode Q4, wherein a first data receiving end RX is connected with a collector of the triode Q1, a base of the triode Q1 is connected with a first power supply voltage VDD end, an emitter of the triode Q1 is connected with the collector of the triode Q3, meanwhile, an emitter of the triode Q1 is connected with a first circuit voltage VCC end, a first data transmitting end TX is connected with an emitter of the triode Q3, a base of the triode Q3 is connected with the first power supply voltage VDD end, and a collector of the triode Q3 is grounded; the second data receiving terminal RX1 is connected to a collector of the transistor Q2, a base of the transistor Q2 is connected to a second power voltage VDD1 terminal, a base of the transistor Q2 is connected to a base of the transistor Q4, an emitter of the transistor Q2 is connected to a collector of the transistor Q4, an emitter of the transistor Q2 is connected to a second circuit voltage VCC1 terminal, a second data transmitting terminal TX1 is connected to an emitter of the transistor Q4, and a collector of the transistor Q4 is grounded; the emitter of the transistor Q1 is connected with the emitter of the transistor Q2, and the collector of the transistor Q3 is connected with the collector of the transistor Q4.
Further, the transistor Q1, the transistor Q2, the transistor Q3, and the transistor Q4 are all NPN-type triacs.
Furthermore, the emitter of the triode Q1 is sequentially connected with the emitter of the triode Q2 through a resistor R4 and a resistor R6, and the collector of the triode Q3 is sequentially connected with the collector of the triode Q4 through a resistor R4 and a resistor R6.
Furthermore, the base electrode of the triode Q1 is connected with a first power voltage VDD end through a resistor R1, the emitter electrode of the triode Q1 is sequentially connected with a first circuit voltage VCC end through a resistor R2 and a diode D1, the base electrode of the triode Q3 is connected with the first power voltage VDD end through a resistor R7, the collector electrode of the triode Q3 is grounded through an anti-static protection tube ZD1,
furthermore, the triode Q2 is connected to the second power voltage VDD1 end through a resistor R5, the emitter of the triode Q2 is connected to the second circuit voltage VCC end through a resistor R3 and a diode D2 in sequence, and the collector of the triode Q4 is grounded through an anti-static protection tube ZD 2.
Further, the transistor Q1 and the transistor Q2 may be replaced with a diode D3 and a diode D4.
The beneficial technical effects are as follows:
the utility model discloses a single bus communication circuit, including triode Q1, triode Q2, triode Q3 and triode Q4, first data receiving terminal RX is connected triode Q1's collecting electrode, first mains voltage VDD end is connected to triode Q1's base, triode Q1's projecting pole is connected triode Q3's collecting electrode, and simultaneously, triode Q1's projecting pole is connected first circuit voltage VCC end, and first data sending terminal TX is connected triode Q3's projecting pole, first mains voltage VDD end is connected to triode Q3's base, triode Q3's collecting electrode ground connection; the second data receiving terminal RX1 is connected to a collector of the transistor Q2, a base of the transistor Q2 is connected to a second power voltage VDD1 terminal, a base of the transistor Q2 is connected to a base of the transistor Q4, an emitter of the transistor Q2 is connected to a collector of the transistor Q4, an emitter of the transistor Q2 is connected to a second circuit voltage VCC1 terminal, a second data transmitting terminal TX1 is connected to an emitter of the transistor Q4, and a collector of the transistor Q4 is grounded; the emitting electrode of the triode Q1 is connected with the emitting electrode of the triode Q2, and the collecting electrode of the triode Q3 is connected with the collecting electrode of the triode Q4, so that the problems that when a traditional communication circuit is connected, if the level ranges of two devices are inconsistent, the two devices need level conversion and then are connected, the circuit structure is complex, and the production cost is increased are solved, the communication circuit can be compatible with different communication level voltages, and the noise resistance and the interference resistance are good.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiments will be briefly described below.
Fig. 1 shows a conventional communication circuit connection method.
Fig. 2 is a structural diagram of a single bus communication circuit according to a first embodiment of the present invention;
fig. 3 is a structural diagram of a single bus communication circuit according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram of an example transmission of ASCII "W".
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of the present invention should not be construed as being limited.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The first embodiment is as follows:
the utility model discloses a single bus communication circuit, see fig. 1, single bus communication circuit includes triode Q1, triode Q2, triode Q3 and triode Q4, concretely, triode Q1's collecting electrode is connected to first data receiving terminal RX, triode Q1's base passes through resistance R1 and connects first mains voltage VDD end, triode Q1's projecting pole connects triode Q3's collecting electrode, and simultaneously, triode Q1's projecting pole is in proper order through resistance R2 and diode D1 connect first circuit voltage VCC end, triode Q3's base passes through resistance R7 and connects first mains voltage VDD end, triode Q3's projecting pole connects first data sending terminal TX, triode Q3's collecting electrode passes through TVS anti-static electricity protection tube ZD1 ground connection, and simultaneously, triode Q3's collecting electrode passes through resistance R4 and resistance R6 in proper order and connects triode Q2's projecting pole, triode Q2's collecting electrode connects second data RX1, the base electrode of the triode Q2 is connected with the second power voltage VDD1 end through the resistor R5, meanwhile, the base electrode of the triode Q2 is connected with the base electrode of the triode Q4, the emitter electrode of the triode Q2 can be sequentially connected with the second circuit voltage VCC1 end through the resistor R3 and the diode D2, meanwhile, the emitter of the triode Q2 is connected with the collector electrode of the triode Q4, the base electrode of the triode Q4 is connected with the second power voltage VDD1 end through the resistor R5, the collector electrode of the triode Q4 is grounded through the TVS anti-static protection tube ZD2, the emitter electrode of the triode Q4 is connected with the second data transmitting end TX1, the emitter electrode of the triode Q1 and the collector electrode of the triode Q3 are sequentially connected with the emitter electrode of the triode Q2 and the collector electrode of the triode Q4 through the resistor R4 and the resistor R6.
As an embodiment of the present invention, triode Q1, triode Q2, triode Q3 and triode Q4 are NPN transistors, and triode Q1, triode Q2, triode Q3 and triode Q4 function as switches.
The utility model discloses an among the single bus communication circuit, resistance R2 and resistance R4 are current-limiting resistor, diode D1 and diode D2 are reverse clamp protection diode, ZD1 and ZD2 are TVS anti-static protection tube, resistance R1, resistance R5 and resistance R7 are base resistance, first data sending end TX and the highest level of first data receiving end RX are first supply voltage VDD, second data sending end TX1 and the highest level of second data receiving end RX1 are second supply voltage VDD1, when first circuit voltage VCC is different with second circuit voltage VCC1 level, resistance R2, resistance R4, resistance R6 and resistance R3 carry out the current-limiting partial pressure, make first circuit voltage VCC and second circuit voltage VCC1 level equal.
The utility model discloses a monobus communication circuit's concrete theory of operation does:
generally speaking, when no data is transmitted by a conventional serial port, a serial bus is in a high level state, when data is transmitted, a clock cycle is pulled down firstly to serve as a Start Bit, data to be transmitted is followed, the data length is agreed by both sides, finally a check Bit can be followed, the completion of data transmission is represented by a pulled-up clock cycle to serve as a Stop Bit, and then the bus is in a high level state continuously.
Taking ASCII "W" (1010111) transmission as an example, referring to fig. 4, the working process of the single-bus communication circuit disclosed by the present invention is described in detail, wherein the first data receiving terminal RX, the second data receiving terminal RX1, the first data transmitting terminal TX and the second data transmitting terminal TX1 are in a high level state in an idle state; when the first data transmitting terminal TX is at a low level, the triode Q1, the triode Q2 and the triode Q3 work in an amplifying area, the triode Q4 works in a cut-off area, the level of an ONE LINE BUS is reduced by the triode Q3, and the level of a second data receiving terminal RX1 is consistent with the level of a BUS; when the first data transmitting terminal TX is at a high level, the transistor Q1, the transistor Q2, the transistor Q3 and the transistor Q4 all operate in a cut-off region, the ONE LINE BUS is at a high level, and the level of the second data receiving terminal RX1 is consistent with the level of the BUS.
Example two:
in an embodiment, the transistor Q1 and the transistor Q2 may be replaced by a diode D3 and a diode D4, and specifically, referring to fig. 3, the first data receiving terminal RX is connected to the collector of the transistor Q3 through a diode D3, the first data receiving terminal RX is connected to the first circuit voltage VCC terminal through a diode D3, a resistor R2 and a diode D1 in turn, the base of the transistor Q7 is connected to the first power voltage VDD terminal, the emitter of the transistor Q3 is connected to the first data transmitting terminal, the collector of the transistor Q3 is connected to the ground through a TVS esd protection tube ZD1, the collector of the transistor Q3 is connected to the cathode of the diode D4 and the collector of the transistor Q4 through a resistor R4 and a resistor R6 in turn, the second data receiving terminal is connected to the anode of the diode D4, the cathode of the diode D4 is connected to the second circuit voltage terminal 4 through a resistor R4 and the base of the transistor Q4 is connected to the second circuit voltage VDD terminal 4, an emitter of the triode Q4 is connected with a second data transmitting terminal TX1, a collector of the triode Q4 is grounded through a TVS anti-static protection tube ZD2, and meanwhile, a collector of the triode Q4 is sequentially connected with a cathode of a diode D3 and a collector of the triode Q3 through a resistor R6 and a resistor R4.
The working principle of this embodiment is the same as that of the first embodiment, and is not described herein again.
The utility model discloses a single bus communication circuit can compatible different communication level voltage to reduce a communication line, and have good noise interference immunity of resisting, long distance transmission ability and multiple spot transmission ability.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above embodiments are only intended to describe the preferred embodiments of the present invention, but not to limit the scope of the present invention, and various modifications and improvements made by the technical solutions of the present invention by those skilled in the art should fall within the protection scope defined by the claims of the present invention without departing from the design spirit of the present invention.
Claims (6)
1. A single bus communication circuit, comprising: the device comprises a triode Q1, a triode Q2, a triode Q3 and a triode Q4, wherein a first data receiving end RX is connected with a collector of the triode Q1, a base of the triode Q1 is connected with a first power supply voltage VDD end, an emitter of the triode Q1 is connected with the collector of the triode Q3, meanwhile, an emitter of the triode Q1 is connected with a first circuit voltage VCC end, a first data transmitting end TX is connected with an emitter of the triode Q3, a base of the triode Q3 is connected with the first power supply voltage VDD end, and a collector of the triode Q3 is grounded; the second data receiving terminal RX1 is connected to the collector of the transistor Q2, the base of the transistor Q2 is connected to the second power voltage VDD1, the base of the transistor Q2 is connected to the base of the transistor Q4, the emitter of the transistor Q2 is connected to the collector of the transistor Q4, the emitter of the transistor Q2 is connected to the second circuit voltage VCC1, the second data transmitting terminal TX1 is connected to the emitter of the transistor Q4, and the collector of the transistor Q4 is grounded; the emitter of the transistor Q1 is connected with the emitter of the transistor Q2, and the collector of the transistor Q3 is connected with the collector of the transistor Q4.
2. The single bus communication circuit as claimed in claim 1, wherein the transistor Q1, the transistor Q2, the transistor Q3 and the transistor Q4 are NPN transistors.
3. The unibus communication circuit as claimed in claim 2, wherein the emitter of said transistor Q1 is connected to the emitter of said transistor Q2 through a resistor R4 and a resistor R6, and the collector of said transistor Q3 is connected to the collector of said transistor Q4 through a resistor R4 and a resistor R6.
4. The single-bus communication circuit as claimed in claim 3, wherein the base of the transistor Q1 is connected to the first power voltage VDD via a resistor R1, the emitter of the transistor Q1 is connected to the first circuit voltage VCC via a resistor R2 and a diode D1 in turn, the base of the transistor Q3 is connected to the first power voltage VDD via a resistor R7, and the collector of the transistor Q3 is grounded via an anti-static protection tube ZD 1.
5. The unibus communication circuit as claimed in claim 4, wherein said transistor Q2 is connected to the second power voltage VDD1 via a resistor R5, the emitter of said transistor Q2 is connected to the second circuit voltage VCC via a resistor R3 and a diode D2, and the collector of said transistor Q4 is grounded via an anti-electrostatic protection tube ZD 2.
6. The single bus communication circuit as claimed in claim 1, wherein said transistor Q1 and said transistor Q2 are replaced by a diode D3 and a diode D4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023095706.0U CN213754540U (en) | 2020-12-21 | 2020-12-21 | Single-bus communication circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023095706.0U CN213754540U (en) | 2020-12-21 | 2020-12-21 | Single-bus communication circuit |
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| Publication Number | Publication Date |
|---|---|
| CN213754540U true CN213754540U (en) | 2021-07-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202023095706.0U Active CN213754540U (en) | 2020-12-21 | 2020-12-21 | Single-bus communication circuit |
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| CN (1) | CN213754540U (en) |
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