CN216817396U

CN216817396U - Conversion circuit for converting four-wire system TTL interface into two-wire system bus interface

Info

Publication number: CN216817396U
Application number: CN202123098905.1U
Authority: CN
Inventors: 吴帅; 柴学勇; 孙健
Original assignee: Jiangsu Binchen Electronics Co ltd
Current assignee: Jiangsu Binchen Electronics Co ltd
Priority date: 2021-12-10
Filing date: 2021-12-10
Publication date: 2022-06-24
Anticipated expiration: 2031-12-10

Abstract

The utility model discloses a conversion circuit for converting a four-wire system TTL interface into a two-wire system bus interface, which is characterized in that the interface conversion circuit consists of a connecting terminal CON4 connected with the four-wire system TTL interface, a connecting terminal CON2 connected with the two-wire system bus and discrete active and passive components, and the interface conversion circuit can enable instrument equipment connected to the TTL interface and instrument equipment connected to the two-wire system bus to realize half-duplex serial communication. The utility model solves the problem that two instruments can carry out serial half-duplex communication through a two-wire system bus. By adopting a two-wire system, communication wires can be saved, construction is convenient, and the misoperation rate of workers is reduced.

Description

Conversion circuit for converting four-wire system TTL interface into two-wire system bus interface

Technical Field

The utility model relates to the field of communication, in particular to a four-wire system TTL interface to two-wire system bus circuit.

Background

The traditional TTL interface communication mostly adopts four-wire system or three-wire system lines, the construction is complex, and the misoperation rate of workers is high.

SUMMERY OF THE UTILITY MODEL

The utility model provides a four-wire system TTL interface to two-wire system bus circuit aiming at the problems in the background art.

The technical scheme is as follows:

a conversion circuit for converting a four-wire system TTL interface into a two-wire system bus interface is composed of a wiring terminal CON4 connected with the four-wire system TTL interface, a wiring terminal CON2 connected with the two-wire system bus and discrete active and passive components, and can enable instrument equipment connected to the TTL interface and instrument equipment connected to the two-wire system bus to realize half-duplex serial port communication.

Preferably, the connection terminal CON4 has four pins, which are respectively a 1-pin power supply VCC, a 2-pin transmitting pin TXD, a 3-pin receiving pin RXD, and a 4-pin ground; the connecting terminal CON2 is provided with two pins which are respectively 1 pin BUS and 2 pin BUS +; when the four-wire system TTL interface sends signals, a sending pin TXD is at a low level, a receiving pin RXD is at a high level, and a BUS + pin is at a high level; when the two-wire BUS BUS sends signals, the BUS + pin is at a high level, the receiving pin RXD is at a low level, and the sending pin TXD is at a high level.

Preferably, the discrete active and passive components, the connection terminal CON4, and the connection terminal CON2 are connected as follows:

on one hand, a terminal 2 pin BUS + of the CON2 is connected with a cathode of the diode D1, two ends of the diode D1 are connected with the resistor R1 in parallel, and an anode of the diode D1 is grounded;

the CON2 terminal 2 pin BUS + is connected with one end of a resistor R2, the other end of the resistor R2 is connected with a base electrode of a triode NPN1 through a resistor R3, and the other end of the resistor R2 is also connected with a collector electrode of the triode NPN 2; an emitter of the triode NPN1 is grounded, a resistor R4 is connected between a base and the emitter of the triode NPN1, and a collector of the triode NPN1 is connected with a voltage VCC through a resistor R5; the emitter of the triode NPN2 is grounded, a resistor R8 is connected between the base and the emitter of the triode NPN2, and the base of the triode NPN2 is also connected with the collector of the triode PNP1 through a resistor R7;

on the other hand, a terminal 2 pin BUS + of the CON2 is also connected with one end of a resistor R6, the other end of the resistor R6 is connected with a cathode of a diode D2, an anode of a diode D2 is connected with a collector of a triode PNP1, and the collector of the triode PNP1 is also connected with a capacitor C1 in series through a resistor R9 and grounded;

CON2 terminal 1 pin BUS-ground;

the CON4 terminal 1 pin is connected with a voltage VCC;

a pin 2 sending pin TXD of a CON4 is connected with a base electrode of a triode PNP1 through a resistor R10, and an emitting electrode of the triode PNP1 is connected with a voltage VCC;

a pin 3 receiving pin RXD of a CON4 terminal is connected with a collector of a triode NPN 1;

CON4 is pin 4 grounded.

Specifically, the type of the diode D1 is: SMBJ12A, diode D2 model: 4148.

specifically, the capacitance and the withstand voltage of the capacitor C1 are as follows: 10 nF/50V.

Specifically, the resistance value of the resistor R1 is: 2K Ω, the resistance of the resistor R2 is: 4.7K Ω, the resistance of resistance R3 is: 4.7K Ω, the resistance of resistance R4 is: 10K Ω, the resistance of the resistor R5 is: 10K Ω, the resistance of the resistor R6 is: 100 Ω, resistance R7 is: 4.7K Ω, the resistance of resistance R8 is: 10K Ω, the resistance of the resistor R9 is: 2K Ω, the resistance of the resistor R10 is: 4.7K omega.

The utility model has the advantages of

The utility model solves the problem that two instruments can carry out serial half-duplex communication through a two-wire system bus. By adopting the two-wire system, communication wires can be saved, construction is convenient, and the misoperation rate of workers is reduced.

Drawings

FIG. 1 is a circuit configuration diagram of the present invention

Detailed Description

The utility model is further illustrated by the following examples, without limiting the scope of the utility model:

the utility model discloses an interface conversion circuit for converting a four-wire system TTL interface into a two-wire system bus, which consists of a connecting terminal CON4 connected with the four-wire system TTL interface, a connecting terminal CON2 connected with the two-wire system bus and discrete active and passive components, wherein the interface conversion circuit can enable instrument equipment connected to the TTL interface and instrument equipment connected to the two-wire system bus to realize half-duplex serial port communication.

Referring to fig. 1, the connection terminal CON4 has four pins, which are respectively a 1-pin power supply VCC, a 2-pin transmitting pin TXD, a 3-pin receiving pin RXD, and a 4-pin ground; the connecting terminal CON2 is provided with two pins which are respectively 1-pin BUS and 2-pin BUS +; when the four-wire system TTL interface sends signals, a sending pin TXD is at a low level, a receiving pin RXD is at a high level, and a BUS + pin is at a high level; when the two-wire BUS BUS sends signals, the BUS + pin is at a high level, the receiving pin RXD is at a low level, and the sending pin TXD is at a high level.

With reference to fig. 1, the interconnection relationship between the discrete active and passive components, the connection terminal CON4, and the connection terminal CON2 is as follows:

CON2 terminal 1 pin BUS-ground;

the CON4 terminal 1 pin is connected with a voltage VCC;

CON4 is pin 4 grounded.

In a preferred embodiment, the diode D1 is of the type: SMBJ12A, diode D2 model: 4148.

in a preferred embodiment, the capacitance and the withstand voltage of the capacitor C1 are as follows: 10 nF/50V.

In a preferred embodiment, the resistance value of the resistor R1 is: 2K Ω, the resistance of the resistor R2 is: 4.7K Ω, the resistance of resistance R3 is: 4.7K Ω, the resistance of resistance R4 is: 10K Ω, the resistance of the resistor R5 is: 10K Ω, the resistance of the resistor R6 is: 100 Ω, resistance R7 is: 4.7K Ω, the resistance of resistance R8 is: 10K Ω, the resistance of the resistor R9 is: 2K Ω, the resistance of the resistor R10 is: 4.7K omega.

The circuit realizes the following functions:

1. during sending, the TTL interface is converted into a two-wire bus, two or more instrument devices can be hung on the two buses to realize half-duplex serial port communication, and during receiving, signals are received through the two-wire bus and then converted into the TTL interface.

2. The BUS voltage isolation circuit has a voltage isolation function, a normal BUS is in a low level state, a BUS + and a BUS-are connected through a resistor R1, and the BUS is in a communication working state when the BUS has voltage of more than 1.5V.

3. Half-duplex transmission function:

(1) the pin RXD is connected with a sending pin of the equipment, the pin RXD is normally in a high-level PNP1 triode and is in a cut-off state, when the pin RXD receives a low-level signal, the triode PNP1 is in saturated conduction, current flows from a power supply VCC to a bus through the triode PNP1, the diode D2 and the current-limiting resistor R6, and the bus has high level (> 1.5V). At the same time, the current flows through the resistors R7 and R8 to make the transistor NPN2 in a saturated conducting state, the resistor R3 is pulled low by the collector of the transistor NPN2 to make the transistor NPN1 in a cut-off state, and the resistor R5 is pulled up to the power supply VCC to make the TXD pin in a high level.

(2) When the pin RXD returns to high level, the transistor PNP1 is cut off, the bus is pulled down to ground through the resistor R1 to return to low level, meanwhile, the resistors R2, R3 and R4 are in low level, the transistor NPN1 is in cut-off state, and the pin TXD is in high level.

(3) When the transistor PNP1 is turned on, the capacitor C1 is charged through the resistor R9, and when the transistor PNP1 is turned off, the capacitor C1 is discharged through the resistors R9, R7, and R8, so that the transistor NPN2 maintains a saturated on state until the bus level is in a low state. The purpose is to prevent the TXD pin from glitching at the instant the transistor PNP1 turns off, which is caused by the momentary conduction of the transistor NPN1 by the charge maintained by the bus parasitic capacitance.

4. Half-duplex reception function:

(1) when BUS BUS + is low, resistors R2, R3, R4 have no current flowing, transistor NPN1 is off, and resistor R5 is pulled up to power VCC, causing the TXD pin to be high.

(2) When the BUS BUS + is at a high level, the resistors R2, R3 and R4 have current flowing through them, the transistor NPN1 is in a saturated conduction state, and the TXD pin is at a low level.

(3) When the BUS BUS + is at a high level, the diode D2 is in a cut-off state, the transistor PNP1 is in a cut-off state, and therefore no current flows through the resistor R7, the resistor R8 and the transistor NPN2 are in a cut-off state, and the operation of the receiving transistor NPN1 is not influenced.

The specific embodiments described herein are merely illustrative of the spirit of the utility model. Various modifications or additions may be made to the described embodiments, or alternatives may be employed, by those skilled in the art, without departing from the spirit or ambit of the utility model as defined in the appended claims.

Claims

1. The interface conversion circuit is characterized by consisting of a connecting terminal CON4 connected with the four-wire system TTL interface, a connecting terminal CON2 connected with the two-wire system bus and discrete active and passive components, and can enable instrument equipment connected to the TTL interface and instrument equipment connected to the two-wire system bus to realize half-duplex serial port communication.

2. The circuit of claim 1, wherein: the connecting terminal CON4 has four pins, namely a 1-pin power VCC, a 2-pin transmitting pin TXD, a 3-pin receiving pin RXD and a 4-pin grounding respectively; the connecting terminal CON2 is provided with two pins which are respectively 1-pin BUS and 2-pin BUS +; when the four-wire system TTL interface sends signals, a sending pin TXD is at a low level, a receiving pin RXD is at a high level, and a BUS + pin is at a high level; when the two-wire BUS BUS sends signals, the BUS + pin is at a high level, the receiving pin RXD is at a low level, and the sending pin TXD is at a high level.

3. The circuit of claim 1, wherein: the discrete active and passive components, the connection terminal CON4 and the connection terminal CON2 are connected with each other as follows:

CON2 terminal 1 pin BUS-ground;

the CON4 terminal 1 pin is connected with a voltage VCC;

CON4 is pin 4 grounded.

4. The circuit of claim 3, wherein the diode D1 is of the type: SMBJ12A, diode D2 model: 4148.

5. the circuit of claim 3, wherein the capacitance and withstand voltage of the capacitor C1 are: 10 nF/50V.

6. The circuit of claim 3, wherein the resistance R1 has a value of: 2K Ω, the resistance of the resistor R2 is: 4.7K Ω, the resistance of resistance R3 is: 4.7K Ω, the resistance of resistance R4 is: 10K Ω, the resistance of the resistor R5 is: 10K Ω, the resistance of the resistor R6 is: 100 Ω, resistance R7 is: 4.7K Ω, the resistance of resistance R8 is: 10K Ω, the resistance of the resistor R9 is: 2K Ω, the resistance of the resistor R10 is: 4.7K omega.