CN213718281U - Electronic device - Google Patents
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- CN213718281U CN213718281U CN202022144351.3U CN202022144351U CN213718281U CN 213718281 U CN213718281 U CN 213718281U CN 202022144351 U CN202022144351 U CN 202022144351U CN 213718281 U CN213718281 U CN 213718281U
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Abstract
The embodiment of the application discloses an electronic device, includes: the double data rate synchronous dynamic memory comprises at least one double data rate synchronous dynamic memory, a processor and a circuit board assembly, wherein the circuit board assembly is provided with a plurality of through holes, the plurality of through holes comprise a plurality of first through holes positioned below the double data rate synchronous memory and a plurality of second through holes positioned below the processor, and the plurality of first through holes and the plurality of second through holes are connected through a plurality of first electric connecting wires; the projection of at least one first electric connection line in the plurality of first electric connection lines on a first plane is at least partially overlapped with the projection of the gaps of the plurality of first through holes on the first plane, so that at least part of the plurality of first electric connection lines in the plurality of first electric connection lines can be arranged below the double data rate synchronous dynamic memory and the memory, the area of the circuit board assembly is reduced, and the development trend of miniaturization of the electronic device is facilitated.
Description
Technical Field
The present application relates to the field of electronic technology, and in particular, to an electronic device.
Background
With the development of electronic technology, the application of high frequency memories is becoming more common and has been gradually applied to various electronic devices. However, the existing electronic devices with high frequency memories have large volumes and are not suitable for the development trend of miniaturization of electronic devices.
SUMMERY OF THE UTILITY MODEL
In order to solve the above technical problems, the present application provides an electronic device to adapt to the trend of miniaturization of electronic devices on the basis of having a high frequency memory.
To solve the above problem, an embodiment of the present application provides an electronic device, including: the double data rate synchronous dynamic memory comprises at least one double data rate synchronous dynamic memory, a processor and a circuit board assembly, wherein the circuit board assembly is provided with a plurality of through holes, the plurality of through holes comprise a plurality of first through holes positioned below the double data rate synchronous memory and a plurality of second through holes positioned below the processor, and the plurality of first through holes and the plurality of second through holes are connected through a plurality of first electric connecting wires;
wherein a projection of at least one of the first electrical connection lines on a first plane at least partially overlaps a projection of gaps of the first vias on the first plane.
Optionally, the double data rate synchronous dynamic memory is a low-power consumption double data rate synchronous dynamic memory with a storage frequency not less than 4266 Mbps.
Optionally, the circuit board assembly includes a plurality of stacked circuit boards, and adjacent circuit boards are fixedly connected by an adhesive layer;
the circuit board comprises a substrate, at least one wiring layer located on a first surface of the substrate, and at least one wiring layer located on a second surface of the substrate, wherein the second surface is opposite to the first surface.
Optionally, the transmission loss of the adhesive layer is not greater than 0.015.
Optionally, the thickness of the substrate ranges from 3mil to 4mil, inclusive.
Optionally, the thickness of the substrate is 4 mil.
Optionally, the circuit board assembly further includes:
the annular electric connecting piece is positioned on the surface of the circuit board assembly, is annularly arranged around the through hole and is electrically contacted with the through hole; the outer diameter of the annular electric connecting piece ranges from 15mil to 17mil including the end point value.
Optionally, the annular electrical connector has an outer diameter of 16 mils.
Optionally, the distance between the processor and the double data rate synchronous dynamic memory is less than 15 mm.
Optionally, the electronic device includes: at least two double data rate synchronous dynamic memories, and the distance between the adjacent double data rate synchronous dynamic memories is less than 2.5 mm.
Compared with the prior art, the technical scheme has the following advantages:
the technical scheme provided by the embodiment of the application comprises the following steps: the double data rate synchronous dynamic memory comprises at least one double data rate synchronous dynamic memory, a processor and a circuit board assembly, wherein the circuit board assembly is provided with a plurality of through holes, the plurality of through holes comprise a plurality of first through holes positioned below the double data rate synchronous memory and a plurality of second through holes positioned below the processor, and the plurality of first through holes and the plurality of second through holes are connected through a plurality of first electric connecting wires; the projection of at least one first electric connection line in the plurality of first electric connection lines on a first plane is at least partially overlapped with the projection of the gaps of the plurality of first through holes on the first plane, so that at least part of the plurality of first electric connection lines in the plurality of first electric connection lines can be arranged below the double data rate synchronous dynamic memory, the area of the circuit board assembly occupied by the plurality of first electric connection lines except for the projection of the double data rate synchronous dynamic memory on the circuit board assembly can be reduced, the area of the circuit board assembly is further reduced, and the development trend of miniaturization of the electronic device is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of the relative positions of electrical connections electrically connecting a double data rate synchronous dynamic memory and a processor and the double data rate synchronous dynamic memory and the processor in a conventional electronic device;
fig. 2 is a partial cross-sectional view of an electronic device provided in an embodiment of the present application;
FIG. 3 is a schematic diagram of the relative positions of the electrical connection lines electrically connecting the DDR SDRAM and the processor and the DDR SDRAM and the processor in an electronic device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the relative positions of the electrical connection lines electrically connecting the double data rate synchronous dynamic memory and the processor and the double data rate synchronous dynamic memory and the processor in another electronic device provided by the embodiments of the present application;
fig. 5 is a schematic structural diagram of a circuit board assembly in an electronic device according to an embodiment of the present disclosure;
FIG. 6 is a partial cross-sectional view of another electronic device provided in an embodiment of the present application;
fig. 7 is a structural diagram of a circuit board in another electronic device provided in an embodiment of the present application;
fig. 8 is a structural diagram of a circuit board in another electronic device according to an embodiment of the present disclosure;
fig. 9 is a cross-sectional view of yet another electronic device provided by an embodiment of the present application;
fig. 10 is a partial cross-sectional view of yet another electronic device provided by an embodiment of the present application;
fig. 11 is a schematic distribution diagram of a processor and a double data rate synchronous dynamic memory in an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background section, the existing electronic devices with high frequency memories are bulky and are not suitable for the trend of miniaturization of electronic devices.
This is because in electronic devices, a high frequency memory is usually connected to a processor through a via plate (i.e., a circuit board with a via hole), and as the frequency of the memory is higher, the number of signals in the memory is larger, and accordingly, the number of signal lines connecting the memory and the processor is larger. As shown in fig. 1, in the conventional electronic device, the signal line 110 on the through-hole board 100 for connecting the memory 120 and the processor 90 is usually located in the peripheral region of the projection of the memory 120 and the processor 90 on the through-hole board 100, resulting in a larger size of the through-hole board 100, and thus a larger volume of the electronic device.
In view of this, the present application provides an electronic device, as shown in fig. 2, including: the double data rate synchronous dynamic memory comprises at least one double data rate synchronous dynamic memory 10, a processor 20 and a circuit board assembly 30, wherein the circuit board assembly 30 is provided with a plurality of through holes 40, the plurality of through holes comprise a plurality of first through holes 41 positioned below the double data rate synchronous memory 10 and a plurality of second through holes 42 positioned below the processor 20, and the plurality of first through holes 41 and the plurality of second through holes 42 are connected through a plurality of first electric connecting lines.
Specifically, in this embodiment of the present application, the double data rate synchronous dynamic memory is connected to a first via hole of the circuit board assembly located below the circuit board assembly, the processor is connected to a second via hole of the circuit board assembly located below the circuit board assembly, and the first via hole and the second via hole are connected to each other through a first electrical connection line, so as to connect the double data rate synchronous dynamic memory to the processor.
It should be noted that, in the embodiment of the present application, as shown in fig. 3, a projection of at least one of the first electrical connection lines 50 on a first plane at least partially overlaps a projection of gaps of the first through holes 41 on the first plane, that is, at least a portion of at least one of the first electrical connection lines 50 is located in a gap between two adjacent first through holes 41 in the first through holes 41, that is, at least a portion of at least one of the first electrical connection lines 50 passes through a gap between any two adjacent first through holes 41 in the first through holes 41, so as to dispose at least a portion of at least one of the first electrical connection lines 50 below the dual data rate synchronous dynamic memory 10, and on the premise that the total number of the first electrical connection lines 50 is unchanged, the area of the circuit board assembly 30 occupied by the first electrical connection lines 50 is reduced, except for the projection of the double data rate synchronous dynamic memory 10 on the circuit board assembly 30, the area of the circuit board assembly 30 is reduced, and the development trend of miniaturization of electronic devices is facilitated. Wherein, the first plane is the plane of the circuit board assembly.
Optionally, on the basis of the foregoing embodiment, in an embodiment of the present application, a projection of a plurality of first electrical connection lines in the plurality of first electrical connection lines on a first plane at least partially overlaps a projection of gaps of the plurality of first through holes on the first plane, so as to dispose at least part of the plurality of first electrical connection lines in the plurality of first electrical connection lines below the dual data rate synchronous dynamic memory, and on the premise that the total number of the plurality of first electrical connection lines is not changed, the area of a region of the circuit board assembly occupied by the plurality of first electrical connection lines except for the projection of the dual data rate synchronous dynamic memory on the circuit board assembly is further reduced, the area of the circuit board assembly is further reduced, and the development trend of miniaturization of the electronic device is facilitated.
Optionally, on the basis of the foregoing embodiment, in an embodiment of the present application, the double data rate synchronous dynamic memory is a low-power double data rate synchronous dynamic memory with a storage frequency of not less than 4266Mbps, so as to implement high-frequency signal storage, and is suitable for application requirements of high-frequency signal storage.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 4, a projection of at least one of the first electrical connection lines 50 on a first plane at least partially overlaps a projection of gaps of the second through holes 42 on the first plane, that is, at least a portion of at least one of the first electrical connection lines 50 is located in a gap between two adjacent second through holes 42 of the second through holes 42, that is, at least a portion of at least one of the first electrical connection lines 50 passes through a gap between any two adjacent second through holes 52 of the second through holes 52, so as to dispose at least a portion of at least one of the first electrical connection lines 50 below the processor 20, and on the premise that the total number of the first electrical connection lines 50 is unchanged, the area of the circuit board assembly 30, which is occupied by the first electrical connection lines 50 except for the projection of the double data rate synchronous dynamic memory 10 and the processor 20 on the circuit board assembly 30, is further reduced, the area of the circuit board assembly 30 is reduced, and the development trend of miniaturization of the electronic device is facilitated.
Optionally, on the basis of the foregoing embodiment, in an embodiment of the present application, a projection of a plurality of first electrical connection lines in the plurality of first electrical connection lines on a first plane at least partially overlaps a projection of gaps of the plurality of second through holes on the first plane, so as to dispose at least part of the plurality of first electrical connection lines in the plurality of first electrical connection lines below the processor, and on the premise that the total number of the plurality of first electrical connection lines is not changed, the area of the circuit board assembly occupied by the plurality of first electrical connection lines except for the projection of the dual data rate synchronous dynamic memory and the processor on the circuit board assembly is further reduced, the area of the circuit board assembly is further reduced, and the trend of miniaturization of the electronic device is facilitated.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 5, the circuit board assembly includes a plurality of stacked circuit boards 60, and in order to fixedly connect the plurality of stacked circuit boards 60 in the circuit board assembly, two adjacent circuit boards 60 are fixedly connected by an adhesive layer 70, so that the plurality of circuit boards 60 in the circuit board assembly can be mutually fixed, and the firmness of the circuit board assembly 30 is ensured.
On the basis of the above-described embodiments, in one embodiment of the present application, as shown in fig. 5, the circuit board 60 includes a substrate 61, and at least one routing layer 62 on a first surface of the substrate 61 and at least one routing layer 63 on a second surface of the substrate 61, wherein the second surface of the substrate 61 is opposite to the first surface.
Optionally, in an embodiment of the present application, each of the routing layers is a copper routing layer, but the present application does not limit this, as the case may be.
It should be noted that, when the first surface of the substrate has at least two routing layers, adjacent routing layers may be fixedly connected through an adhesive layer, and similarly, when the second surface of the substrate has at least two routing layers, adjacent routing layers may be fixedly connected through an adhesive layer, and when the first surface of the substrate has at least two routing layers, the manufacturing process for manufacturing the substrate may be simplified, but this application is not limited thereto, and is specifically determined as the case may be.
Optionally, in this embodiment of the application, as shown in fig. 6, the first through hole 41 and the second through hole 42 penetrate through the plurality of circuit boards 60, and the first through hole 41 and the second through hole 42 are connected by a trace in at least one trace layer, so as to implement signal transmission between the double data rate synchronous dynamic memory 10 and the processor 20.
It should be noted that, in this embodiment of the application, the first through hole and the second through hole all penetrate through the plurality of circuit boards, and the process difficulty of the first through hole and the second through hole can be reduced, so that the process difficulty of the circuit board assembly is reduced, the cost of the circuit board assembly is further reduced, and finally, the cost of the electronic device is reduced.
It should be further noted that, compared with the case where an electrical connection hole is formed between any two circuit boards separately to form a through hole penetrating through each circuit board, the electrical connection between the traces on each trace layer and the through hole is realized by setting the electrical connection relationship between the traces on each trace layer and the through hole, which can reduce the cost by about half.
Specifically, in an embodiment of the present application, each routing layer in the circuit board assembly includes a plurality of traces, and in an embodiment of the present application, one first electrical connection line may be formed by at least part of the traces in one routing layer, that is, a first through hole and a second through hole electrically connected to the first electrical connection line may be connected by at least part of the traces in one routing layer; in another embodiment of the present application, a first electrical connection line may be composed of at least some traces in at least two trace layers, that is, a first via and a second via electrically connected to the first electrical connection line may be connected by at least some traces in at least two trace layers, which is not limited in this application, as the case may be.
In the following, a first electrical connection line may be formed by at least some traces in one trace layer, that is, a first via and a second via electrically connected to the first electrical connection line may be connected by at least some traces in one trace layer. For convenience of description, a routing layer for transmitting signals is defined as a signal transmission layer, two routing layers located at two sides of the signal transmission layer and adjacent to the signal transmission layer are defined as a first signal reference layer and a second signal reference layer, and as shown in fig. 6, for example, the signal transmission layer is a routing layer L4, and the first signal reference layer and the second signal reference layer are a routing layer L3 and a routing layer L5, respectively, but the present application does not limit this, depending on the situation.
The inventors have studied and found that, as shown in fig. 7, the impedance of the trace in the signal transmission layer 64 is related to the distance between the first signal reference layer 65 and the second signal reference layer 66, the dielectric constant of the insulating layer between the first signal reference layer 65 and the second signal reference layer 66, the thickness of the trace in the signal transmission layer 64, and the width of the trace in the signal transmission layer 64. Specifically, the calculation formula of the impedance of the wires in the signal transmission layer is as follows:
wherein Z is the impedance of the trace of the signal transmission layer; h is the distance between the first signal reference layer and the second signal reference layer; t is the thickness of the wiring in the signal transmission layer; w is the width of the wiring in the signal transmission layer; ε is the dielectric constant of the insulating layer between the first signal reference layer and the second signal reference layer.
As can be seen from the calculation formula of the impedance of the trace in the signal transmission layer, on the premise that the impedance Z of the trace on the signal transmission trace layer is fixed, the smaller the distance h between the first signal reference layer and the second signal reference layer is, the smaller the width w of the trace in the signal transmission layer is; the larger the dielectric constant epsilon of the insulating layer between the first signal reference layer and the second signal reference layer is, the smaller the impedance Z of the routing of the signal transmission layer is.
Specifically, in an embodiment of the present application, as shown in fig. 7 and 8, when the signal transmission layer 64 and the first signal reference 65 layer are insulated by the substrate 61 and the through hole adhesive layer 70 between the signal transmission layer 64 and the second signal reference layer 66 is insulated, when the trace impedance Z and the thickness of the adhesive layer 70 are fixed, the smaller the thickness of the substrate 61 is, the smaller the width of the trace of the signal transmission layer 64 is.
Therefore, on the basis of any one of the above embodiments, in an embodiment of the present application, the thickness of the substrate ranges from 3mil to 4mil, including the endpoint value, so that the width of the routing lines in the routing layers on both sides of the substrate is reduced on the premise that the signal transmission impedance of the circuit board is not changed, and therefore, on the premise that the number of the first electrical connection lines is not changed, the occupied space of the first electrical connection lines is reduced, the area of the circuit board assembly is reduced, and the development trend of miniaturization of the electronic device is facilitated.
It can also be seen from the impedance calculation formula of the trace of the signal transmission layer that, when the signal transmission impedance of the circuit board and the thickness of the substrate are fixed, the smaller the thickness of the adhesive layer is, the smaller the trace width of the signal transmission layer is.
It should be noted that, if the signal transmission layer and the first signal reference layer are insulated by a substrate and the signal transmission layer and the second signal reference layer are insulated by an adhesive layer, the dielectric constant of the insulating layer between the first signal reference layer and the second signal reference layer is determined by the dielectric constant of the substrate and the dielectric constant of the adhesive layer.
On the basis of any one of the above embodiments, in an optional embodiment of the present application, the thickness of the substrate is 4 mils, the thickness of the adhesive layer is 3 mils, so that the thickness of the substrate and the adhesive layer is reduced, on the basis of the width of the trace on the signal transmission layer, the dielectric constant between the first signal reference layer and the second signal reference layer is increased by setting the thickness of the substrate and the thickness of the adhesive layer, and further, on the premise that the signal transmission impedance of the circuit board is fixed, the width of the trace on the signal transmission layer is reduced.
It should be noted that, in the embodiment of the present application, after the width of the first electrical connection line is reduced, in addition to reducing the preset area occupied by the plurality of first electrical connection lines, the distance between adjacent first electrical connection lines may also be increased, so as to reduce signal interference between adjacent first electrical connection lines, where the preset area is an area excluding a projected area of the double data rate synchronous dynamic memory and the processor in the first plane.
Moreover, each wire in the wire routing layer has a smaller line width, so that the wire can be conveniently arranged in a gap between two adjacent first through holes or two adjacent second through holes, the gap between two adjacent first through holes in the plurality of first through holes and the gap between two adjacent second through holes in the plurality of second through holes are fully utilized, the area of the plurality of first electric connecting wires in a preset area is further reduced, the preset area is not overlapped with the projection of the double-data-rate synchronous dynamic memory on the circuit board assembly and the projection of the processor on the circuit board assembly, the area of the circuit board assembly is further reduced, and the wire routing layer is suitable for the development trend of miniaturization of electronic devices.
On the basis of any of the above embodiments, in an embodiment of the present application, in order to reduce transmission loss between two circuit boards performing signal transmission in the circuit board assembly, the transmission loss of the adhesive layer is not greater than 0.015, but the present application does not limit this, as the case may be.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 9 and 10, in order to facilitate the electrical connection between the first via 41 and the double data rate synchronous dynamic memory 10 and the electrical connection between the second via 42 and the processor 20, the circuit board assembly 30 further includes: and the annular connecting piece 80 is positioned on the surface of the circuit board assembly 30, is annularly arranged around the through hole and is electrically connected with the through hole. Specifically, the surface of the circuit board assembly is provided with a first annular connecting piece and a second annular connecting piece, the first annular connecting piece and the second annular connecting piece are annularly arranged around the first through hole, the double-data-rate synchronous dynamic memory is electrically connected with the first through hole through the first annular connecting piece, and the processor is electrically connected with the second through hole through the second annular connecting piece.
Optionally, on the basis of the foregoing embodiment, in an embodiment of the present application, an outer diameter of the ring-shaped electrical connector ranges from 15 mils to 17 mils, including end points, so as to reduce an occupied area of the ring-shaped electrical connector on a surface of the circuit board assembly and reduce an area of the circuit board assembly on the basis of ensuring an electrical connection performance of the ring-shaped electrical connector with the dual data rate synchronous dynamic memory or the processor, and is suitable for development of miniaturization of an electronic device.
It should be noted that, in the embodiment of the present application, the double data rate synchronous dynamic memory may be directly electrically connected to the first ring connector, or may be electrically connected to the first ring connector through a second electrical connection line. When the double data rate synchronous dynamic memory is electrically connected with the first annular connecting piece through the second electric connecting line, the outer diameter size of the first annular electric connecting piece is smaller, so that more second electric connecting lines can be arranged in the gap between the adjacent first through holes on the surface of the circuit board assembly on the premise that the density of the first through holes in the circuit board assembly is not changed, the area increase of the circuit board assembly caused by the arrangement of the second electric connecting line is reduced, the miniaturization of the circuit board assembly is facilitated, and the double data rate synchronous dynamic memory is suitable for the development trend of miniaturization of electronic devices.
Similarly, in the embodiment of the present application, the processor may be electrically connected to the second annular connecting element directly, or may be electrically connected to the second annular connecting element through a third electrical connection line. When the processor is electrically connected with the second annular connecting piece through the third electric connecting line, the outer diameter of the second annular electric connecting piece is smaller, so that more third electric connecting lines can be arranged in the gap between the adjacent second through holes on the surface of the circuit board assembly on the premise that the density of the second through holes in the circuit board assembly is not changed, the increase of the area of the circuit board assembly caused by the arrangement of the third electric connecting lines is reduced, the miniaturization of the circuit board assembly is facilitated, and the electronic device is suitable for the development trend of miniaturization of electronic devices.
It should be noted that, in the embodiment of the present application, the outer diameter range of the annular connecting member is set to 15mil to 17mil, including an endpoint value, only the outer diameter of the annular connecting member is changed, and the inner diameter of the annular connecting member is not changed, that is, the diameter of the through hole is not changed, so that the electronic device provided in the embodiment of the present application may not change the layout of the first electrical connection lines electrically connecting the first through holes and the second through holes on the basis of reducing the occupied area of the annular connecting member.
In addition to the above embodiments, in an optional embodiment of the present application, the annular electrical connection member has an outer diameter of 16 mils, so as to improve the electrical connection performance between the dual data rate synchronous dynamic memory and the first via and between the processor and the second via on the basis of reducing an area occupied by the annular electrical connection wire, but the present application is not limited thereto, as the case may be.
On the basis of any of the above embodiments, in an embodiment of the present application, the plurality of first vias and the plurality of second vias correspond to the double data rate synchronous dynamic memory and the processor, respectively, wherein the annular electric connecting pieces are arranged around the plurality of first through holes and the plurality of second through holes, the outer diameter of each annular electric connecting piece is smaller, and the line width of the first electric connection lines electrically connecting the double data rate synchronous dynamic memory and the processor is smaller, and the occupied area is smaller, therefore, the electronic device provided by the embodiment of the application, the space between the processor and the double data rate synchronous dynamic memory for placing the plurality of first electrical connection lines and the ring connector may be reduced, thereby reducing the distance between the processor and the double data rate synchronous dynamic memory.
Optionally, in this embodiment of the present application, as shown in fig. 11, a distance y between the processor 20 and the double data rate synchronous dynamic memory 10 is less than 15mm, a length of a signal line between the processor 20 and the double data rate synchronous dynamic memory 10 is shortened, a signal transmission loss between the processor 20 and the double data rate synchronous dynamic memory 10 is reduced, and a size of an entire assembly of the double data rate synchronous dynamic memory 10, the processor 20, and the circuit board assembly 30 is reduced, which is suitable for a trend of miniaturization of electronic devices.
On the basis of any of the embodiments described above, in an embodiment of the present application, as shown in fig. 11, the electronic device includes: at least two double data rate synchronous dynamic memories 10.
It should be noted that, in the embodiment of the present application, since the outer diameter of the ring-shaped electrical connector is small, and the first electrical connection lines are partially located in the gaps between the adjacent first through holes, the area of the preset area required by the first electrical connection lines is reduced, so that the adjacent double data rate synchronous dynamic memories can be arranged more compactly, and the distance between the adjacent double data rate synchronous dynamic memories is reduced. Wherein the preset region is a region of the circuit board assembly outside a projected area of the double data rate synchronous dynamic memory and the processor.
Optionally, in an embodiment of the present application, the distance x between the double data rate synchronous dynamic memories 30 is less than 2.5mm, so that when the electronic device includes at least two double data rate synchronous dynamic memories, the size of the whole of at least two double data rate synchronous dynamic memories, the processor and the circuit board assembly is reduced by reducing the distance between adjacent double data rate synchronous dynamic memories, which is suitable for the development trend of miniaturization of electronic devices.
In summary, the electronic device provided in the embodiment of the present application includes: the double data rate synchronous dynamic memory comprises at least one double data rate synchronous dynamic memory, a processor and a circuit board assembly, wherein the circuit board assembly is provided with a plurality of through holes, the plurality of through holes comprise a plurality of first through holes positioned below the double data rate synchronous memory and a plurality of second through holes positioned below the processor, and the plurality of first through holes and the plurality of second through holes are connected through a plurality of first electric connecting wires; the projection of at least one first electric connection line in the plurality of first electric connection lines on a first plane is at least partially overlapped with the projection of the gaps of the plurality of first through holes on the first plane, namely at least one first electric connection line in the plurality of first electric connection lines is positioned between the plurality of first through holes, so that the area of the circuit board assembly occupied by the plurality of first electric connection lines except for the projection of the double data rate synchronous dynamic memory and the storage on the circuit board assembly is reduced, the area of the circuit board assembly is further reduced, and the development trend of miniaturization of the electronic device is facilitated.
In addition, in the electronic device provided by the embodiment of the application, the thickness of the substrate in the circuit board assembly is smaller, and on the premise that the signal transmission impedance of the circuit board assembly is not changed, the width of the routing lines on two sides of the substrate can be reduced, the occupied space of the plurality of first electric connection lines is reduced, and then the area of the circuit board assembly is reduced, so that the miniaturization development trend of the electronic device is facilitated, the distance between the adjacent first electric connection lines can be increased, and the signal interference between the adjacent first electric connection lines is reduced.
In addition, the electronic device provided by the embodiment of the application further utilizes the annular electric connector with a smaller outer diameter to realize the electric connection between the processor and the second through hole and the electric connection between the double data rate synchronous dynamic memory and the first through hole, so that the length of a signal wire between the processor and the double data rate synchronous dynamic memory is shortened, the signal transmission loss between the processor and the double data rate synchronous dynamic memory is reduced, meanwhile, the size of the whole formed by the double data rate synchronous dynamic memory, the processor and the circuit board assembly is also reduced, and the electronic device is suitable for the development trend of miniaturization of electronic devices.
Therefore, the electronic device provided by the embodiment of the application can reduce the size of the circuit board assembly, is suitable for the development trend of miniaturization of the electronic device, and can also enable the signal distance of transmission signals to be increased, reduce crosstalk among the signals, shorten the length of signal lines and reduce signal transmission loss.
All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.
In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An electronic device, comprising: the double data rate synchronous dynamic memory comprises at least one double data rate synchronous dynamic memory, a processor and a circuit board assembly, wherein the circuit board assembly is provided with a plurality of through holes, the plurality of through holes comprise a plurality of first through holes positioned below the double data rate synchronous memory and a plurality of second through holes positioned below the processor, and the plurality of first through holes and the plurality of second through holes are connected through a plurality of first electric connecting wires;
wherein a projection of at least one of the first electrical connection lines on a first plane at least partially overlaps a projection of gaps of the first vias on the first plane.
2. The electronic device according to claim 1, wherein the double data rate synchronous dynamic memory is a low power consumption double data rate synchronous dynamic memory having a memory frequency of not less than 4266 Mbps.
3. The electronic device of claim 1, wherein the circuit board assembly comprises a plurality of stacked circuit boards, adjacent ones of the circuit boards being fixedly connected by an adhesive layer;
the circuit board comprises a substrate, at least one wiring layer located on a first surface of the substrate, and at least one wiring layer located on a second surface of the substrate, wherein the second surface is opposite to the first surface.
4. The electronic device of claim 3, wherein the adhesive layer has a transmission loss of no greater than 0.015.
5. The electronic device of claim 3, wherein the substrate has a thickness ranging from 3 mils to 4 mils, inclusive.
6. The electronic device of claim 3, wherein the substrate has a thickness of 4 mils.
7. The electronic device of claim 1, wherein the circuit board assembly further comprises:
the annular electric connecting piece is positioned on the surface of the circuit board assembly, is annularly arranged around the through hole and is electrically contacted with the through hole;
the outer diameter of the annular electric connecting piece ranges from 15mil to 17mil including the end point value.
8. The electronic device of claim 7, wherein the annular electrical connector has an outer diameter of 16 mils.
9. The electronic device of claim 1, wherein a distance between the processor and the double data rate synchronous dynamic memory is less than 15 mm.
10. The electronic device of claim 1, wherein the electronic device comprises: at least two double data rate synchronous dynamic memories, and the distance between the adjacent double data rate synchronous dynamic memories is less than 2.5 mm.
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| CN202022144351.3U CN213718281U (en) | 2020-09-25 | 2020-09-25 | Electronic device |
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| CN202022144351.3U CN213718281U (en) | 2020-09-25 | 2020-09-25 | Electronic device |
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