CN213715385U

CN213715385U - Terahertz chip test system

Info

Publication number: CN213715385U
Application number: CN202021668353.6U
Authority: CN
Inventors: 许奔; 骆睿
Original assignee: Shenzhen Huaxun Ark Photoelectric Technology Co Ltd
Current assignee: Shenzhen Huaxun Ark Photoelectric Technology Co Ltd
Priority date: 2020-08-11
Filing date: 2020-08-11
Publication date: 2021-07-16
Anticipated expiration: 2030-08-11

Abstract

The application discloses terahertz chip's test system now, this test system includes: the terahertz chip is bound on the PCB and is connected with the test circuit; the test circuit is used for receiving a high-frequency signal through the signal bonding pad and inputting a test signal to the terahertz chip so as to test the terahertz chip; the test circuit comprises a high-frequency signal pin, the signal bonding pad is connected with the high-frequency signal pin through a signal gold wire, the length of the signal gold wire is smaller than or equal to 0.5941mm, and the length of the signal gold wire is larger than or equal to 0.4242 mm. By means of the mode, the test efficiency can be improved, and the cost is reduced.

Description

Terahertz chip test system

Technical Field

The application relates to the technical field of chip testing, in particular to a terahertz chip testing system.

Background

In the development process of radio frequency, millimeter wave and terahertz chips, bare chips need to be packaged and performance tested, at present, a mixed package test mode of a probe station and a Printed Circuit Board (PCB) is usually adopted for testing the gigahertz frequency chips, that is, a high-frequency pin of the test chip is clamped by the probe station, and a test mode bound to a Printed Circuit Board Assembly (PCBA) is adopted for a low-frequency pin of the chip.

SUMMERY OF THE UTILITY MODEL

The application provides a terahertz chip's test system now, can improve efficiency of software testing, reduce cost.

In order to solve the above technical problem, a technical scheme adopted in the present application is to provide a test system for a terahertz chip, where the test system includes: the terahertz chip is bound on the PCB and is connected with the test circuit; the test circuit is used for receiving a high-frequency signal through the signal bonding pad and inputting a test signal to the terahertz chip so as to test the terahertz chip; the test circuit comprises a high-frequency signal pin, the signal bonding pad is connected with the high-frequency signal pin through a signal gold wire, the length of the signal gold wire is smaller than or equal to 0.5941mm, and the length of the signal gold wire is larger than or equal to 0.4242 mm.

Through the scheme, the beneficial effects of the application are that: binding all pins of the terahertz chip on a PCB, directly testing the PCB during testing, connecting a signal bonding pad with a high-frequency signal pin on the terahertz chip through a signal gold wire, so that the high-frequency signal pin of the terahertz chip can receive a high-frequency signal, inputting a test signal to the terahertz chip according to the high-frequency signal, and testing whether the corresponding pin of the terahertz chip can normally work or not; compare and utilize the probe station to test, the scheme that this application adopted is lower to the requirement of PCB board test, can directly utilize the commonly used test instruments such as the external oscilloscope of signal pad to realize the capability test to the high frequency signal pin to can effectually save the cost, possess the advantage that the test ageing is high, the expense is low and the retest is swift, and conveniently carry out functional test in the external environment, the adaptability is higher.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

fig. 1 is a schematic structural diagram of an embodiment of a test system of a terahertz chip provided by the present application;

FIG. 2 is a schematic diagram of a PCB, a test circuit, and a signal pad provided in the present application;

FIG. 3 is an enlarged schematic view of the detail area A of FIG. 2;

FIG. 4 is another schematic diagram of the PCB, the test circuit and the signal pad provided by the present application;

FIG. 5 is an enlarged schematic view of the detail area A of FIG. 4;

FIG. 6 is a schematic structural diagram of another embodiment of a terahertz chip testing system provided by the present application;

FIG. 7 is a schematic diagram of the first power supply circuit in the embodiment shown in FIG. 6;

FIG. 8 is a schematic diagram of the DC bias circuit in the embodiment shown in FIG. 6;

FIG. 9 is a schematic diagram of the connection between the clock circuit and the terahertz chip in the embodiment shown in FIG. 6;

FIG. 10 is a schematic diagram of the structure of the transmitting circuit in the embodiment shown in FIG. 6;

fig. 11 is a schematic diagram of the structure of the receiving circuit in the embodiment shown in fig. 6.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1 to fig. 3, fig. 1 is a schematic structural diagram of an embodiment of a test system of a terahertz chip provided in the present application, the test system including: PCB board 10, test circuit 20, and signal pads 40.

The terahertz chip 20 and the signal bonding pad 40 are arranged at intervals; specifically, the high-frequency signal pin 21 and the signal pad 40 are disposed at an interval, and the high-frequency signal pin 21 and the signal pad 40 may be connected by a signal gold wire 41.

Further, the length of the signal gold wire 41 is less than or equal to 0.5941mm, and the length of the signal gold wire 41 is greater than or equal to 0.4242mm, which may be 0.5941mm, 0.5296mm, 0.5000mm, 0.4300mm, or 0.4242mm, and is not limited herein.

The terahertz chip 30 is bound on the PCB 10, the test circuit 20 is arranged on the PCB 10, and the test circuit 20 is connected with the terahertz chip 30; specifically, the size of the PCB 10 may be 110mm × 75mm, a 4-layer stacked design may be adopted, the PCB 10 may be made of an RF-4 plate, the analog bandwidth of the PCB 10 may be 14.75GHz, the PCB 10 is further provided with a plurality of pads, the pads may be connected to an external device and the terahertz chip 30, the pads may be divided into a radio frequency pad and a common pad, the radio frequency pad on the PCB 10 may be disposed closer to the terahertz chip 30, the common pad on the PCB 10 may be disposed in a radial manner, the radio frequency process design is processed in a flooring manner, and specifically, the radio frequency pad may include the signal pad 40.

The test circuit 20 is configured to receive a high-frequency signal and input a test signal to the terahertz chip 30 to test the performance of the terahertz chip 30.

The signal bonding pad 40 is arranged on the PCB 10, and the signal bonding pad 40 is connected with the high-frequency signal pin 21 on the terahertz chip 20 through the signal gold wire 41, so that the performance test of the high-frequency signal pin 21 can be realized by directly utilizing the signal bonding pad 40; the specific test procedure may be as follows: after the high-frequency clock signal is input into the terahertz chip 20, the high-frequency clock signal can be output through the high-frequency signal pin 21, the signal gold wire 41 and the signal bonding pad 40 through a series of processing, and then the output high-frequency clock signal can be processed by externally connecting a detection device such as an oscilloscope on the signal bonding pad 40, so that the performance test of the high-frequency signal pin 21 is completed.

Namely, the terahertz chip 20 can be packaged by using the PCB 10, the signal pad 40 is arranged on the PCB 10, and the high-frequency signal pin 21 and the signal pad 40 are further connected by the signal gold wire 41, so that the test on the high-frequency signal pin 21 on the terahertz chip 20 can be realized.

In an optional scenario, the length of the signal gold wire 41 directly affects the frequency of the high-frequency signal pin 21 to be tested, i.e. the length of the signal gold wire 41 needs to satisfy the following condition:

wherein L is the length of the signal gold wire 41, Trise is the signal rise time, L is the inductance per unit length of the signal gold wire 41, and C is the capacitance per unit length of the signal gold wire 41; optionally, because the impedance between the high-frequency signal pin 21 and the signal pad 40 is discontinuous, the high-frequency signal pin 21 is connected to the signal pad 40 through the signal gold wire 41, the signal gold wire 41 is actually also a discontinuous transmission line, and when the length of the discontinuous transmission line is less than the length of one sixth of the rise time signal transmission, the discontinuous transmission line can be regarded as a continuous transmission line.

Wherein v is the transmission rate of the electromagnetic wave in the medium, c is the transmission rate of the electromagnetic wave in vacuum, and Er is the relative dielectric constant of the transmission medium.

Combining equation 1 and equation 2, equation 3 can be obtained as follows:

and when the length l of the signal gold wire 41 is less than or equal to 0.5941mm and greater than or equal to 0.4242mm, the longest 0.5941mm is used for calculation, the actual value of Trise can be obtained as 1.1882 × 10-10S, and optionally, because the transmission line adopted in the application is the signal gold wire 41, the sine wave high-frequency clock signal with the length capable of meeting 3GHZ can be calculated. That is, the length of the signal gold wire 41 designed in the present application is enough to satisfy the high frequency clock signal with Ghz level frequency, that is, the test requirement of the high frequency signal pin 21 in the present application can be satisfied.

In addition, in terms of cost, in the existing scenario, because the probe station is expensive and needs to be maintained in real time, the probe station is generally configured only by a special testing company, and after the chip design is completed, the chip needs to be sent to the special testing company to complete the test, which often takes several weeks and is very expensive in testing price. Time cost and money cost are all high, and this application can directly utilize equipment such as signal pad 40 and oscilloscope commonly used to realize the test, and efficiency is fast and consume for a short time, can in time discover the problem to the flow of very big acceleration chip design.

In the above embodiment, the signal pad 40 is arranged on the PCB 10, and the signal pad 40 and the high-frequency signal pin 21 on the terahertz chip 20 are connected by the signal gold wire 41, so that the performance test on the high-frequency signal pin 21 can be directly realized by using a common test instrument such as an oscilloscope externally connected to the signal pad 40, and the cost can be effectively saved.

In an optional embodiment, at least a portion of the signal gold wire 41 is spaced apart from the PCB 10, that is, the signal gold wire 41 is disposed in a floating manner with respect to the PCB 10, so that the processing requirement can be effectively reduced, that is, manual soldering can also be achieved.

In another alternative embodiment, an ink layer (not shown) is further disposed on the PCB board 10, and the signal gold wires 41 are attached to the ink layer. Through pasting signal gold thread 41 and locating the printing ink layer is favorable to signal gold thread 41's steadiness on the one hand, is difficult to the fracture, and on the other hand compares in floating the setting, can effectual reduction signal gold thread 41's length, and then can reach higher test standard, and paste signal gold thread 41 and locate on the printing ink layer, peripheral medium also changes to some extent, not only air, therefore Er in the formula 2 has also changed, compares the air medium and improves, thereby improvement test standard that can be further.

As shown in fig. 4 and 5, the terahertz chip 30 further includes two reference signal pins 22 disposed on both sides of the high-frequency signal pin 21 and two ground pads 50 disposed on the PCB board 10. The two ground pads 50 are connected to the two reference signal pins 22 in a one-to-one correspondence by the reference gold wires 51, and the two reference gold wires 51 and the signal gold wires 41 do not intersect each other. That is, each ground pad 50 is connected to the corresponding reference signal pin 22 by only one reference gold wire 51. And two reference gold lines 51 are provided in parallel with the signal gold line 41.

By providing two ground pads 50 and reference gold wires 51, when a high-frequency clock signal enters the high-frequency signal pin 21 from the signal pad 40 via the signal gold wire 41, a return signal having the same frequency returns to the two ground pads 50 via the reference signal pin 22 and the reference gold wire 51. Since mutual inductance M is generated between the reference gold wire 51 and the signal gold wire 41, and when the current directions of the reference gold wire 51 and the signal gold wire 41 are the same, M is greater than 0, and when the currents of the reference gold wire 51 and the signal gold wire 41 are opposite, M is less than 0, since the high-frequency clock signal and the return signal are opposite, mutual inductance M is generated between the reference gold wire 51 and the signal gold wire 41 and is less than 0, the overall inductance of the whole structure can be reduced, and the signal transmission is facilitated. The scheme provided by the application can meet the bandwidth requirement of 14.75Ghz, and can meet the bandwidth requirement of 18.75GHz under certain conditions.

In other embodiments, the pitch between the high-frequency signal pin 21 and the adjacent reference signal pin 22 is less than or equal to 0.1200mm, and the pitch between the high-frequency signal pin 21 and the adjacent reference signal pin 22 is greater than or equal to 0.0889mm, which may be 0.1200mm, 0.900mm, or 0.0889mm, and is not limited herein.

In an alternative embodiment, the pitch between the high frequency signal pins 21 and the adjacent reference signal pins 22 may be 0.1000mm, subject to the requirements of conventional processing requirements and required test standards.

The distance between the ground pad 50 and the signal pad 40 is greater than or equal to 0.1300mm, and the distance between the ground pad 50 and the signal pad 40 is less than or equal to 0.1700mm, which may be 0.1300mm, 0.1400 mm or 0.1700, and is not limited herein.

In an alternative embodiment, ground pads 50 are spaced 0.1554mm from signal pads 40 as required to meet conventional processing requirements and required test standards.

Optionally, since the reference gold wire 51 and the signal gold wire 41 are not parallel, the distance between the reference gold wire 51 and the signal gold wire 41 is based on the shortest distance, and the shortest distance is less than or equal to 0.1200mm, and greater than or equal to 0.0889mm, and may specifically be 0.1200mm, 0.9000mm, or 0.0889mm, which is not limited herein.

Optionally, under the conditions that the length of the signal gold wire 41 is 0.5296mm, the distance between the high-frequency signal pin 21 and the adjacent reference signal pin 22 can be 0.1000mm, and the distance between the ground pad 50 and the signal pad 40 is 0.1554mm, the test requirement of the 14.75GHz bandwidth can be met, and based on the existing common processing density in China at present, the processing difficulty of the numerical values can be commonly realized by most processing plants in China, namely, most companies or factories can produce the test system, so that the whole test system is very simple and convenient to manufacture, and the process cost is low. Compared with the scheme of the prior art which needs to pass through the probe station, the method has extremely low cost and extremely high efficiency, and is one important advantage of the scheme, namely low cost and universality.

Furthermore, the length of the signal gold wire 41, the distance between the high-frequency signal pin 21 and the adjacent reference signal pin 22, and the distance between the ground pad 50 and the signal pad 40 can be further reduced, so that the bandwidth requirement of the test can be effectively improved.

By arranging the signal bonding pad 40 on the PCB 10 and connecting the signal bonding pad 40 and the high-frequency signal pin 21 on the terahertz chip 20 through the signal gold wire 41, the performance test of the high-frequency signal pin 21 can be realized by directly connecting the signal bonding pad 40 with common test instruments such as an oscilloscope and the like, so that the cost can be effectively saved; and the length of the signal gold wire 41, the distance between the high-frequency signal pin 21 and the adjacent reference signal pin 22, the distance between the grounding pad 50 and the signal pad 40 and other parameters can be realized based on the existing common processing requirements in China, so that the whole test system can be well popularized, and the cost can be well optimized.

In a specific embodiment, the high-frequency signal includes a high-frequency clock signal, the signal input by the test circuit 20 to the terahertz chip through the pad further includes a first power supply signal and a second power supply signal, and the test signal input by the test circuit 20 to the terahertz chip 30 includes the high-frequency clock signal, a first power supply signal and a bias signal.

Further, the test system for the terahertz chip further includes a first power supply pad and a second power supply pad (not shown in the figure), and the test circuit 20 includes: a first power supply circuit 21, a dc bias circuit 22, and a clock circuit 23.

The first power supply circuit 21 is connected with the terahertz chip 30, and is configured to receive a first power supply signal through a first power supply pad, process the first power supply signal to generate a first power supply signal, and input the first power supply signal to the terahertz chip 30; specifically, the first power signal and the first power signal may be direct current signals, and a voltage value of the first power signal is greater than a voltage value of the first power signal, that is, the first power supply circuit 21 may perform a boosting function, and provide the first power signal obtained by boosting to the terahertz chip 30; or the voltage value of the first power supply signal is smaller than that of the first power supply signal, that is, the first power supply circuit 21 can perform a voltage reduction function, and the first power supply signal obtained by voltage reduction is provided to the power supply pin of the terahertz chip 30; in addition, a ground signal can be input to the ground pin of the terahertz chip 30 through the first power supply circuit 21, so that whether the power pin of the terahertz chip 30 and the ground pin of the terahertz chip 30 are normal or not can be tested.

The direct current bias circuit 22 is connected to the terahertz chip 30, and is configured to receive a second power supply signal through a second power supply pad, process the second power supply signal to generate a bias signal, and input the bias signal to the terahertz chip 30; specifically, the dc bias circuit 22 may receive a second power signal sent by an external device, process the second power signal to obtain a bias signal, where the bias signal may be a dc signal, and then input the bias signal to the tuning pin of the terahertz chip 30 to test whether the tuning pin of the terahertz chip 30 is normal.

The clock circuit 23 is connected with the terahertz chip 30, and is used for receiving a high-frequency clock signal through a signal pad and inputting the high-frequency clock signal to the terahertz chip 30; specifically, the high-frequency signal pin includes a clock pin, and the clock circuit 23 may be connected to an external device, receive a high-frequency clock signal input by the external device, and transmit the high-frequency clock signal to the clock pin of the terahertz chip 30 to test whether the clock pin of the terahertz chip 30 is normal, where the high-frequency clock signal may be a high-frequency clock signal, for example, the frequency of the high-frequency clock signal is 1 GHz.

The embodiment provides a test system of a terahertz chip, binding all pins of the terahertz chip 30 on a PCB, directly testing the PCB 10 during chip testing, and inputting a test signal to the terahertz chip 30 through a first power supply circuit 21, a direct current bias circuit 22 and a clock circuit 23, thereby testing whether the terahertz chip 30 can normally work; the requirement of the embodiment on the test of the PCB 10 is much lower than that of a probe station, the PCB is more universal, more efficient, lower in cost and more convenient to repeat the test, and the test of the terahertz chip 30 is conveniently carried out in an external field environment.

Referring to fig. 6, fig. 6 is a schematic structural diagram of another embodiment of a terahertz chip testing system provided in the present application, the testing system including: the method comprises the following steps: the terahertz chip testing device comprises a PCB (printed circuit board) 10 and a testing circuit 20, wherein a terahertz chip 30 can be bound on the PCB 10 through silver glue, the testing circuit 20 is arranged on the PCB 10, and the testing circuit 20 is connected with the terahertz chip 30.

The test circuit 20 is configured to receive a high-frequency signal, and input a test signal to the terahertz chip 30 according to the high-frequency signal, so as to test the performance of the terahertz chip 30; specifically, the test circuit 20 includes: the test circuit comprises a first power supply circuit 21, a direct current bias circuit 22 and a clock circuit 23, wherein the high-frequency signal comprises a first power supply signal, a second power supply signal and a high-frequency clock signal, and the test signal comprises the first power supply signal, the bias signal and the high-frequency clock signal.

The first power supply circuit 21 is connected to the terahertz chip 30, and is configured to process the received first power supply signal to generate a first power supply signal, and input the first power supply signal to the terahertz chip 30.

Further, the first power supply circuit 21 includes: processing circuit 211 and filtering and stabilizing circuit 212.

The processing circuit 211 is configured to receive a first power signal, process the first power signal, and obtain a second power supply signal; specifically, the processing circuit 211 includes a voltage stabilizing common mode circuit 2111 and a first filter circuit 2112, where the voltage stabilizing common mode circuit 2111 is configured to receive a first power signal, stabilize the voltage of the first power signal, and suppress common mode noise; the first filtering circuit 2112 is connected to the voltage stabilizing common mode circuit 2111, and is configured to filter a signal output by the voltage stabilizing common mode circuit 2111 to obtain a second power supply signal.

The filtering and voltage stabilizing circuit 212 is connected to the processing circuit 211, and is configured to receive the second power supply signal, process the second power supply signal to obtain a first power supply signal, and input the first power supply signal to a power pin of the terahertz chip 30; specifically, the filtering and voltage stabilizing circuit 212 includes a second filter circuit 2121, a voltage stabilizing circuit 2122, and a third filter circuit 2123, and the second filter circuit 2121 is connected to the processing circuit 211 and is configured to filter the second power supply signal; the voltage stabilizing circuit 2122 is connected to the second filter circuit 2121, and configured to stabilize a signal output by the second filter circuit 2121; the third filter circuit 2123 is connected to the voltage regulator circuit 2122, and is configured to filter a signal output by the voltage regulator circuit 2122 to obtain a first power supply signal.

In a specific embodiment, as shown in fig. 7, the regulator-common-mode circuit 2111 includes a regulator tube Z and a common-mode inductor U1, where the regulator tube Z is configured to receive the first power signal and stabilize the voltage of the first power signal at a preset voltage; the first end of the common-mode inductor U1 is connected with one end of the voltage regulator tube Z, and the second end of the common-mode inductor U1 is connected with the other end of the voltage regulator tube Z and used for suppressing common-mode noise; specifically, one end of the voltage-stabilizing tube Z may be a negative electrode, and the other end of the voltage-stabilizing tube Z may be a positive electrode.

The first filtering circuit 2112 is connected to the voltage stabilizing common mode circuit 2111, and is configured to filter a signal output by the voltage stabilizing common mode circuit 2111 to obtain a second power supply signal; specifically, the first filter circuit 2112 includes: the circuit comprises first to third magnetic beads FB1 to FB3, an inductor L, a first capacitor C1, a second capacitor C2, a light emitting diode D and a first resistor R1.

One end of the first magnetic bead FB1 is connected with the third end of the common-mode inductor U1; one end of the second magnetic bead FB2 is connected with the fourth end of the common-mode inductor U1; one end of the inductor L is connected with the other end of the second magnetic bead FB 2; one end of the first capacitor C1 is connected with the other end of the inductor L, and the other end of the first capacitor C1 is grounded; one end of the third magnetic bead FB3 is connected with one end of the first capacitor C1; one end of the second capacitor C2 is connected with the other end of the third magnetic bead FB3, and the other end of the second capacitor C2 is grounded; one end of the light emitting diode D is connected to one end of the second capacitor C2; one end of the first resistor R1 is connected with the other end of the light-emitting diode D, and the other end of the first resistor R1 is grounded; specifically, one end of the light emitting diode D may be a positive electrode, the other end of the light emitting diode D may be a negative electrode, the first capacitor C1 includes three capacitors connected in parallel, and the capacitance values thereof are 22 μ F, 22 μ F and 100nF, respectively, and the second capacitor C2 includes three capacitors connected in parallel, and the capacitance values thereof are 22 μ F, 100nF and 1nF, respectively.

The second filter circuit 2121 includes: the fourth magnetic bead FB4 and the third capacitor C3, one end of the fourth magnetic bead FB4 is connected to the processing circuit 211, and specifically, one end of the fourth magnetic bead FB4 is connected to one end of the diode D and one end of the second capacitor C2; the voltage stabilizing circuit 2122 comprises a voltage stabilizing chip U2, the voltage stabilizing chip U2 comprises a signal input end VIN, a ground end GND, an enable end EN and a signal output end OUT, the ground end GND of the voltage stabilizing chip U2 is grounded, the input voltage of the voltage stabilizing chip U2 can be 2.2V-5.5V, and the output voltage of the voltage stabilizing chip U2 can be 1.2V; one end of the third capacitor C3 is connected to the other end of the fourth magnetic bead FB4, the signal input terminal VIN of the voltage stabilization chip U2, and the enable terminal EN of the voltage stabilization chip U2, and the other end of the third capacitor C3 is grounded; specifically, the third capacitor C3 includes three capacitors connected in parallel, with capacitance values of 100 μ F, 4.7 μ F, and 100nF, respectively.

The third filter circuit 2123 includes: one end of a fourth capacitor C4 is connected with the fifth magnetic bead FB5, one end of the fourth capacitor C4 is connected with the signal output end OUT of the voltage stabilizing chip U2, and the other end of the fourth capacitor C4 is grounded; one end of the fifth magnetic bead FB5 is coupled to one end of the fourth capacitor C4, and the other end of the fifth magnetic bead FB5 is connected to the power supply pin of the terahertz chip 30, so as to input a first power supply signal to the power supply pin of the terahertz chip 30; specifically, the fourth capacitor C4 includes three capacitors connected in parallel, with capacitance values of 100nF, 4.7 μ F, and 100 μ F, respectively.

The first power supply signal enters a signal input end VIN of a voltage stabilization chip U2 through a voltage stabilization common mode circuit 2111, a first filter circuit 2112 and a second filter circuit 2121, and after being processed by a voltage stabilization chip U2, the first power supply signal with a voltage value of 1.2V can be output, and the first power supply signal is input to a power supply pin of the terahertz chip 30, so that whether the power supply pin of the terahertz chip 30 is normal is tested.

The direct current bias circuit 22 is connected to the terahertz chip 30, and is configured to process the received second power signal to generate a bias signal, and input the bias signal to the terahertz chip 30; specifically, the dc bias circuit 22 includes: the second power supply circuit 221 and the bias circuit 222, wherein the second power supply circuit 221 is configured to receive a second power supply signal, process the second power supply signal, and obtain a third power supply signal; the bias circuit 222 is connected to the second power supply circuit 221, and is configured to receive a third power supply signal, process the third power supply signal to obtain a bias signal, and input the bias signal to the terahertz chip 30 to test the tuning performance of the terahertz chip 30, where the voltage of the bias signal may be 0.4V to 0.8V.

In a specific embodiment, as shown in fig. 8, the circuit structure of the second power supply circuit 221 is the same as that of the first power supply circuit 21, and is not repeated here.

The bias circuit 222 includes: one end of the sixth magnetic bead FB6 is connected to the second power supply circuit 221, and is configured to receive a third power supply signal; the first end of the potentiometer RW is connected to the other end of the sixth magnetic bead FB 6; one end of the second resistor R2 is connected with the second end of the potentiometer RW, and the other end of the second resistor R2 is grounded; one end of the third resistor R3 is connected with the third end of the potentiometer RW; one end of the fifth capacitor C5 is connected to the other end of the third resistor R3 and the tuning pin of the terahertz chip 30, and the other end of the fifth capacitor C5 is grounded.

Further, during the actual test, the third resistor R3 may not be connected to the second end of the potentiometer RW, and after the voltage value of the center tap of the potentiometer RW is measured to be within the safe voltage, the third resistor R3 may be connected to the second end of the potentiometer RW, so as to prevent the terahertz chip 30 from being damaged due to the excessive voltage value of the bias signal.

Because the terahertz chip 30 adopts a Complementary Metal Oxide Semiconductor (CMOS) process, and the gate input impedance of the CMOS is high, the terahertz chip can be adjusted by the potentiometer RW, which has a high resistance value, such as: 10⁵Ω, the potentiometer RW can provide a tuning voltage to the terahertz chip 30 through the third resistor R3 to test the performance of the terahertz chip 30.

The clock circuit 23 is connected to the terahertz chip 30, and is configured to input the received high-frequency clock signal to the terahertz chip 30; specifically, as shown in fig. 9, the clock circuit 23 includes a connector 231, a microstrip line 232, and a sixth capacitor C6, where the connector 231 is configured to receive a high-frequency clock signal, and input the high-frequency clock signal to a clock pin of the terahertz chip 30 through the microstrip line 232 and the sixth capacitor C6, so as to implement testing of the terahertz chip 30.

In a specific embodiment, the terahertz Chip 30 may be a System On Chip (SOC) wireless transceiver Chip, where the SOC wireless transceiver Chip includes a transmitting circuit and a receiving circuit, the transmitting circuit uses an input high-frequency clock signal as a reference, and the SOC wireless transceiver Chip adaptively synchronizes the frequency of the pseudo-random sequence generator to the input high-frequency clock signal to generate a baseband signal, and the baseband signal is modulated to a 250GHz radio frequency signal through an on-Chip radio frequency link and is transmitted through a transmitting antenna; the receiving circuit can amplify, filter and mix the received 250GHz radio frequency signal to a baseband signal through a receiving radio frequency link, complete demodulation and output the baseband signal to an output radio frequency port; the SOC wireless transceiver chip can be set to be in a receiving or sending state, and the SOC wireless transceiver chip can complete signal transceiving through the on-chip antenna.

Further, as shown in fig. 10, the transmitting circuit 31 includes a first frequency source 311, a first driving amplifier 312a, a first power amplifier 312b, an amplifier 312c, a quadrature coupler 313, a pseudo random sequence generator 314, first switches 315a to 315c, an inverter 316, a quadrupler 317, and a first antenna 318.

As shown in fig. 11, the receiving circuit 32 includes a second antenna 321, a second switch 322, a mixer 323, a frequency tripler 324, a second driver amplifier 325a, a second power amplifier 325b, an intermediate frequency amplifier 325c, a second frequency source 326, and a demodulator 327.

The high bandwidth brought by the pad structure on the PCB 10 can provide a high frequency clock signal to the transmitting circuit 31, and the receiving circuit 32 can demodulate the received signal to obtain a high frequency clock signal, and output the high frequency clock signal to the oscilloscope through the pad structure on the other side of the PCB 10 to display the demodulation result, thereby realizing the test of the SOC wireless transceiver chip.

The bandwidth of the PCB 10 adopted in this embodiment is relatively wide, which can meet the requirement of the high frequency clock signal for the transmission bandwidth; in addition, based on the design of the full PCB, the terahertz chip 30 can be tested in all functions by adopting a common processing technology for manufacturing and assembling and a common processing factory, a gold wire bonder and a set of test instruments; the traditional test scheme needs to additionally increase a probe station, the mode is low in timeliness, high in cost, slow in repeated measurement and inconvenient in external field application, and the scheme provided by the embodiment is obviously superior to the traditional test system in timeliness, cost, test convenience and external field application test.

The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.

Claims

1. A terahertz chip testing system is characterized by comprising: the terahertz chip is bound on the PCB and is connected with the test circuit; the test circuit is used for receiving a high-frequency signal through the signal bonding pad and inputting a test signal to the terahertz chip so as to test the terahertz chip;

the test circuit comprises a high-frequency signal pin, the signal bonding pad is connected with the high-frequency signal pin through a signal gold wire, the length of the signal gold wire is smaller than or equal to 0.5941mm, and the length of the signal gold wire is larger than or equal to 0.4242 mm.

2. The terahertz chip testing system of claim 1,

the terahertz chip further comprises two reference signal pins arranged on two sides of the high-frequency signal pin and two grounding bonding pads arranged on the PCB.

3. The terahertz chip testing system of claim 2,

the two grounding bonding pads are correspondingly connected with the two reference signal pins one by one through reference gold wires, and the two reference gold wires and the signal gold wires are not crossed with each other.

4. The terahertz chip testing system of claim 2,

the space between the high-frequency signal pin and the adjacent reference signal pin is less than or equal to 0.1200mm, and the space between the high-frequency signal pin and the adjacent reference signal pin is greater than or equal to 0.0889 mm; the distance between the ground pad and the signal pad is greater than or equal to 0.1300mm, and the distance between the ground pad and the signal pad is less than or equal to 0.1700 mm.

5. The system for testing the terahertz chip according to claim 1, wherein the high-frequency signal comprises a high-frequency clock signal, the system for testing the terahertz chip further comprises a first power supply pad and a second power supply pad, and the test circuit comprises:

the first power supply circuit is connected with the terahertz chip and used for receiving a first power supply signal through the first power supply bonding pad, processing the received first power supply signal to generate a first power supply signal, and inputting the first power supply signal to the terahertz chip;

the direct current bias circuit is connected with the terahertz chip and used for receiving a second power supply signal through the second power supply bonding pad, processing the received second power supply signal to generate a bias signal and inputting the bias signal to the terahertz chip;

and the clock circuit is connected with the terahertz chip and used for receiving the high-frequency clock signal through the signal bonding pad and inputting the received high-frequency clock signal to the terahertz chip.

6. The terahertz chip testing system of claim 5, wherein the first power supply circuit comprises:

the processing circuit is used for receiving the first power supply signal and processing the first power supply signal to obtain a second power supply signal;

and the filtering and voltage stabilizing circuit is connected with the processing circuit and used for receiving the second power supply signal, processing the second power supply signal to obtain the first power supply signal, and inputting the first power supply signal to a power pin of the terahertz chip.

7. The terahertz chip testing system of claim 6, wherein the processing circuit comprises:

the voltage stabilizing common mode circuit is used for receiving the first power supply signal, stabilizing the voltage of the first power supply signal and inhibiting common mode noise;

and the first filter circuit is connected with the voltage-stabilizing common-mode circuit and is used for filtering the signal output by the voltage-stabilizing common-mode circuit to obtain the second power supply signal.

8. The terahertz chip testing system of claim 6, wherein the filtering and voltage stabilizing circuit comprises:

the second filtering circuit is connected with the processing circuit and is used for filtering the second power supply signal;

the voltage stabilizing circuit is connected with the second filter circuit and is used for stabilizing the voltage of the signal output by the second filter circuit;

and the third filter circuit is connected with the voltage stabilizing circuit and is used for filtering the signal output by the voltage stabilizing circuit to obtain the first power supply signal.

9. The terahertz chip testing system of claim 5, wherein the direct current bias circuit comprises:

the second power supply circuit is used for receiving the second power supply signal and processing the second power supply signal to obtain a third power supply signal;

and the bias circuit is connected with the second power supply circuit and used for receiving the third power supply signal, processing the third power supply signal to obtain the bias signal, and inputting the bias signal to the terahertz chip.

10. The terahertz chip testing system of claim 5,

the high-frequency signal pin comprises a clock pin, the clock circuit comprises a connector, a microstrip line and a sixth capacitor, and the connector is used for receiving the high-frequency clock signal and inputting the high-frequency clock signal to the clock pin through the microstrip line and the sixth capacitor.