CN213693673U

CN213693673U - Clock distribution circuit

Info

Publication number: CN213693673U
Application number: CN202022407500.0U
Authority: CN
Inventors: 陈建平; 吴龟灵; 胡亮
Original assignee: Jiaxing Taichuan Photoelectric Co ltd
Current assignee: Jiaxing Taichuan Photoelectric Co ltd
Priority date: 2020-10-27
Filing date: 2020-10-27
Publication date: 2021-07-13
Anticipated expiration: 2030-10-27

Abstract

The utility model discloses a clock distribution circuit, include: the crystal oscillator is used for generating a standard frequency signal; a first clock buffer U1 including a first clock input signal port CLKIN, a first output enable control signal port OE, a first working voltage port VDD, a first ground port VSS, a first output clock signal port 1Y0, a second output clock signal port 1Y1, a third output clock signal port 1Y2 and a fourth output clock signal port 1Y 3; the first filter circuit comprises a first resistor R1, a first capacitor C1, a power supply voltage VCC and a ground terminal GND. The utility model discloses a clock distribution circuit simple structure, convenient to use through the cooperation setting between rubidium clock, filter circuit and the clock buffer, has realized dividing the standard frequency signal that rubidium clock produced into the multichannel and provides corresponding test equipment; the consistency of the multi-road frequencies is guaranteed, so that the consistency of the testing performance of corresponding testing equipment is guaranteed, the quantity of rubidium clocks required to be purchased is reduced, and the cost is saved.

Description

Clock distribution circuit

Technical Field

The utility model relates to an electronic measuring instrument field, concretely relates to clock distribution circuit.

Background

In a time measurement system, the standard frequency used by a measurement chip is of great importance, and the performance of the standard frequency directly influences the measurement precision. If the standard frequency performance is not good, the measurement precision of the tester is directly influenced, the standard frequency with good performance is expensive, for example, the price of a rubidium clock is ten thousand yuan, and the cost is unacceptable when multiple standard frequencies are needed at the same time.

2018.03.06 discloses a patent with publication number CN107769773A and name "a clock distribution circuit", which discloses a clock distribution circuit, including a constant temperature crystal oscillator generating a basic clock frequency, and a first amplifier, where the first amplifier outputs a signal to a power divider through a second filter circuit, the power divider divides the signal into four paths and outputs the four paths, and a fourth path of output signal is output through a third filter circuit; the fourth filtering and amplifying circuit outputs signals through a sixth filtering circuit; the clock distribution circuit provided by the invention applies the digital step attenuator and a specific signal processing flow, so that the circuit works more stably, and simultaneously outputs radio frequency signals within a target range.

In the current time measurement system, the following problems still exist:

1. if a component with poor standard frequency performance is selected, the measurement precision of the tester can be directly influenced, so that the measurement result is poor;

2. if the component with better standard frequency performance is selected, the price is very expensive and the universality is not good.

Based on the circumstances, the utility model provides a clock distribution circuit can effectively solve above problem.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a clock distribution circuit. The utility model discloses a clock distribution circuit simple structure, convenient to use through the cooperation setting between rubidium clock, filter circuit and the clock buffer, has realized dividing the standard frequency signal that rubidium clock produced into the multichannel and provides corresponding test equipment; the consistency of the multi-road frequencies is guaranteed, so that the consistency of the testing performance of corresponding testing equipment is guaranteed, the quantity of rubidium clocks required to be purchased is reduced, and the cost is saved.

The utility model discloses a following technical scheme realizes:

a clock distribution circuit comprising:

the crystal oscillator is used for generating a standard frequency signal;

the first clock buffer U1 is used for dividing one path of standard frequency signals into multiple paths of standard frequency signals, and includes a first clock input signal port CLKIN, a first output enable control signal port OE, a first working voltage port VDD, a first ground port VSS, a first output clock signal port 1Y0, a second output clock signal port 1Y1, a third output clock signal port 1Y2 and a fourth output clock signal port 1Y 3;

the first filter circuit comprises a first resistor R1, a first capacitor C1, a power supply voltage VCC and a ground terminal GND;

the first clock input signal port CLKIN is electrically connected to the crystal oscillator, one end of the first resistor R1 is electrically connected to the power supply voltage VCC, the other end is electrically connected to the first output enable control signal port OE, the first working voltage port VDD is electrically connected to the power supply voltage VCC, the first ground port VSS is electrically connected to the ground terminal GND, one end of the first capacitor C1 is electrically connected to the power supply voltage VCC, and the other end is electrically connected to the ground terminal GND.

Preferably, a second clock buffer U2 is included, wherein the second clock buffer U2 includes a second clock input signal port CLKIN, a second output enable control signal port OE, a second operating voltage port VDD, a second ground port VSS, a fifth output clock signal port 1Y0, a sixth output clock signal port 1Y1, a seventh output clock signal port 1Y2 and an eighth output clock signal port 1Y 3;

the second filter circuit comprises a second resistor R2 and a second capacitor C2;

the second clock input signal port CLKIN is electrically connected to the first output clock signal port 1Y0, one end of the second resistor R2 is electrically connected to the power supply voltage VCC, the other end is electrically connected to the second output enable control signal port OE, the second working voltage port VDD is electrically connected to the power supply voltage VCC, the second ground port VSS is electrically connected to the ground terminal GND, one end of the second capacitor C2 is electrically connected to the power supply voltage VCC, and the other end is electrically connected to the ground terminal GND.

Preferably, a third clock buffer U3 is included, the third clock buffer U3 includes a third clock input signal port CLKIN, a third output enable control signal port OE, a third operating voltage port VDD, a third ground port VSS, a ninth output clock signal port 1Y0, a tenth output clock signal port 1Y1, an eleventh output clock signal port 1Y2 and a twelfth output clock signal port 1Y 3;

a third filter circuit comprising a third resistor R3 and a third capacitor C3;

the third clock input signal port CLKIN is electrically connected to the second output clock signal port 1Y1, one end of the third resistor R3 is electrically connected to the power supply voltage VCC, the other end is electrically connected to the third output enable control signal port OE, the third working voltage port VDD is electrically connected to the power supply voltage VCC, the third ground port VSS is electrically connected to the ground terminal GND, one end of the third capacitor C3 is electrically connected to the power supply voltage VCC, and the other end is electrically connected to the ground terminal GND.

Preferably, a fourth clock buffer U4 is included, the fourth clock buffer U4 includes a fourth clock input signal port CLKIN, a fourth output enable control signal port OE, a fourth operating voltage port VDD, a fourth ground port VSS, a thirteenth output clock signal port 1Y0, a fourteenth output clock signal port 1Y1, a fifteenth output clock signal port 1Y2 and a sixteenth output clock signal port 1Y 3;

a fourth filter circuit comprising a fourth resistor R4 and a fourth capacitor C4;

the fourth clock input signal port CLKIN is electrically connected to the third output clock signal port 1Y2, one end of the fourth resistor R4 is electrically connected to the power supply voltage VCC, the other end is electrically connected to the fourth output enable control signal port OE, the fourth operating voltage port VDD is electrically connected to the power supply voltage VCC, the fourth ground port VSS is electrically connected to the ground terminal GND, one end of the fourth capacitor C4 is electrically connected to the power supply voltage VCC, and the other end is electrically connected to the ground terminal GND.

Preferably, the crystal oscillator is a rubidium clock.

Preferably, the power supply voltage VCC is 3.3V.

Preferably, the resistances of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are all 1000 Ω.

Preferably, the capacitance values of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are all 100 nF.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

the utility model discloses a clock distribution circuit simple structure, convenient to use through the cooperation setting between rubidium clock, filter circuit and the clock buffer, has realized dividing the standard frequency signal that rubidium clock produced into the multichannel and provides corresponding test equipment; the consistency of the multi-road frequencies is guaranteed, so that the consistency of the testing performance of corresponding testing equipment is guaranteed, the quantity of rubidium clocks required to be purchased is reduced, and the cost is saved.

1. The user can set the number of the multi-road pilot frequency to be divided according to the actual requirement without testing by a single group, the operation is convenient and simple, and the working efficiency is improved;

2. the clock signal is shunted without deteriorating the clock performance, and the driving capability of the lower circuit is ensured.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

Detailed Description

In order to make the technical solution of the present invention better understood by those skilled in the art, the following description of the preferred embodiments of the present invention is given with reference to the accompanying examples, but it should be understood that the drawings are for illustrative purposes only and are not to be construed as limiting the patent; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the present patent.

The utility model discloses in technical characteristics such as crystal oscillator, first clock buffer, second clock buffer, third clock buffer, fourth clock buffer and filter circuit (the utility model discloses a constitution unit/component), if do not have special explanation, all obtain from conventional commercial route, or make with conventional method, its concrete structure, theory of operation and the control mode that may involve, spatial arrangement mode adopt the conventional selection in this field can, should not be regarded as the innovation point of the utility model is located, to the technical staff in this field, can understand, the utility model discloses a do not do further specifically expand detailed description.

Example 1:

as shown in fig. 1, the present invention provides a clock distribution circuit, including:

the crystal oscillator is used for generating a standard frequency signal;

the first clock buffer U11 is configured to divide one standard frequency signal into multiple standard frequency signals, and includes a first clock input signal port CLKIN 11, a first output enable control signal port OE 12, a first working voltage port VDD 13, a first ground port VSS 14, a first output clock signal port 1Y015, a second output clock signal port 1Y 116, a third output clock signal port 1Y 217, and a fourth output clock signal port 1Y 318; the first output clock signal port 1Y015, the second output clock signal port 1Y 116, the third output clock signal port 1Y 217 and the fourth output clock signal port 1Y 318 are externally connected with different measuring devices.

A first filter circuit 2 including a first resistor R121, a first capacitor C122, a power supply voltage VCC 23, and a ground terminal GND 24; the filter circuit only allows the signal components in a certain frequency range to normally pass through, and prevents the other part of the frequency components from passing through.

The first clock input signal port CLKIN 11 is electrically connected to the crystal oscillator, one end of the first resistor R121 is electrically connected to the power supply voltage VCC 23, the other end of the first resistor R is electrically connected to the first output enable control signal port OE 12, the first working voltage port VDD 13 is electrically connected to the power supply voltage VCC 23, the first ground port VSS 14 is electrically connected to the ground terminal GND 24, one end of the first capacitor C122 is electrically connected to the power supply voltage VCC 23, and the other end of the first capacitor C122 is electrically connected to the ground terminal GND 24.

Example 2:

the crystal oscillator is used for generating a standard frequency signal;

Further, in another embodiment, a second clock buffer U23 is included, the second clock buffer U23 includes a second clock input signal port CLKIN 31, a second output enable control signal port OE 32, a second operating voltage port VDD 33, a second ground port VSS 34, a fifth output clock signal port 1Y 035, a sixth output clock signal port 1Y 136, a seventh output clock signal port 1Y 237, and an eighth output clock signal port 1Y 338;

a second filter circuit 4 including a second resistor R241 and a second capacitor C242;

the second clock input signal port CLKIN 31 is electrically connected to the first output clock signal port 1Y015, one end of the second resistor R241 is electrically connected to the power supply voltage VCC 23, the other end is electrically connected to the second output enable control signal port OE 32, the second working voltage port VDD 33 is electrically connected to the power supply voltage VCC 23, the second ground port VSS 34 is electrically connected to the ground terminal GND 24, one end of the second capacitor C242 is electrically connected to the power supply voltage VCC 23, and the other end is electrically connected to the ground terminal GND 24.

Because above structure, fifth output clock signal mouth 1Y 035, sixth output clock signal mouth 1Y 136, seventh output clock signal mouth 1Y 237 and eighth output clock signal mouth 1Y 338 all can external different measuring equipment, the utility model discloses the quantity that can external measuring equipment has become 7 from 4.

Further, in another embodiment, a third clock buffer U35 is included, the third clock buffer U35 includes a third clock input signal port CLKIN 51, a third output enable control signal port OE 52, a third operating voltage port VDD 53, a third ground port VSS 54, a ninth output clock signal port 1Y 055, a tenth output clock signal port 1Y 156, an eleventh output clock signal port 1Y 257, and a twelfth output clock signal port 1Y 358;

a third filter circuit 6 including a third resistor R361 and a third capacitor C362;

the third clock input signal port CLKIN 51 is electrically connected to the second output clock signal port 1Y 116, one end of the third resistor R361 is electrically connected to the power supply voltage VCC 23, the other end is electrically connected to the third output enable control signal port OE 52, the third working voltage port VDD 53 is electrically connected to the power supply voltage VCC 23, the third ground port VSS 54 is electrically connected to the ground terminal GND 24, one end of the third capacitor C362 is electrically connected to the power supply voltage VCC 23, and the other end is electrically connected to the ground terminal GND 24.

Because above structure, ninth output clock signal mouth 1Y 055, tenth output clock signal mouth 1Y 156, eleventh output clock signal mouth 1Y 257 and twelfth output clock signal mouth 1Y 358 all can external different measuring equipment, the utility model discloses the quantity that can external measuring equipment has become 10 from 7.

Further, in another embodiment, a fourth clock buffer U47 is included, the fourth clock buffer U47 including a fourth clock input signal port CLKIN 71, a fourth output enable control signal port OE 72, a fourth operating voltage port VDD 73, a fourth ground port VSS 74, a thirteenth output clock signal port 1Y 075, a fourteenth output clock signal port 1Y 176, a fifteenth output clock signal port 1Y 277, and a sixteenth output clock signal port 1Y 378;

a fourth filter circuit 8 including a fourth resistor R481 and a fourth capacitor C482;

the fourth clock input signal port CLKIN 71 is electrically connected to the third output clock signal port 1Y 217, one end of the fourth resistor R481 is electrically connected to the power supply voltage VCC 23, the other end is electrically connected to the fourth output enable control signal port OE 72, the fourth operating voltage port VDD 73 is electrically connected to the power supply voltage VCC 23, the fourth ground port VSS 74 is electrically connected to the ground terminal GND 24, one end of the fourth capacitor C482 is electrically connected to the power supply voltage VCC 23, and the other end is electrically connected to the ground terminal GND 24.

Owing to above structure, thirteenth output clock signal mouth 1Y 075, fourteenth output clock signal mouth 1Y 176, fifteenth output clock signal mouth 1Y 277 and sixteenth output clock signal mouth 1Y 378 all can external different measuring equipment, the utility model discloses the quantity that can external measuring equipment has become 13 from 10.

Further, in another embodiment, the crystal oscillator is a rubidium clock.

Further, in another embodiment, the power supply voltage VCC 23 is 3.3V.

Further, in another embodiment, the resistances of the first resistor R121, the second resistor R241, the third resistor R361, and the fourth resistor R481 are all 1000 Ω.

Further, in another embodiment, the capacitance values of the first capacitor C122, the second capacitor C242, the third capacitor C362 and the fourth capacitor C482 are all 100 nF.

The utility model discloses a theory of operation of an embodiment as follows:

a clock distribution circuit, the standard frequency signal of rubidium clock enters the first clock buffer U11 and is divided into 4-way quasi-frequency signal, and enters the second clock buffer U23, the third clock buffer U35, the fourth clock buffer U47 and the measuring device (if necessary, more clock buffers can be arranged), the second clock buffer U23, the third clock buffer U35, the fourth clock buffer U47 are divided into 12-way quasi-frequency signal respectively and can be connected with the measuring device.

According to the description and drawings of the present invention, it is easy for those skilled in the art to manufacture or use the clock distribution circuit of the present invention, and the positive effects described in the present invention can be produced.

Unless otherwise specified, in the present invention, if the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore, the terms describing orientation or positional relationship in the present invention are used for illustrative purposes only, and should not be construed as limiting the present patent, specific meanings of the above terms can be understood by those of ordinary skill in the art in light of the specific circumstances in conjunction with the accompanying drawings.

Unless expressly stated or limited otherwise, the terms "disposed," "connected," and "connected" are used broadly and encompass both fixed and removable connections, or integral connections; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The above is only the preferred embodiment of the present invention, not to the limitation of the present invention in any form, all the technical matters of the present invention all fall into the protection scope of the present invention to any simple modification and equivalent change of the above embodiments.

Claims

1. A clock distribution circuit, comprising:

the crystal oscillator is used for generating a standard frequency signal;

the first clock buffer U1(1) is used for dividing one path of standard frequency signal into multiple paths of standard frequency signals, and comprises a first clock input signal port CLKIN (11), a first output enable control signal port OE (12), a first working voltage port VDD (13), a first ground port VSS (14), a first output clock signal port 1Y0(15), a second output clock signal port 1Y1(16), a third output clock signal port 1Y2(17) and a fourth output clock signal port 1Y3 (18);

a first filter circuit (2) including a first resistor R1(21), a first capacitor C1(22), a power supply voltage VCC (23), and a ground GND (24);

the first clock input signal port CLKIN (11) is electrically connected to a crystal oscillator, one end of the first resistor R1(21) is electrically connected to a power supply voltage VCC (23), the other end is electrically connected to the first output enable control signal port OE (12), the first working voltage port VDD (13) is electrically connected to the power supply voltage VCC (23), the first ground port VSS (14) is electrically connected to a ground terminal GND (24), one end of the first capacitor C1(22) is electrically connected to the power supply voltage VCC (23), and the other end is electrically connected to the ground terminal GND (24).

2. The clock distribution circuit of claim 1, wherein: the circuit comprises a second clock buffer U2(3), wherein the second clock buffer U2(3) comprises a second clock input signal port CLKIN (31), a second output enable control signal port OE (32), a second working voltage port VDD (33), a second ground port VSS (34), a fifth output clock signal port 1Y0(35), a sixth output clock signal port 1Y1(36), a seventh output clock signal port 1Y2(37) and an eighth output clock signal port 1Y3 (38);

a second filter circuit (4) including a second resistor R2(41) and a second capacitor C2 (42);

the second clock input signal port CLKIN (31) is electrically connected to the first output clock signal port 1Y0(15), one end of the second resistor R2(41) is electrically connected to the power supply voltage VCC (23), the other end is electrically connected to the second output enable control signal port OE (32), the second working voltage port VDD (33) is electrically connected to the power supply voltage VCC (23), the second ground port VSS (34) is electrically connected to the ground terminal GND (24), one end of the second capacitor C2(42) is electrically connected to the power supply voltage VCC (23), and the other end is electrically connected to the ground terminal GND (24).

3. The clock distribution circuit of claim 2, wherein: the circuit comprises a third clock buffer U3(5), wherein the third clock buffer U3(5) comprises a third clock input signal port CLKIN (51), a third output enable control signal port OE (52), a third working voltage port VDD (53), a third ground port VSS (54), a ninth output clock signal port 1Y0(55), a tenth output clock signal port 1Y1(56), an eleventh output clock signal port 1Y2(57) and a twelfth output clock signal port 1Y3 (58);

a third filter circuit (6) including a third resistor R3(61) and a third capacitor C3 (62);

the third clock input signal port CLKIN (51) is electrically connected to the second output clock signal port 1Y1(16), one end of the third resistor R3(61) is electrically connected to the power supply voltage VCC (23), the other end is electrically connected to the third output enable control signal port OE (52), the third working voltage port VDD (53) is electrically connected to the power supply voltage VCC (23), the third ground port VSS (54) is electrically connected to the ground terminal GND (24), one end of the third capacitor C3(62) is electrically connected to the power supply voltage VCC (23), and the other end is electrically connected to the ground terminal GND (24).

4. The clock distribution circuit of claim 3, wherein: the circuit comprises a fourth clock buffer U4(7), wherein the fourth clock buffer U4(7) comprises a fourth clock input signal port CLKIN (71), a fourth output enable control signal port OE (72), a fourth working voltage port VDD (73), a fourth ground port VSS (74), a thirteenth output clock signal port 1Y0(75), a fourteenth output clock signal port 1Y1(76), a fifteenth output clock signal port 1Y2(77) and a sixteenth output clock signal port 1Y3 (78);

a fourth filter circuit (8) including a fourth resistor R4(81) and a fourth capacitor C4 (82);

the fourth clock input signal port CLKIN (71) is electrically connected to the third output clock signal port 1Y2(17), one end of the fourth resistor R4(81) is electrically connected to the power supply voltage VCC (23), the other end is electrically connected to the fourth output enable control signal port OE (72), the fourth operating voltage port VDD (73) is electrically connected to the power supply voltage VCC (23), the fourth ground port VSS (74) is electrically connected to the ground terminal GND (24), one end of the fourth capacitor C4(82) is electrically connected to the power supply voltage VCC (23), and the other end is electrically connected to the ground terminal GND (24).

5. The clock distribution circuit of claim 1, wherein: the crystal oscillator is a rubidium clock.

6. The clock distribution circuit of claim 1, wherein: the power supply voltage VCC (23) is 3.3V.

7. The clock distribution circuit of claim 4, wherein: the resistance values of the first resistor R1(21), the second resistor R2(41), the third resistor R3(61) and the fourth resistor R4(81) are all 1000 omega.

8. The clock distribution circuit of claim 4, wherein: the capacitance values of the first capacitor C1(22), the second capacitor C2(42), the third capacitor C3(62) and the fourth capacitor C4(82) are all 100 nF.