JP3198748B2 - Capacitance detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance detecting circuit for detecting the magnitude of a predetermined action by utilizing the fact that the capacitance changes in response to a predetermined external action.

[0002]

2. Description of the Related Art A conventional capacitance detection circuit is provided with a detection unit whose capacitance changes in accordance with a predetermined action such as pressure, acceleration, displacement, etc., which is received from the outside. The magnitude of the action was detected by measuring the absolute value. Particularly, in recent years, when controlling the system based on the detected values, a microcomputer is often used. In most cases, the detected value is simply displayed as a digital value.

Therefore, an analog signal obtained by measuring the capacitance is amplified, converted into a digital signal by an A / D converter, and supplied to a microcomputer to control the system and perform digital display.

[0004]

However, the above-mentioned conventional capacitance detecting circuit converts an analog signal into a digital signal, so that a conversion bit error occurs.
In order to reduce the bit error, a large number of bits, that is, an expensive A / D converter was required. Further, a high-precision amplifier for amplifying an analog signal is required, and its temperature must be compensated.

[0005] Further, in order to measure the absolute value of the capacitance, the relationship between the magnitude of the external action and the capacitance becomes inconsistent, for example, when the dielectric constant changes due to the environment around the detection unit, and the measurement error occurs. Was a factor.

SUMMARY OF THE INVENTION An object of the present invention is to solve such conventional problems, and it is possible to detect an accurate capacitance with a very simple and inexpensive structure, to eliminate the need for temperature compensation and to use a detection unit. Even if the dielectric constant changes due to the surrounding environment,
An object of the present invention is to provide an excellent capacitance detection circuit capable of performing detection with a small error.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a detecting unit whose capacitance changes in response to a predetermined external operation, and a detecting unit whose capacitance changes in accordance with the predetermined operation. A reference unit, a first oscillation circuit that generates a detection frequency signal in accordance with the capacitance of the detection unit, and a second oscillation circuit that generates a reference frequency signal in accordance with the capacitance of the reference unit. , a structure in which and a measurement unit for generating a measurement signal by measuring the number of periods of the detection frequency signal within a predetermined period of the reference frequency signal, the first and second origination
Circuit is determined according to the capacitance and resistance, respectively.
Oscillating section that generates an oscillating signal with
Residual in the capacitor related to the capacitance according to the signal
It is characterized in Rukoto that having a circuitry for equalizing the charge amount. In addition, the present invention provides an electrostatic
A detecting section whose capacity changes; and a static section depending on the predetermined action.
The capacitance of the reference unit where the capacitance does not change and the capacitance of the detection unit
A first oscillation circuit for generating a detection frequency signal in response to the
Generating a reference frequency signal according to the capacitance of the reference section
The second oscillation circuit and the cycle of the reference frequency signal are highly accurate.
Measurement based on the timer of
And the detection frequency signal within the predetermined period is determined.
Computing means for measuring the number of signal periods, and
I have.

[0008]

According to the present invention, since the capacitance obtained from the detection unit is directly converted into a digital signal by the above configuration, it is not necessary to use an amplifier or an A / D converter. Accurate capacitance can be detected,
There is no need for temperature compensation.

Further, by measuring the relative value between the capacitance of the detection unit and the capacitance of the reference unit, detection with little error is performed even when the dielectric constant changes due to the environment around the detection unit. be able to.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the capacitance detection circuit according to the present invention. In FIG. 1, reference numeral 1 denotes a detection unit, which is not shown in the figure, and includes two fixed electrodes and a movable electrode provided between the two fixed electrodes. This movable electrode is provided with a hole in a part of one fixed electrode, and is directly connected to a plunger passed through the hole. Further, the plunger is connected to a pressure receiving portion which is displaced in response to an external action such as pressure of liquid or gas such as oil pressure or gas pressure or acceleration. Alternatively, the plunger itself is configured to be displaced in accordance with the displacement of an external object. That is, the movable electrode is biased toward one of the fixed electrodes in response to an external action, and divides the two fixed electrodes into two when no external action is applied (hereinafter referred to as a “normal state”). It is located exactly in the middle. Therefore, in a normal state, the capacitance C1 of the capacitor 1a formed by one fixed electrode and the movable electrode
Has a value equal to the capacitance C2 of the capacitor 1b formed by the other fixed electrode and the movable electrode.

In a state where the movable electrode is deflected in response to an external action (hereinafter referred to as a "deflected state"), the capacitances C1 and C2 have different values. In the case of the present embodiment, the configuration is such that the capacitance C1 becomes smaller than the capacitance C2 when subjected to an external action.
Therefore, by measuring the difference between the two capacitances, the magnitude of the external action can be detected. In addition,
The movable electrode is connected to the ground, and the two fixed electrodes are connected to a circuit section described later.

Reference numeral 2 denotes a reference unit (reference unit) provided in proximity to the detection unit 1, that is, in the same environment.
It is composed of two fixed electrodes (not shown). Therefore, the value of the capacitance Cr of the capacitor 2a formed by these two fixed electrodes does not change due to an external action. In this embodiment, the capacitance Cr has the same value as the capacitances C1 and C2 of the detection unit 1 in the normal state. One of the fixed electrodes of the reference portion 2 is connected to the ground, and the other fixed electrode is connected to the circuit portion.

The capacitors 1a of the detection unit 1 and the reference unit 2,
When the dielectric constant of 1b and 2a changes depending on the surrounding environment, the respective capacitances C1, C2 and Cr also change.

Reference numeral 3 denotes a circuit section composed of a gate array, the internal configuration of which is as follows. Reference numeral 31 denotes a CR oscillation circuit connected to the capacitor 1a of the detection unit 1, and sends out a clock signal CK1 of a pulse signal having a frequency determined by the capacitance C1 and a resistance (not shown). 3
Reference numeral 2 denotes a CR oscillation circuit connected to the capacitor 1b of the detection unit 1, and a square wave clock signal CK2 having a frequency determined by a capacitance (not shown) having the same resistance as the capacitance C2 and the resistance of the CR oscillation circuit 31. Is sent. 33 is the reference part 2
Is a CR oscillation circuit connected to the capacitor 2a, and sends out a square wave clock signal CK3 having a frequency determined by the capacitance Cr and a resistance (not shown).

Reference numeral 34 denotes a frequency dividing circuit for dividing the frequency of the clock signal CK3 sent from the CR oscillation circuit 33 to generate a plurality of frequency dividing signals having different frequency dividing ratios. A timing generator 35 generates a plurality of timing signals by supplying the plurality of frequency-divided signals. The timing signals include enable signals CK1EN and CK2EN for controlling the oscillation of CR oscillation circuits 31 and 32, and select signal S1.
And S2, and an up-down signal UD and others.

Reference numeral 36 denotes a selector circuit for selecting and outputting one of the clock signals CK1, CK2, or CK3 from each of the CR oscillation circuits 31, 32, or 33 according to the select signals S1 and S2. For example, when the select signals S1 and S2 are "0, 1", the clock signal C
K1 is selected, and when "1, 0", the clock signal CK2
When "1, 1", the clock signal CK3 is selected. When "0, 0", no oscillation signal is selected, and its output is connected to the ground by a pull-down resistor or the like, and the low level is selected. Has become.

37 is based on the up / down signal UD,
This is an up / down counter that counts a pulse signal (hereinafter, referred to as “clock signal CKIN”) obtained from the selector circuit 36. This up-down counter 3
7 counts up the clock signal CKIN when the up / down signal UD is at a low level, and counts down the clock signal CKIN when the up / down signal UD is at a high level. When the count value becomes "0" after the down-counting, a low-level borrow signal BO is output and supplied to the timing generator 35, and a signal obtained by latching this borrow signal BO (hereinafter, the description will be simplified). Therefore, this signal is also referred to as a “borrow signal BO”) to the CR oscillation circuit 33 as an enable signal CK3EN for controlling oscillation.

A gate circuit 38 outputs a clock signal CKIN input to the up / down counter 37 when the enable signal OEN from the timing generator 35 becomes active. An output terminal 39 is a clock signal CKIN obtained from the gate circuit 38.
At the next stage as an output pulse signal Pout (not shown)
To supply.

Note that a flip-flop or the like (not shown) constituting the frequency dividing circuit 34 and the up / down counter 37 is provided.
Are initialized by a power-on reset signal XRST described later. Therefore, in this initial state, the count value of the up / down counter 37 is of course "0".

Next, an outline of the operation of the configuration of FIG. 1 will be described with reference to FIG. FIG. 2A is a timing chart when the power supply VDD supplied to the circuit unit 3 is supplied,
FIG. 2B is a timing chart showing the counting operation of the up / down counter 37. In this case, the external action is hydraulic pressure.

Now, when the detecting section 1 is in the bias state, the capacitance C1 becomes smaller than the capacitance C2 as described above, so that the frequency of the clock signal CK1 from the CR oscillation circuit 31 becomes CR The frequency becomes higher than the frequency of the clock signal CK2 from the oscillation circuit 32. Therefore, as shown in FIG. 2A, the count value N1 obtained by up-counting the pulse signal of the clock signal CK1 for a certain period of time (which will be described later) reduces the pulse signal of the clock signal CK2 by the same predetermined period. It becomes larger than the counted value N2. That is, the remaining value Nd of the up-down counter 37 after the down-count is Nd
= N1−N2, and the pulse signal of the clock signal CK3 is counted down until the borrow signal BO becomes low level, so that Nd output pulse signals can be transmitted from the output terminal as the magnitude of the hydraulic pressure. it can.

As shown in FIG. 2A, the period in which the counting operation is performed is an oscillation mode in which one of the CR oscillation circuits is oscillating, and the period in which the counting operation is not performed is in the oscillation stop mode ( (Hereinafter referred to as “sleep mode”)
It is. Furthermore, even in the oscillation mode, the CR oscillation circuit 3
Among the CR oscillation circuits other than 3, those that do not contribute to the counting operation are in the oscillation stop state, thereby saving power consumption.

That is, the CR oscillating circuit 31 and the CR oscillating circuit 32 constitute means as a first oscillating circuit for generating a detection frequency signal (clock signals CK1, CK2) in accordance with the capacitance of the detection unit 1. , CR oscillating circuit 33 constitutes a second oscillating circuit for generating a reference frequency signal (clock signal CK3) according to the capacitance of reference unit 2. Further, a measuring unit that generates the measurement signal by measuring the number of periods of the detected frequency signal within a predetermined period of the reference frequency signal by the frequency dividing circuit 34, the timing generator 35, the selector circuit 36, and the up / down counter 37 is configured. I do.

Next, a detailed operation of the configuration of FIG. 1 will be described with reference to FIG. FIG. 3 is a diagram showing a timing chart of signal waveforms inside the circuit section 3, and each signal waveform is represented by the same reference numeral as a signal in the circuit 3.

In FIG. 3, a power-on reset signal X
When RST (FIG. 3A) goes high, the borrow signal BO goes high, so that the CR oscillation circuit 33 starts oscillating, and the clock signal CK3 is supplied to the frequency dividing circuit 34. By the frequency-divided signal generated by the frequency-divider circuit 34, the enable signal CK1EN which has become high level at the falling edge of the second pulse signal of the clock signal CK3 shown in FIG.
It is supplied to the R oscillation circuit 31. At the same time, the up / down signal UD goes low, and the up / down counter 37
Becomes a state where up-counting is possible.

At the falling edge of the fourth pulse signal of the clock signal CK3, the select signals S1 and S2 supplied to the select circuit 36 become "0, 1", and the clock signal CK1 becomes the clock signal CKIN as an up / down counter. 37 and the up-counting is started. Thereafter, at the falling edge of the 511th pulse signal of the clock signal CK3, the enable signal CK1EN becomes low level, and the oscillation of the CR oscillation circuit 31 stops. That is, the clock signal CK1 is counted up during the period when 508 pulses of the clock signal CK3 are input. In this case, the count value of the up-down counter 37 when the up-count is completed is N1. Further, the up-down signal UD becomes high level simultaneously with the stop of the oscillation, and the up-down counter 37 enters a down-countable state.

After that, the enable signal CK2EN which has become high level at the falling edge of the 513th pulse signal of the clock signal CK3 is supplied from the timing generator 35 to the CR oscillation circuit 32. Then, at the falling edge of the 515th pulse signal of the clock signal CK3, the select signals S1 and S2 supplied to the select circuit 36 become “1, 0”, and the clock signal CK2 is supplied to the up / down counter 37 as the clock signal CKIN. Then, the down count is started. Then, at the fall of the 1022 pulse signal of the clock signal CK3,
The enable signal CK2EN becomes low level, and the oscillation of the CR oscillation circuit 32 stops. Therefore, the clock signal CK
The clock signal CK2 is counted down while 508 pulses of 3 are input as in the case of counting up. That is, the up-down counter 37
Is decremented every down count. In this case, the total number counted down when the down count ends is N2. Therefore, the count value Nd remaining in the up-down counter 37 is Nd
= N1-N2.

Thereafter, at the falling edge of the 1024th pulse signal of the clock signal CK3, the select signals S1 and S2 supplied to the select circuit 36 become "1, 1".
The clock signal CK3 is supplied to the up-down counter 37 as the clock signal CKIN, and the down-counting is started. When the select signals S1 and S2 are "1,1"
At the same time, the enable signal OEN supplied from the timing generator 35 to the gate circuit 38 becomes active, and the clock signal CK3 becomes the output pulse signal Pou.
It is transmitted from the output terminal 39 as t.

The down count of the clock signal CK3 is
The count value Nd remaining in the up / down counter 37
Until it becomes "0". This is because when the count value of the up / down counter 37 becomes "0", the borrow signal BO becomes low level, and the oscillation of the CR oscillation circuit 33 stops.

Therefore, since the count value Nd is generated by the difference between the capacitances C1 and C2 of the detection unit 1, that is, the magnitude of the oil pressure, by supplying Nd output pulse signals to a microcomputer (not shown) or the like. Therefore, the magnitude of the hydraulic pressure can be detected.

In this embodiment, the detecting unit 1 and the reference unit 2
Are provided in the same environment. Therefore, even when the dielectric constant of the capacitors 1a and 1b of the detection unit 1 changes due to a change in this environment, for example, a change in the chemical composition of the hydraulic oil to be detected. , It is possible to minimize the detection error.

Now, it is assumed that the capacitances C1 and C2 of the capacitors 1a and 1b of the detection unit 1 increase by 30% with the change in the dielectric constant. In this case, since the frequency of the pulse signals of the clock signals CK1 and CK2 decreases, the number of pulses counted by the up / down counter 37 within a predetermined time decreases by 30%. However, in this case, the capacitance Cr of the capacitor 2a of the reference unit 2 also increases by 30%, and the frequency of the pulse signal of the clock signal CK3 decreases, so that 508 pulse signals of the clock signal CK3 are input. The period for which the detection is performed becomes longer by 30%, and the detection error accompanying the change in the dielectric constant can be canceled.

Further, since the change in the capacitance is directly converted into a pulse signal (digital signal) without being converted into an analog signal, an amplifier for amplifying the analog signal and an A / D for converting the analog signal into a digital signal. There is no need to use a converter. Therefore, the circuit configuration is simplified, and it can be realized at low cost. In addition, it is possible to avoid the occurrence of a detection error due to the influence of temperature drift, humidity drift, power supply voltage fluctuation, and the like.

Further, by configuring the circuit section 3 with an IC of a gate array, the circuit section 3 can be realized in a small area of silicon which is a material of the IC.
The threshold levels of the gates forming the oscillation circuits of the R oscillation circuits 31, 32 and 33 can be made uniform, and the oscillation conditions such as the oscillation frequency can be made the same.

Further, by providing a means for adjusting the oscillation frequency, the detection accuracy can be extremely increased.
FIG. 4 shows a circuit configuration provided with a means for adjusting the oscillation frequency. In FIG. 4, resistors R1 and R4, resistors R2 and R5
And a semi-fixed variable resistor (hereinafter referred to as "trimmer") TM1 and resistors R3, R6 and trimmer TM1 are constants that determine the oscillation frequency in cooperation with capacitors 1a and 1b of detection unit 1 and capacitor 2a of reference unit 2, respectively. It is.
When the gate array 3 is set to the test mode, for example, by providing a reset signal to the power-on reset terminal 40, the clock signals CK1, CK2, and CK3 are transmitted from the output terminal 39 individually or switched at regular intervals. Therefore, the trimmers TM1 and TM2 can be adjusted manually or automatically by the adjusting means so that the frequency of the output clock signals CK2 and CK3 becomes the same as the frequency of the clock signal CK1.

FIG. 5 shows the CR oscillation circuits 31, 3 in FIG.
2 and 33, and specific circuits of the detection unit 1 and the reference unit 2, which are applied to a capacitance detection circuit formed as a CMOS gate array.

Referring to FIG. 5, first, components external to the gate array will be described. C1 and C2 are variable capacitors, and Cr is a fixed capacitor, and constitutes a detecting unit for detecting an external pressure. The capacitors C1 and C2 are composed of two fixed electrodes and a movable electrode provided between the two fixed electrodes.

On the other hand, the capacitor Cr is a reference part (reference part) and is composed of two fixed electrodes. Therefore, the capacitor Cr formed by these two fixed electrodes
Does not change due to an external action. When the dielectric constant and the like of the capacitors C1, C2, and Cr change depending on the surrounding environment, the respective capacitances also change.

R1, R2 and R3 are external fixed resistors, and together with the capacitors C1, C2 and Cr, respectively, determine a time constant for determining the oscillation frequency. The fixed electrodes forming the capacitors C1 and C2 are connected to the terminals of the gate array by lead wires or the like, and the movable electrode is connected to one end of the resistors R1 and R2 to the terminal of the gate array as the common side of the detection unit. I have. The two fixed electrodes of the reference capacitor Cr are connected to the terminals of the gate array, respectively, and one end of the resistor R3 is independently connected to the terminal of the gate array, and the other is connected to one fixed electrode of the capacitor Cr. ing.

Next, the internal circuit of the gate array will be described. In FIG. 5, 4a to 4d are inverter circuits, 6a to 6h are 2-input NAND circuits, 7a and 7
b is a two-input NOR circuit, and 8a to 8g are clocked gate circuits. In this case, it is desirable that the transistor capacity and the configuration of each gate be the same.

FIG. 6 is a diagram showing a clocked gate circuit composed of a CMOS semiconductor device. FIG. 6A shows an internal circuit thereof, and FIG. 6B shows an equivalent circuit thereof. FIG.
In (a), when the clock signal φ is at a high level, an inverter operation is performed, and the output signal Y is the input signal A.
Is the inverted signal of. On the other hand, when the clock signal φ is at the low level, the output becomes high impedance, and the input and output are cut off. In FIG. 6A, an inverter 81 for inverting a clock signal φ has two CMOSs.
It is formed of a transistor. Therefore, the clocked gate circuit can be formed by six CMOS transistors, and has a very simple configuration. Therefore, the gate array can be easily formed at a low cost. In addition, the variation in manufacturing is smaller than that of the analog switch, and the mass productivity is good. Further, the state is quickly inverted between the inverter state and the high impedance state, and driving can be performed with a high-speed clock signal φ.

The NAND circuits 6a and 6b, the clocked gate circuits 8a and 8b, and the inverter circuit 4a constitute a first oscillating unit, and generate an oscillating signal of a frequency f1 according to a time constant determined by the capacitor C1 and the resistor R1. I do. Similarly, the NAND circuits 6a and 6c, the clocked gate circuits 8c and 8d, and the inverter circuit 4b constitute a second oscillating unit, and generate an oscillating signal of a frequency f2 according to a time constant determined by the capacitor C2 and the resistor R2. I do. Also, NAN
D circuits 6d and 6e, clocked gate circuits 8e and 8g
And 8f, the inverter circuit 4c constitutes a third oscillation unit,
A reference oscillation signal having a fixed frequency f3 is generated according to a time constant determined by the capacitor Cr and the resistor R3.

Since the clock signal input terminals of the clocked gate circuits 6e, 6f and 6g of the third oscillating section are pulled up to the power supply, they always constitute an inverter circuit. Nevertheless, the clocked gate circuit is used because the load capacity of the NAND circuit 6d is made equal to the load capacity of the NAND circuit 6a in the first and second oscillating sections, and the characteristics of the respective oscillating sections are identical. This is for the purpose of conversion.
Further, the first and second oscillating sections share the first stage NAND circuit 6a for the same reason.

Further, by sharing the first stage NAND gates of the first and second oscillating units, the input parasitic capacitance of each oscillating circuit can be made the same, and the effect of reducing oscillation errors can be obtained. is there.

On the other hand, NAND circuits 6f, 6g and 6h,
The gate circuits of the inverter circuit 4d and the NOR circuits 7a and 7b are provided with pulse signals E0 and E which are control signals from a timing generator (not shown) in the gate array.
1, E2 and E3 are received by the control terminal of this oscillation circuit,
The pulse signals E4 to E8 that determine conditions such as the oscillating operation of the first, second, and third oscillating units are generated. The signal serving as a reference for these pulse signals is a reference oscillation signal of frequency f3 generated from the third oscillation unit.

Next, the operation of the oscillation circuit of FIG. 5 will be described. FIG. 7 is a timing chart of the pulse signals E0 to E8. Table 1 shows the oscillating state of the pulse signals E0, E1, E2, and E3 input to the control terminal of the oscillation circuit.

[0048]

[Table 1] When the pulse signal E0 is L (low level), the NAND
The circuit 6a and the NAND circuit 6d become non-active, and all oscillations stop regardless of the state of other pulse signals. (Period of T6 in FIG. 7)

When the pulse signal E0 is at H (high level), the NAND circuit 6d is active, so that the third oscillating unit is in an oscillating state, and a reference oscillation signal having a frequency f3 is generated. (Period of T1 to T5 in FIG. 7)

When the pulse signal E0 is H, and the pulse signal E1 is H, E2 is L, and E3 is H, the pulse signals E5 and E7 which are the clock signals φ of the clocked gate circuits 8a and 8b. Are both H. That is, during the period T2 in FIG. 7, the first oscillation unit is in the oscillation state. During this period, the clocked gate circuits 8c and 8d are cut off because the pulse signals E6 and E8, which are the clock signal φ, are both at L level, and the second oscillation unit is in the oscillation stop state.

When the pulse signal E0 is H, the pulse signal E1 is H, E2 is H, and E3 is L, the pulse signal E6 which is the clock signal φ of the clocked gate circuits 8c and 8d. And E8 both become H. That is, during the period T4 in FIG. 7, the second oscillation unit is in the oscillation state. During this period, the clocked gate circuits 8a and 8b output the pulse signals E5 and E7 as the clock signal φ.
Are both L, so that the first oscillating unit is in the oscillation stopped state.

When the pulse signal E0 is H and the pulse signal E1 is L, the clocked gate circuit 8a
And 8c become active because both E5 and E6, which are the clock signals φ, become H level. In addition, the clocked gate circuits 8b and 8d output the clock signals φ, E7 and E, respectively.
8 are both L, so that the state is cut off. Under such conditions, that is, during the periods T1, T3 and T5 in FIG. 7, the common terminal connecting the capacitors C1 and C2 is open because the clocked gate circuits 8b and 8d are in the cut-off state. . The capacitors C1 and C
The other terminals of 2 have the same potential. Therefore, when the oscillation state is switched from one oscillation section to the other oscillation section, the period of T1, T3 or T5 in FIG. 7 is provided to equalize the amount of electric charge remaining in the capacitors C1 and C2, thereby achieving oscillation. It is possible to eliminate variations in the operation start time.

Although not shown in FIG. 7, in FIG. 5, when the pulse signals E0, E1, E2 and E3 are H,
Although the pulse signal E4 becomes H and the NAND circuit 6a connected thereto is active, the clocked gate circuits 8a, 8b, 8c and 8d are turned off, and the other input of the NAND circuit 6a is opened. Care must be taken to avoid this situation.

FIG. 8 is a circuit diagram of a CR oscillation circuit of another embodiment different from the CR oscillation circuit of FIG. The feature of the circuit of FIG. 8 is that the external resistors R1 and R2 that determine the oscillation frequency are connected to the first oscillation unit and the second oscillation unit in the oscillation circuit shown in FIG. The point is that the resistor is used in common. With this configuration, it is possible to further reduce the error in the oscillation frequency of the first oscillation unit and the second oscillation unit due to the variation in the two resistances.

The remaining configuration, the timing chart of FIG. 7, and Table 1 are the same as those of the embodiment of the oscillation circuit shown in FIG. 5, and the description thereof will be omitted. As described above, the 2 including the clocked gate circuit which is brought into the inverter or high impedance output state by the clock signal.
Since each oscillating unit is provided with two oscillating units and generates an oscillating signal of a frequency determined according to the capacitance and resistance value, each oscillating unit stops or starts the oscillating operation according to the clock signal given to each. In addition, it is possible to realize an inexpensive oscillation circuit which does not require a high-precision power supply, has little variation with respect to changes in the external environment, and has a small variation.

Further, an oscillating section for generating an oscillation signal having a frequency determined according to the capacitance and the resistance value, and a circuit for equalizing the charge of the capacitor related to the capacitance according to the clock signal are provided. With this configuration, the amount of charge remaining in the capacitor can be made uniform before starting the oscillating operation. Therefore, when switching from one oscillating unit to the other oscillating unit, the oscillating operation is quickly stabilized, and Capacitance detection can be performed at high speed.

In the oscillation circuits shown in FIGS. 5 and 8, two oscillators (excluding the third oscillation unit, which is a reference oscillation unit) applied to the capacitance detection circuit have been described. Without limitation, when detecting pressure or the like at two or more n points, n oscillating units are provided, and when detecting the pressure and the like at each point sequentially, the oscillating unit and the reference Only the oscillating unit is oscillated while switching at high speed. Therefore, the configuration of the present invention using the clocked gate circuit to apply to such an electrostatic capacitance detection circuit exhibits an excellent effect.

When the oscillation circuit is constituted by ordinary MSI, or when there is a margin in the current consumption of the gate array, a similar oscillation circuit can be constituted without using a clocked gate circuit.

FIG. 9 shows an alternative to the clocked gate circuit.
C using a tri-state buffer that is an I / O cell
FIG. 3 is a circuit diagram of an R oscillation circuit. With such a configuration, although current consumption is increased as compared with the case of a clocked gate circuit, a gate array can be easily formed, so that an inexpensive oscillation circuit can be realized. In FIG. 9, reference numeral 1 denotes a detection unit as in the conventional example. The other configuration, the timing chart of FIG. 7, and Table 1 are the same as the configuration of the oscillation circuit shown in FIG. 5, and the description thereof will be omitted.

FIG. 10 is a block diagram showing the configuration of the second embodiment of the present invention. 10, the same components as those of the previous embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The feature of this embodiment is that the pulse output of the circuit section 3 is made parallel. 5, reference numeral 41 denotes an output latch circuit, which is pulse signal data Q1, Q2,..., Qn sequentially output from the up / down counter 37.
Is latched and sent out as n-bit parallel data. Reference numeral 42 denotes a parallel output terminal for supplying the parallel data to a next stage (not shown). Reference numeral 43 denotes a terminal for sending a borrow signal as a measurement end signal at the end of measurement.

According to this embodiment, measured data can be transmitted at a high speed, and can be directly connected to a data bus having a plurality of bits of a microcomputer.

FIG. 11 is a block diagram showing the configuration of the third embodiment of the present invention. 11, the same components as those of the previous embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The feature of this embodiment is that the detection unit 11 is constituted by a single capacitor 11a. That is,
Although not shown in the figure, the detection unit 11 is formed of one fixed electrode and a movable electrode directly connected to the plunger, and the movable electrode is biased toward the fixed electrode in accordance with the oil pressure, and the capacitance C1 is changed.
Changes (increases).

Accordingly, also in the internal configuration of the circuit section 13, the CR oscillation circuit connected to the detection section 11 is a single oscillation circuit (CR oscillation circuit 31) and the select circuit 136
Is also a circuit for selecting two inputs. Further, a counter as a means for measuring the frequency is constituted by a down counter 137. Further, in the down counter 137, a predetermined preset value Np is set by a power-on reset.
The frequency divider 134 and the timing generator 135 are also slightly different from the configuration of FIG. 1, but this point will be described in the following description of the operation.

In the configuration shown in FIG. 11, when hydraulic pressure is applied to the detecting section 11 as an external action, the capacitance C1 of the capacitor 11a increases. In this case, the clock signal CK
Between a predetermined number of pulse signals of 3 (255 in this case),
The number of pulse signals of the clock signal CK1 supplied from the select circuit 136 to the down counter 137 and counted down is defined as N1. Therefore, the remaining count value of the down counter 137 after the completion of the down count is:
Np-N1. When the down-counting is completed, the CR oscillation circuit 31 is enabled by the enable signal CK1EN.
Oscillation stops.

Next, the clock signal CK 3 is supplied from the select circuit 136 to the down counter 137 and counted down. When the count value of the down counter 137 becomes “0”, the borrow signal BO is output to the CR oscillation circuit 33.
And its oscillation stops. At the same time as the start of down counting of the clock signal CK3, the enable signal OEN from the timing generator 135 becomes active, and the total number of down counting, that is, (Np-N1) pulse signals from the gate circuit 38 is output from the output terminal 39. It is sent to arithmetic means such as a microcomputer.

Since the value of N1 represents the magnitude of the hydraulic pressure, the arithmetic means can detect the magnitude of the hydraulic pressure by subtracting the value of (Np-N1) from the preset value Np known in advance. it can. Therefore, in this embodiment, the CR oscillation circuit 31 constitutes a means as a first oscillation circuit for generating a detection frequency signal (clock signal CK1) according to the capacitance of the detection unit 1, and the CR oscillation circuit 33
Constitutes a second oscillation circuit that generates a reference frequency signal (clock signal CK3) according to the capacitance of the reference unit 2.
Further, the frequency divider 134 and the timing generator 13
5. The measuring unit that measures the number of periods of the detected frequency signal within a predetermined period of the reference frequency signal (actually, the difference from the predetermined value) by the selector circuit 136 and the down counter 137 to generate a measurement signal Constitute.

In this embodiment, the same effects as those of the previous embodiment can be obtained, but the structure of the detector 11 and the structure of the circuit 13 can be further simplified.
A cheaper detection circuit can be realized.

In the above three embodiments, the structure of the capacitor of the detecting section is such that the distance between the fixed electrode and the movable electrode changes according to the oil pressure. However, the movable electrode is biased according to the oil pressure. Alternatively, a structure may be employed in which the area opposed to the fixed electrode changes without changing the distance from the fixed electrode. In the case of such a structure, the relationship between the magnitude of the received hydraulic pressure and the change in the capacitance becomes proportional.

In the above two embodiments, the action received from the outside is detected as a change in capacitance.
The present invention is not limited to this, and it is also possible to adopt a configuration in which the change is detected as a change in inductance or light amount. That is, it goes without saying that the present invention can be widely applied to a circuit that directly converts an analog amount of an externally applied action into a change in frequency.

Further, in the above three embodiments, the circuit section 3 is constituted by the gate array including the oscillation circuit for generating the detection frequency signal and the reference frequency signal and the measuring section for measuring the frequency (period) of these signals. and a built-in microcomputer as arithmetic means to the circuit portion as the fourth embodiment can also be a so-called one-chip microcomputer.

In such a one-chip microcomputer configuration, each clock signal is measured by a timer in the microcomputer. As a method, the period of the reference frequency signal generated according to the capacitance of the capacitor of the reference unit is measured by an accurate clock from a timer, and the time for measuring the detection frequency signal is determined according to the measurement result. I do. After that, frequency measurement is performed in the same manner as in the above embodiment.

According to this configuration, a highly accurate detection can be achieved, and a very simple and small measuring system can be realized at a low cost. In addition to this, by adopting a configuration for detecting a change in inductance or light amount, it is possible to obtain excellent effects as an extremely wide range measurement system.

[0073]

According to the present invention, as is clear from the above examples, the first, a detecting unit whose capacitance changes in response to a predetermined external action, the capacitance is a predetermined action A reference portion that does not change, a first oscillation circuit that generates a detection frequency signal according to the capacitance of the detection portion, a second oscillation circuit that generates a reference frequency signal according to the capacitance of the reference portion,
A measuring unit that measures the number of periods of the detection frequency signal within a predetermined period of the reference frequency signal and generates a measurement signal.
Therefore, the first and second oscillation circuits respectively have capacitance and resistance.
A source that generates an oscillation signal with a frequency determined according to the resistance value
A vibration section, and a coil related to the capacitance in response to a predetermined control signal.
Circuit for equalizing the amount of charge remaining in the capacitor
Secondly, statically in response to a predetermined external action.
Depending on the detection unit where the capacitance changes,
A reference portion whose capacitance does not change, and a capacitance of the detection portion
A first oscillation circuit that generates a detection frequency signal in accordance with
A reference frequency signal is generated according to the capacitance of the reference unit.
A second oscillating circuit and a cycle of the reference frequency signal with high precision.
Measurement based on the timer, and
A predetermined period is determined, and the detection frequency within the predetermined period is determined.
The provision of the calculation means for measuring the number of signal periods provides the following effects.

Since the detecting section and the reference section are provided in the same environment, a change in the environment, in this case, for example, a change in the chemical composition of the hydraulic oil to be detected changes the dielectric constant of the capacitor of the detecting section. In such a case, the detection error can be minimized.

Further, since the change in the capacitance is directly converted into a pulse signal (digital signal) without being converted into an analog signal, an amplifier for amplifying the analog signal and an A / D for converting the analog signal into a digital signal. There is no need to use a converter. Therefore, the circuit configuration is simplified, and it can be realized at low cost. In addition, it is possible to avoid the occurrence of a detection error due to the influence of temperature drift, humidity drift, power supply voltage fluctuation, and the like.

Furthermore, since the circuit section can be realized in a very small area of silicon, which is a material of the IC, by configuring the circuit section with an IC of a gate array, the gate forming the oscillation circuit of each CR oscillation circuit can be realized. Can be made uniform, and the oscillation conditions such as the oscillation frequency can be made the same. Further, by providing a means for adjusting the oscillation frequency, the detection accuracy can be extremely increased.

An oscillation circuit constituted by a gate array includes an inverter or a clocked gate circuit which enters a high-impedance output state by a clock signal and generates an oscillation signal having a frequency determined according to the capacitance and resistance value. The system includes an oscillating unit and a gate circuit that generates a clock signal according to a control signal, and each oscillating unit stops or starts an oscillating operation according to a clock signal applied thereto, thereby providing a high-precision power supply. It is not necessary, and there is an effect of realizing an inexpensive capacitance detection circuit that has little change with respect to changes in the external environment and is inexpensive.

An oscillating section for generating an oscillation signal having a frequency determined according to the capacitance and the resistance value, and a circuit for equalizing the amount of charge remaining in the capacitor related to the capacitance according to the clock signal. With this configuration, a high-speed switching operation of the plurality of oscillating units can be performed, so that the effect of increasing the detection speed can be obtained.

[0079] As another configuration, by using a one-chip microcomputer with built-in microcomputer as arithmetic means to the circuit section, while enabling more accurate detection, a very simple and compact measuring system By adopting a configuration that can be realized at low cost and that detects not only a change in capacitance but also a change in inductance or light quantity, an excellent effect can be obtained as an extremely wide range measurement system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a capacitance detection circuit according to the present invention.

FIG. 2A is a timing chart when a power supply VDD supplied to a circuit unit 3 is supplied. (B) is a timing chart showing the counting operation of the up / down counter 37.

FIG. 3 is a diagram showing a timing chart of signal waveforms inside a circuit section 3 in FIG. 1;

FIG. 4 is a diagram showing a circuit configuration provided with a means for adjusting an oscillation frequency.

FIG. 5 is a specific circuit diagram of the CR oscillation circuit in FIG.

FIG. 6 is a diagram showing a clocked gate circuit composed of a CMOS semiconductor device.

FIG. 7 is a timing chart of pulse signals E0 to E8 in FIG.

FIG. 8 is a circuit diagram of a CR oscillation circuit of another embodiment different from the CR oscillation circuit of FIG.

FIG. 9 is a circuit diagram of a CR oscillation circuit using a tri-state buffer.

FIG. 10 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a third example of the present invention.

[Explanation of symbols]

 Reference Signs List 1,11 detection unit 2,12 reference unit (reference unit) 3,13 circuit unit 31,32,33 CR oscillation circuit 34,134 frequency divider 35,135 timing generator 36,136 selector circuit 37 up / down counter 41 latch circuit 137 Down counter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01L 1/14 G01D 5/24 G01P 15/125 G01L 9/12

Claims (2)

(57) [Claims] A detecting unit for changing the capacitance in response to a predetermined external operation; a reference unit in which the capacitance does not change in accordance with the predetermined operation; and a detecting unit in accordance with the capacitance of the detecting unit. A first oscillation circuit that generates a detection frequency signal, a second oscillation circuit that generates a reference frequency signal in accordance with the capacitance of the reference unit, and the detection frequency signal within a predetermined period of the reference frequency signal A measurement unit that measures the number of periods of the measurement signal to generate a measurement signal;
And configure wherein the first and second oscillator circuits are respectively capacitance and
Generates an oscillation signal with a frequency determined by the resistance value
An oscillating unit, and the capacitance is related to a predetermined control signal.
The electrostatic capacitance detection circuit according to claim Rukoto that having a circuitry for equalizing the amount of charge remaining in the capacitor. 2. An electrostatic capacitance according to a predetermined action from the outside.
And a reference unit whose capacitance does not change due to the predetermined action.
And generating a detection frequency signal according to the capacitance of the detection unit.
A first oscillation circuit for generating a reference frequency signal in accordance with the capacitance of the reference section.
A second oscillating circuit, and a period of the reference frequency signal based on a high-precision timer.
Measurement, determine a predetermined period according to the measurement result,
Measuring the number of periods of the detection frequency signal within the predetermined period
And a calculating means for performing the operation .