CN213600832U

CN213600832U - High-precision chip test time cost analysis system

Info

Publication number: CN213600832U
Application number: CN202022657165.XU
Authority: CN
Inventors: 张经祥; 魏津; 杜宇
Original assignee: Sundec Semiconductor Technology Shanghai Co Ltd
Current assignee: Sundak Semiconductor Technology Shanghai Co ltd
Priority date: 2020-11-17
Filing date: 2020-11-17
Publication date: 2021-07-02
Anticipated expiration: 2030-11-17
Also published as: TWM619862U

Abstract

The utility model discloses a high-precision chip testing time cost analysis system, which comprises a FPGA timing module; the FPGA timing module is respectively connected with the automatic integrated circuit tester and the module to be tested; the FPGA timing module realizes data communication with an upper computer through a data transmission module. The utility model discloses a high accuracy chip test time cost analysis system adopts the mode of hardware timing to set up FPGA timing module promptly and realizes the high accuracy timing to chip test time, and the measuring accuracy can reach 10^‑8The timing precision of the tester is far superior to that of the similar traditional ATE tester; the hardware timing mode avoids the influence of the performance difference of the upper computer on the time used for calculation and test; the whole structure is simple and canCan conveniently transform the prior device, and has wide application prospect.

Description

High-precision chip test time cost analysis system

Technical Field

The utility model belongs to the technical field of the semiconductor, a high accuracy chip test time cost analysis system is related to.

Background

The semiconductor industry refers to Integrated Circuit (IC) automatic testers, which are used to detect the functional integrity of an IC and provide the final process for the production and manufacture of the IC to ensure the quality of the IC.

Many chip test machines currently provide analysis for test time, but because they mostly use the way of upper computer software timing (the schematic structural diagram of the system along the chip test time direction is shown in fig. 1), the performance difference of different computers will affect the accurate calculation of the test time. Because time cannot be accurately calculated, current test machine products cannot provide time-based fine analysis on the cost of each test item of a chip, and cannot perform various test links in a segmented manner, such as the material changing time of a mechanical arm and the fine time of various test items of an ATE (automatic test equipment) test machine (namely an integrated circuit automatic test machine). This leads to the inability of both the user and the manufacturer of the chip tester to know the precise time of the testing link, and to the inability of the chip tester to make better optimization and cost assessment of the testing link and the testing equipment (ATE tester, robotic arm), etc.

Therefore, it is very practical to develop a device or system for analyzing the chip testing time cost with high precision.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art and can't realize the defect to the high accuracy analysis of chip test time cost, provide a system that carries out high accuracy analysis to chip test time cost.

In order to achieve the above object, the utility model provides a following technical scheme:

a high-precision chip test time cost analysis system comprises an FPGA timing module;

the FPGA timing module is respectively connected with the automatic integrated circuit tester and the module to be tested;

the FPGA timing module realizes data communication with an upper computer through a data transmission module.

The utility model discloses a high accuracy chip test time cost analysis system, when the mode that adopts hardware timing set up FPGA timing module promptly and realize the high accuracy meter to chip test time, the measuring accuracy canUp to 10^-8The timing precision of the tester is far better than that of a similar traditional ATE tester, and meanwhile, the influence of performance difference of an upper computer on the time used for calculation and test is avoided by the way of hardware timing, so that the tester has a wide application prospect.

As a preferred technical scheme:

according to the high-precision chip testing time cost analysis system, the module to be tested is a mechanical arm. The protection scope of the present invention is not limited to this, and here, only the mechanical arm is taken as an example, and other devices are also applicable.

According to the high-precision chip testing time cost analysis system, the module to be tested (the mechanical arm) is connected with the automatic integrated circuit tester, and the mechanical arm is controlled by the automatic integrated circuit tester.

According to the high-precision chip test time cost analysis system, the data transmission module is PCIE data transmission hardware, namely a data connecting line and a wireless transmission module.

According to the high-precision chip test time cost analysis system, the FPGA timing module comprises a PCIE communication submodule, a condition trigger circuit and a timer;

the PCIE communication submodule is connected with the data transmission module, the PCIE communication submodule, the condition trigger circuit and the timer are sequentially connected, and the timer realizes high-precision timing through a high-precision crystal oscillator in the timer. The PCIE communication submodule acquires a test timing signal transmitted by an upper computer through the data transmission module, then the condition trigger circuit triggers, and a timer starts (the high-precision crystal oscillator with the temperature compensation function works) to start timing.

According to the high-precision chip testing time cost analysis system, the upper computer is provided with the upper computer software, and the upper computer software comprises a data acquisition software module, a data analysis software module, a report generation software module and a UI display software module which are sequentially connected. The real time cost spent in each link and each test item of the chip test can be conveniently counted and analyzed by using the upper computer software.

The high-precision chip testing time cost analysis system is characterized in that the upper computer is a computer.

Has the advantages that:

(1) the utility model discloses a high accuracy chip test time cost analysis system adopts the mode of hardware timing to set up FPGA timing module promptly and realizes the high accuracy timing to chip test time, and the measuring accuracy can reach 10^-8The timing precision of the tester is far superior to that of the similar traditional ATE tester;

(2) the utility model discloses a high accuracy chip test time cost analysis system, the influence of host computer performance difference to the time that the calculation test used has been avoided to this mode of hardware timing;

(3) the utility model discloses a high accuracy chip test time cost analysis system, overall structure is comparatively simple, can conveniently reform transform current device, has application prospect.

Drawings

FIG. 1 is a schematic diagram of a chip testing time direction system of a conventional chip tester;

fig. 2 is the structure diagram of the high-precision chip testing time cost analysis system of the present invention.

Detailed Description

The following describes the present invention with reference to the accompanying drawings.

A high-precision chip test time cost analysis system is shown in figure 2 and comprises an FPGA timing module;

the FPGA timing module is respectively connected with an automatic integrated circuit tester (corresponding to the ATE tester in FIG. 2) and a mechanical arm, and the mechanical arm is connected with the automatic integrated circuit tester and controlled by the automatic integrated circuit tester;

the FPGA timing module realizes data communication with an upper computer (computer) through PCIE data transmission hardware;

the FPGA timing module comprises a PCIE communication submodule, a condition trigger circuit and a timer (the timer realizes high-precision timing through a high-precision crystal oscillator with a temperature compensation function in the timer) which are connected in sequence, wherein the PCIE communication submodule is connected with PCIE data transmission hardware;

the upper computer (computer) is provided with upper computer software, and the upper computer software comprises a data acquisition software module, a data analysis software module, a report generation software module and a UI display software module which are connected in sequence.

Through verifying, the utility model discloses a high accuracy chip test time cost analysis system adopts the mode of hardware timing to set up FPGA timing module promptly and realizes the high accuracy timing to chip test time, and the measuring accuracy can reach 10^-8The timing precision of the tester is far superior to that of the similar traditional ATE tester; the hardware timing mode avoids the influence of the performance difference of the upper computer on the time used for calculation and test; the whole structure is simple, the existing device can be conveniently transformed, and the device has a wide application prospect.

Although specific embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these embodiments are merely illustrative and various changes or modifications may be made without departing from the spirit and scope of the invention.

Claims

1. A high-precision chip test time cost analysis system is characterized by comprising an FPGA timing module;

2. The system of claim 1, wherein the module under test is a robotic arm.

3. The high-precision chip testing time cost analysis system according to claim 2, wherein the module to be tested is connected with an automatic integrated circuit tester and controlled by the automatic integrated circuit tester.

4. The system of claim 1, wherein the data transmission module is PCIE data transmission hardware.

5. The system according to claim 4, wherein the FPGA timing module comprises a PCIE communication sub-module, a conditional trigger circuit and a timer;

the PCIE communication submodule is connected with the data transmission module, the PCIE communication submodule, the condition trigger circuit and the timer are sequentially connected, and the timer achieves temperature compensation on the high-precision crystal oscillator through a temperature compensation circuit in the timer, so that high-precision timing is achieved.

6. The system for analyzing the testing time and cost of the high-precision chip according to claim 1, wherein the upper computer is provided with upper computer software, and the upper computer software comprises a data acquisition software module, a data analysis software module, a report generation software module and a UI display software module which are sequentially connected.

7. The high-precision chip test time cost analysis system according to claim 6, wherein the upper computer is a computer.