CN213583774U

CN213583774U - Chip packaging structure and memory

Info

Publication number: CN213583774U
Application number: CN202022789267.7U
Authority: CN
Inventors: 孙成思; 孙日欣; 刘小刚
Original assignee: Biwin Storage Technology Co Ltd
Current assignee: Biwin Storage Technology Co Ltd
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2021-06-29
Anticipated expiration: 2030-11-26

Abstract

The utility model discloses a chip packaging structure, this chip packaging structure include the PCB base plate and be located on the PCB base plate and follow supreme DRAM chip wafer, FOW layer and the FLASH chip wafer that set gradually down, wherein, the DRAM chip wafer is for the a plurality of that piles up in proper order, and is adjacent be equipped with first bed course between the DRAM chip wafer, the FOW layer with DRAM chip wafer dislocation set is located in order to constitute the region of suspension between FOW layer and the PCB base plate, be provided with in the region of suspension and be located on the PCB base plate, be used for supporting the gasket on FOW layer. The utility model discloses a chip package structure encapsulation operating condition is reliable and stable to help reduce cost, promote storage product quality and data transmission's stability. Furthermore, the utility model discloses still disclose a memory.

Description

Chip packaging structure and memory

Technical Field

The utility model relates to a chip package technical field, in particular to chip package structure and memory.

Background

Modern portable electronic products put higher demands on microelectronic packaging, and the continuous pursuit of lighter, thinner, smaller, high reliability and low power consumption thereof pushes the microelectronic packaging to develop towards a three-dimensional packaging mode with higher density.

The multi-chip stacking technology is a basic work of three-dimensional packaging, and particularly for storage products, the multi-layer chip stacking technology determines the degree of product size reduction and the integration level of product components.

In the existing chip packaging structure, chip wafers with different specifications, types and sizes are stacked mutually, the chip wafer positioned at the upper layer is generally in a suspended state, and due to the thin chip wafer, when wire bonding operation is performed, the probability of chip wafer fragmentation is high, and the packaging operation condition is not stable enough and reliable enough; in addition, if the distance between the chip wafers is too large, because the gold wires are very thin, the gold wires are easy to break during routing, even if the routing is successful, the cost is increased due to the overlong gold wires, and the gold wires are easy to break due to external force in the subsequent packaging process; if the distance between the chip wafers is too small, the radian part formed on the gold wire is easy to touch the chip wafer above to cause a short circuit, so that the quality of a storage product and the stability of data transmission are influenced.

SUMMERY OF THE UTILITY MODEL

The main objective of the present invention is to provide a chip package structure, which aims to solve the technical problem existing in the background art.

In order to achieve the above object, the present invention provides a chip package structure, which comprises a PCB substrate, and a DRAM chip wafer, a FOW layer, and a FLASH chip wafer sequentially disposed on the PCB substrate from bottom to top, wherein,

DRAM chip wafer is for a plurality of that piles up in proper order, and is adjacent be equipped with first bed course between the DRAM chip wafer, the FOW layer with DRAM chip wafer dislocation set is located with the constitution in the suspension area between FOW layer and the PCB base plate, be provided with in the suspension area and be located on the PCB base plate, be used for supporting the gasket on FOW layer.

Preferably, the FLASH chip wafers are stacked in sequence, and a second cushion layer is arranged between every two adjacent FLASH chip wafers.

Preferably, the first pad layer and the second pad layer have a height of 10 to 20 μm.

Preferably, the upper surface of the DRAM chip wafer is provided with a plurality of first ports, adjacent DRAM chip wafers are arranged in a staggered manner, and the plurality of first ports are exposed at staggered positions;

and/or a plurality of second ports are arranged on the upper surface of the FLASH chip wafer, the adjacent FLASH chip wafers are arranged in a staggered mode, and the second ports are exposed at the staggered positions.

Preferably, a third cushion layer is arranged between the PCB substrate and the DRAM chip wafer at the bottom.

Preferably, the height of the third pad layer is 50 μm.

Preferably, the height of the FOW layer is 50-100 μm.

Preferably, the gasket is a plurality of gaskets arranged at intervals.

Preferably, the upper surface of the PCB substrate is provided with a gold finger interface, and the lower surface of the PCB substrate is provided with a plurality of solder balls.

The utility model also provides a memory, which comprises a mainboard and the chip packaging structure recorded in the above, wherein the chip packaging structure is arranged on the mainboard; the chip packaging structure comprises a PCB substrate, and a DRAM chip wafer, a FOW layer and a FLASH chip wafer which are arranged on the PCB substrate from bottom to top in sequence, wherein,

DRAM chip wafer is for a plurality of that piles up in proper order, and is adjacent be equipped with first bed course between the DRAM chip wafer, FOW layer and top DRAM chip wafer dislocation set is located in order constituting the suspension area between FOW layer and the PCB base plate, be provided with in the suspension area and be located on the PCB base plate, be used for supporting the gasket on FOW layer.

The embodiment of the utility model provides a chip package structure that technical scheme provided comprises PCB base plate, DRAM chip wafer, FOW layer and FLASH chip wafer, and a plurality of DRAM chip wafer piles up in proper order, and is moderate with the assurance interval size through the first bed course that establishes between the adjacent DRAM chip wafer, and the gold thread is difficult for splitting and can not the overlength, helps reduce cost, and the radian part that forms on the gold thread is difficult for touching the chip wafer above to avoid the condition of short circuit, help promoting storage product quality and data transmission's stability; and the FOW layer and the FLASH chip wafer on the FOW layer are supported by the arranged gasket, so that a stable routing structure can be provided for subsequent routing and packaging operations, the risk of chip wafer breakage is reduced, and the packaging operation conditions are stable and reliable.

Drawings

Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a chip package structure according to another embodiment of the present invention;

fig. 3 is a schematic structural diagram of the chip package structure in fig. 2 from another view angle.

Detailed Description

In the following, the embodiments of the present invention will be described in detail with reference to the accompanying drawings, and obviously, the described embodiments are only some embodiments, not all embodiments, of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The utility model provides a chip package structure, referring to fig. 1, the chip package structure comprises a PCB substrate 10, and a DRAM chip wafer 20, a FOW layer 30 and a FLASH chip wafer 40 which are arranged on the PCB substrate 10 in sequence from bottom to top, wherein,

DRAM chip wafer 20 is the several that piles up in proper order, is equipped with first bed course between the adjacent DRAM chip wafer 20, and FOW layer 30 and DRAM chip wafer 20 dislocation set constitute the suspension area that is located between FOW layer and PCB base plate 10, are provided with in the suspension area to be located on PCB base plate 10, are used for supporting the gasket 50 of FOW layer 30.

The chip packaging structure related to the embodiment is a three-dimensional package of a memory chip, and specifically, the chip packaging structure mainly comprises a PCB substrate 10, a DRAM chip wafer 20, a FOW layer 30 and a FLASH chip wafer 40, wherein the DRAM chip wafer 20, the FOW layer 30 and the FLASH chip wafer 40 are located on the PCB substrate 10 and are sequentially stacked from bottom to top, and wherein:

the PCB substrate 10 is divided into mounting sites for mounting the DRAM chip wafer 20, the FOW layer 30 and the FLASH chip wafer 40 on the upper surface thereof, and other mounting sites for mounting other components may be further divided into the PCB substrate 10, which is not shown in detail.

The DRAM (Dynamic Random Access Memory) chip wafer is provided with a plurality of DRAM chip wafers 20, the DRAM chip wafers 20 are identical in size and are stacked in sequence in the vertical direction, a first cushion layer is arranged between any two adjacent DRAM chip wafers 20, a certain distance is reserved between the adjacent DRAM chip wafers 20 through the first cushion layer, and the height of the first cushion layer is the distance between the adjacent DRAM chip wafers 20. Preferably, the first pad layer is made of DAF-epoxy resin material, the height of the first pad layer ranges from 10 to 50 μm, and the first pad layer is set according to actual requirements and is not limited herein.

The FOW (film on wire) layer is a new supporting type chip adhesive, generally in a thin film form, and is used for supporting the FLASH chip wafer 40, and can realize the spacing between the DRAM chip wafer 20 and the FLASH chip wafer 40, and prevent the short circuit caused by the contact between a gold wire bonded below and the upper chip wafer. Preferably, the FOW layer 30 is made of HR-400-S34-epoxy resin material, the height of which is 50-100 μm, and the FOW layer is set according to actual requirements and is not limited herein. The number of the FLASH chip wafers 40 may be a single wafer, or several wafers stacked from bottom to top in sequence, and the number is set according to actual requirements.

The suspended portion formed by the staggered arrangement of the FOW layer 30 and the DRAM chip wafer 20 is supported by the spacers 50, and the height, number and arrangement position of the spacers 50 are set according to actual conditions. Preferably, the gasket 50 is made of a silicon dioxide material, so that not only can the FOW layer 30 and the upper FLASH chip wafer 40 be stably supported, but also the thermal conductivity is provided, heat generated by the chip wafer can be rapidly conducted to the PCB substrate 10 through the gasket 50, the heat dissipation speed is increased, and the working performance of the storage product is further improved.

Certainly, during packaging, a packaging layer (not shown) is further disposed on the PCB substrate 10, and the packaging layer is attached to the PCB substrate 10 to implement packaging of each component on the PCB substrate 10, such as the DRAM chip wafer 20 and the FLASH chip wafer 40. Wherein, the packaging layer is preferably made of epoxy resin material.

The chip packaging structure consists of a PCB substrate 10, DRAM chip wafers 20, a FOW layer 30 and a FLASH chip wafer 40, wherein a plurality of DRAM chip wafers 20 are sequentially stacked, the spacing between adjacent DRAM chip wafers 20 is ensured to be moderate through a first cushion layer, gold wires are not easy to break and cannot be overlong, the cost is reduced, and arc parts formed on the gold wires are not easy to touch the upper chip wafer, so that the short circuit condition is avoided, and the quality of a storage product and the stability of data transmission are improved; in addition, the FOW layer 30 and the FLASH chip wafer 40 thereon are supported by the arranged gasket 50, so that a stable routing structure can be provided for subsequent routing and packaging operations, the risk of chip wafer breakage is reduced, and the packaging operation conditions are stable and reliable.

In a preferred embodiment, referring to fig. 2, the FLASH chip wafers 40 are stacked in sequence, and a second pad layer is disposed between adjacent FLASH chip wafers 40. In this embodiment, a plurality of FLASH chip wafers 40 are provided, and the plurality of FLASH chip wafers 40 have the same size and are sequentially stacked in the vertical direction, wherein a second cushion layer is provided between any adjacent FLASH chip wafers 40, a certain distance is provided between adjacent FLASH chip wafers 40 by the second cushion layer, and the height of the second cushion layer is the distance between adjacent FLASH chip wafers 40. In accordance with the first pad layer of the above embodiment, preferably, the second pad layer is made of DAF-epoxy resin material, and has a height ranging from 10 to 50 μm, and is set according to actual requirements, which is not limited herein.

Further, it is preferable that the first pad layer and the second pad layer have a height of 10 μm to 20 μm. Namely, when the height of the first cushion layer is 10-20 μm, the space between the adjacent DRAM chip wafers 20 is moderate, and when the height of the second cushion layer is 10-20 μm, the space between the adjacent FLASH chip wafers 40 is moderate, so that the space can be greatly saved, the structure size can be reduced, the routing is proper, and the possibility of short circuit is low.

In a preferred embodiment, referring to fig. 2 and 3, the upper surface of the DRAM chip wafer 20 is provided with a plurality of first ports 1, adjacent DRAM chip wafers 20 are arranged in a staggered manner, and the plurality of first ports 1 are exposed at staggered positions;

and/or the upper surface of the FLASH chip wafer 40 is provided with a plurality of second ports 2, the adjacent FLASH chip wafers 40 are arranged in a staggered manner, and the plurality of second ports 2 are exposed at the staggered positions.

In the embodiment, the plurality of first ports 1 arranged on the DRAM chip wafer 20 can be connected with other DRAM chip wafers 20 or the PCB substrate 10 through gold wires, the plurality of first ports 1 are arranged on the upper surface of the DRAM chip wafer 20 near the edge thereof, the first ports 1 are exposed by the staggered arrangement between the adjacent DRAM chip wafers 20, and the routing operation is simple and convenient; correspondingly, the plurality of second ports 2 arranged on the FLASH chip wafer 40 can be connected with other FLASH chip wafers 40 or the PCB substrate 10 through gold wires, the plurality of second ports 2 are arranged on the upper surface of the FLASH chip wafer 40 close to the edge of the FLASH chip wafer, the second ports 2 are exposed through the staggered arrangement of the adjacent FLASH chip wafers 40, and the routing operation is simple and convenient.

In a preferred embodiment, a third pad layer is disposed between the PCB substrate 10 and the bottom DRAM chip wafer 20. The area size of this third bed course is unanimous with DRAM chip wafer 20 of bottom, because of the upper surface unevenness of PCB base plate 10, and the chip wafer is ultra-thin structure and has smooth surface, if directly place the chip wafer on PCB base plate 10, easily cause the chip wafer cracked because of the atress is uneven when the encapsulation, so set up DRAM chip wafer 20 interval on PCB base plate 10 through establishing the third bed course, can avoid DRAM chip wafer 20 and PCB base plate 10 direct contact, further reduce the cracked risk of chip wafer. In accordance with the first pad layer of the above embodiment, preferably, the third pad layer is made of DAF-epoxy resin material, and has a height ranging from 10 to 50 μm, and is set according to actual requirements, which is not limited herein.

Further, as a preferable arrangement, the height of the third pad layer is 50 μm. That is, when the height of the third pad layer is 50 μm, besides the DRAM chip wafers 20 are spaced on the PCB substrate 10, the third pad layer can also form a good support and buffer effect for the DRAM chip wafers 20, so as to provide a stable wire bonding structure for subsequent wire bonding and packaging operations.

Further, the height of the FOW layer 30 is preferably 50 μm to 100. mu.m. That is, when the height of the FOW layer 30 is 50 μm to 100 μm, the FLASH chip wafer 40 can be well supported, and the space can be greatly saved and the structure size can be reduced.

In a preferred embodiment, the spacers 50 are spaced apart. The FOW layer 30 and the FLASH chip wafer 40 thereon are supported by the gaskets 50 together, so that the routing structure is more stable, and the packaging operation condition is more stable and reliable. Moreover, when the spacers 50 are made of silicon dioxide, the spacers 50 conduct heat together, so that the heat dissipation speed can be further increased, and the working performance of the storage product can be improved. Specifically, the spacers 50 are five and are spaced apart in the suspended region.

In a preferred embodiment, the upper surface of the PCB substrate 10 is provided with a gold finger interface, and the lower surface of the PCB substrate 10 is provided with a plurality of solder balls. The gold finger interfaces provided on the upper surface of the PCB substrate 10 are used for connecting with ports on the DRAM chip wafer 20, the FLASH chip wafer 40, and other elements through gold wires to implement data communication, and the number and the arrangement positions thereof are set according to actual situations, which is not limited herein. In addition, the solder balls disposed on the lower surface of the PCB substrate 10 have two functions: the heat dissipation structure is used for welding and fixing the PCB substrate 10 on the memory system mainboard on one hand, and can transfer the heat of the PCB substrate 10 to the system mainboard on the other hand, so as to accelerate the heat dissipation speed of the chip. A plurality of solder balls may be uniformly distributed on the PCB substrate 10 to achieve uniform heat conduction and improve soldering balance of the PCB. In addition, the number of solder balls can be set according to practical situations, and is not limited herein.

The utility model discloses still provide a memory, this memory includes mainboard and chip package structure, and chip package structure sets up on the mainboard, and this chip package structure's concrete structure refers to above-mentioned embodiment, because this memory has adopted all technical scheme of above-mentioned all embodiments, consequently has all technical effect that the technical scheme of above-mentioned embodiment brought at least, no longer gives unnecessary details one by one here.

What just go up be the utility model discloses a part or preferred embodiment, no matter be characters or the drawing can not consequently restrict the utility model discloses the scope of protection, all with the utility model discloses a holistic thought down, utilize the equivalent structure transform that the contents of the description and the drawing do, or direct/indirect application all includes in other relevant technical field the utility model discloses the within range of protection.

Claims

1. A chip packaging structure is characterized by comprising a PCB substrate, a DRAM chip wafer, a FOW layer and a FLASH chip wafer which are arranged on the PCB substrate from bottom to top in sequence, wherein,

2. The chip package structure according to claim 1, wherein the FLASH chip wafers are stacked in sequence, and a second cushion layer is disposed between adjacent FLASH chip wafers.

3. The chip package structure according to claim 2, wherein the first pad layer and the second pad layer have a height of 10 μm to 20 μm.

4. The chip packaging structure according to claim 2, wherein the upper surface of the DRAM chip wafer is provided with a plurality of first ports, adjacent DRAM chip wafers are arranged in a staggered manner, and the plurality of first ports are exposed at staggered positions;

5. The chip package structure according to claim 1, wherein a third pad layer is disposed between the PCB substrate and the bottom DRAM chip wafer.

6. The chip package structure according to claim 5, wherein the third pad layer has a height of 50 μm.

7. The chip package structure of claim 1, wherein the FOW layer has a height of 50 μm to 100 μm.

8. The chip package structure according to claim 1, wherein the pad is spaced apart from the chip.

9. The chip package structure of claim 1, wherein the PCB substrate has a gold finger interface on an upper surface thereof and a plurality of solder balls on a lower surface thereof.

10. A memory comprising a motherboard and the chip package structure of any of claims 1-9, the chip package structure disposed on the motherboard.