CN101840893A - Packaging structure of up-right type chip - Google Patents
Packaging structure of up-right type chip Download PDFInfo
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- CN101840893A CN101840893A CN200910129703A CN200910129703A CN101840893A CN 101840893 A CN101840893 A CN 101840893A CN 200910129703 A CN200910129703 A CN 200910129703A CN 200910129703 A CN200910129703 A CN 200910129703A CN 101840893 A CN101840893 A CN 101840893A
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- type chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Abstract
The invention discloses a packaging structure of an up-right type chip, which comprises at least one up-right chip and a carrier plate. A plurality of connection points are arranged on one side edge of the at least one up-right chip; a plurality of welding pads are correspondingly arranged on the upper surface of the carrier plate; and the carrier plate supports the at least one up-right chip, and the plurality of connection points are electrically connected with the plurality of welding pads. Thus, the packaging structure of a substrate of the up-right type chip can simplify a circuit of the carrier plate and can arrange more chips on the substrate effectively.
Description
[technical field]
The present invention relates to a kind of encapsulating structure of up-right type chip, particularly about a kind of semiconductor package that on support plate, is provided with up-right type chip.
[background technology]
Existing chip has an active surface and a back side, and the combination of a chip and a substrate package mostly is the horizontal mode of level, and the mode that its chip stacks also is the horizontal mode that stacks of level.
Please refer to shown in Figure 1A, it discloses a kind of existing schematic diagram that stacks the encapsulating structure of chip, described substrate package structure comprises a substrate 11, one first chip 12, one second chip 12a, described first chip 12 of carrying and the described second chip 12a on the described substrate 11.The active surface of described first chip 12 up, and the back side is down and be attached on the described substrate 11; The active surface of the described second chip 12a up, and the back side is down and be attached on the active surface of described first chip 12.By a plurality of connecting lines 121 and 121a and 11 electric connections of described substrate, described substrate 11 lower surfaces are provided with a plurality of tin balls 111, in order to electrically connect with an external device (ED) (not illustrating) respectively for described first chip 12 and the described second chip 12a.Because must keeping a space, described first chip 12 active surface up forms weld pad (indicating) and described connecting line 121 electric connections, therefore the width of the described second chip 12a must be less than the width of described first chip 12, the volume that is to say chip more up is relatively little, this kind mode can't upwards stack too many chip, and the effect that the stacks inefficiency that also more heals toward the upper strata.Simultaneously, stack chip the more, more the connecting line of chip up also can be longer, and it increases complexity and wire rod cost in the routing design more easily.
Please refer to shown in Figure 1B, it discloses the another kind of existing schematic diagram that stacks the encapsulating structure of chip, described substrate package structure comprises a substrate 11, one first chip 13, one second chip 13a, described first chip 13 of carrying and the described second chip 13a on the described substrate 11.The active surface of described first chip 13 down, and the back side is located on the described substrate 11 up and in the mode of flip-chip; The active surface of the described second chip 13a down, and the back side is up and be located in the mode of flip-chip on the back side of described first chip 13.Described first chip 13 electrically connects by a plurality of projections 131 and described substrate 11, and the lower surface of described substrate 11 is provided with a plurality of tin balls 111, in order to electrically connect with an external device (ED) (not illustrating).The described second chip 13a electrically connects by the back side of a plurality of projection 131a and described first chip 13, the via 132 of a plurality of correspondences is set simultaneously, so that the described second chip 13a is forwarded to described substrate 11 in described first chip 13.Yet the cost that makes described first chip 13 relatively that is provided with of described via 132 increases, and the active surperficial utilance of described first chip 13 is reduced.
Please refer to shown in Fig. 1 C, it discloses another existing schematic diagram that stacks the encapsulating structure of chip, described substrate package structure comprises a substrate 11, one first chip 14 and one second chip 14a, described first chip 14 of carrying and the described second chip 14a on the described substrate 11.The active surface of described first chip 14 up, and the back side is down and paste to pay on described substrate 11; The active surface of the described second chip 14a down, and the back side is located on the described first chip 14a up and in the mode of flip-chip.Described first chip 14 electrically connects by a plurality of connecting lines 141 and described substrate 11; The described second chip 14a is connected with the active surface electrical behavior of described first chip 14 by a plurality of projection 141a, and described substrate 11 lower surfaces are provided with a plurality of tin balls 111, in order to electrically connect with an external device (ED) (not illustrating).Because must keeping a space, described first chip 14 active surface up forms weld pad (indicating) and described connecting line 141 electric connections, therefore the width of the described second chip 14a must be less than the width of described first chip 14, the volume that is to say chip more up is relatively little, this kind mode can't upwards stack too many chip, and the effect that the stacks inefficiency that also more heals toward the upper strata.Again because the described second chip 14a must be forwarded to described substrate 11 by described first chip 14, therefore need take the weld pad (not indicating) and the connecting line 141 of described first chip, 14 parts, the active surface design complexity and the cost of described first chip 14 are increased, and the chip volume utilance is also reduced.
Please refer to shown in Fig. 1 D, it discloses another existing schematic diagram that stacks the encapsulating structure of chip, described substrate package structure comprises a substrate 11, one first chip 15 and one second chip 15a, described first chip 15 of carrying and the described second chip 15a on the described substrate 11.The active surface of described first chip 15 down, and the back side is located on the described substrate 11 up and in the mode of flip-chip; The active surface of the described second chip 15a up, and the back side is down and paste to pay on the back side of described first chip 15.Described first chip 15 electrically connects by a plurality of projections 151 and described substrate 11; The described second chip 15a electrically connects by a plurality of connecting line 151a and described substrate 11, and described substrate 11 lower surfaces are provided with a plurality of tin balls 111, in order to electrically connect with an external device (ED) (not illustrating).Because the connecting line 151a of the described second chip 15a is elongated, rupture easily when making packing colloid.Simultaneously, stack chip the more, more the connecting line of chip up also can be longer, and it increases complexity and wire rod cost in the routing design more easily.
In sum, existing structure can't effectively stack too many chip, and that chip stacks the utilance of its chip the more is lower, and the corresponding circuit of the described substrate complexity that also can heal, and the cost of encapsulating structure also can increase.Moreover, stack more multicore sheet for level is horizontal, often also need to grind chip thinner, its polish process increases manufacturing cost relatively and reduces chip yields (yield).In addition, stack the radiating efficiency that also causes each chip between the chip mutually and become relatively poor.
Therefore, be necessary to provide a kind of encapsulating structure of up-right type chip, to solve the existing in prior technology problem.
[summary of the invention]
Main purpose of the present invention provides a kind of encapsulating structure of up-right type chip, it is that vertical chip at least always is set on an encapsulating carrier plate, simplifying the circuit of described support plate, and can improve the radiating efficiency of chip, and save chip is carried out polish process.
Secondary objective of the present invention provides a kind of encapsulating structure of up-right type chip, it is that a plurality of up-right type chips are arranged on the support plate with well-regulated arrangement mode, simplifying the circuit of described support plate, and can effectively arrange more chip on described support plate.
Therefore another object of the present invention provides a kind of encapsulating structure of up-right type chip, and it is that a plurality of chips bottom is located in the groove of a support plate, can improve described chip and uprightly be located at steadiness on the described support plate.
Another purpose of the present invention provides a kind of encapsulating structure of up-right type chip, and it is to make up-right type chip being located on the support plate of an angle of tilting, and therefore can reduce the height of overall package structure.
For reaching above-mentioned purpose, the invention provides a kind of encapsulating structure of up-right type chip, it comprises an at least one up-right type chip and a support plate.One side of described at least one up-right type chip is provided with a plurality of contacts, and described upper surface of said carrier plate correspondence is provided with a plurality of weld pads, the described at least one up-right type chip of described carrier for bearing, and described a plurality of contact electrically connects described a plurality of weld pad.Therefore, the substrate encapsulation structure of described up-right type chip can be simplified the circuit of described support plate, and can effectively arrange more chip on described substrate.
In one embodiment of this invention, described at least one up-right type chip is two or above up-right type chip, has a gap between each two adjacent described up-right type chip.
In one embodiment of this invention, described at least one up-right type chip is two or above up-right type chip, is provided with a wall between each two adjacent described up-right type chip.
In one embodiment of this invention, described a plurality of wall is an epoxy resin layer.
In one embodiment of this invention, described support plate is provided with a groove, and described groove is in order to the described up-right type chip of planting, and described weld pad is positioned at described groove.
In one embodiment of this invention, described encapsulating structure comprises colloid in addition, with the described up-right type chip of support fixation in described upper surface of said carrier plate.
In one embodiment of this invention, described a plurality of up-right type chip has an angle of inclination with respect to described support plate.
In one embodiment of this invention, described support plate is a base plate for packaging or a chip.
In one embodiment of this invention, the contact of described up-right type chip electrically connects the weld pad of described support plate by conducting resinl or scolder.
In one embodiment of this invention, a lower surface of described support plate more is provided with a plurality of Metal Ball.
[description of drawings]
Figure 1A to 1D: the existing schematic diagram that stacks the encapsulating structure of chip.
Fig. 2 A to 2C: the present invention is made the schematic diagram of single up-right type chip by wafer.
Fig. 3 A and 3B: the present invention makes the schematic diagram that stacks up-right type chip by stacking wafer.
Fig. 4 A: the three-dimensional exploded view of the encapsulating structure of the up-right type chip of the first embodiment of the present invention.
Fig. 4 B: the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of the first embodiment of the present invention.
Fig. 5: the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of the second embodiment of the present invention.
Fig. 6 A: the three-dimensional exploded view of the encapsulating structure of the up-right type chip of the third embodiment of the present invention.
Fig. 6 B: the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of the third embodiment of the present invention.
Fig. 7: the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of the fourth embodiment of the present invention.
Fig. 8: the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of the fifth embodiment of the present invention.
Fig. 9: the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of the sixth embodiment of the present invention.
[embodiment]
For allowing above-mentioned purpose of the present invention, feature and advantage become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below:
Please refer to shown in Fig. 2 A, 2B and the 2C, it discloses the present invention and makes the schematic diagram of single up-right type chip by wafer, and it is applicable to makes the encapsulating structure with single up-right type chip 3.One wafer A at first is provided, and it has a plurality of chip unit A1; Then, go up a plurality of via A2 of making in described wafer A, described a plurality of via A2 are between the adjacent described chip unit A1 of per two rows, and the setting of slipping a line; At last, described wafer A is cut into a plurality of up-right type chips 3.Shown in Fig. 2 C, described up-right type chip 3 has an active surface (not indicating) and a back side (not indicating), has a plurality of contacts 31 on the surface of a side of described up-right type chip 3, and described contact 31 is described via A2 half.The manufacture method of wherein said via A2 can be preferably from a kind of method (through-silicon via) of straight-through silicon wafer perforation but be not limited to this.
Please refer to shown in Fig. 3 A and the 3B, the present invention makes the schematic diagram that stacks up-right type chip by stacking wafer, and it is applicable to makes the encapsulating structure with two or above up-right type chip 3.At first, shown in previous Fig. 2 A and 2B, provide a wafer A, it has a plurality of chip unit A1; Then, go up a plurality of via A2 of making in described wafer A, described a plurality of via A2 are between the adjacent described chip unit A1 of per two rows, and the setting of slipping a line; Then, shown in Fig. 3 A and 3B, utilize a plurality of walls 4 repeatedly to put described a plurality of same wafer A; At last, cut the stacking structure that described a plurality of wafer A forms a up-right type chip 3 again.Shown in Fig. 3 B, be provided with described wall 4 between each two adjacent described up-right type chip 3.The material of described wall 4 is preferably from epoxy resin, therefore described wall 4 epoxy resin layer preferably, but be not limited to this.
Please refer to shown in Fig. 4 A and the 4B, the three-dimensional exploded view of the encapsulating structure of the up-right type chip of its announcement first embodiment of the invention and encapsulation schematic diagram, the encapsulating structure of described up-right type chip comprises a support plate 5 and a up-right type chip 3, and described up-right type chip 3 is up-right type chip 3 structures that adopt as Fig. 2 A to 2C manufacturing.One side of described up-right type chip 3 is provided with a plurality of contacts 31, and a upper surface correspondence of described support plate 5 is provided with a plurality of weld pads 51, and described a plurality of weld pads 51 are arranged in a straight line.The described up-right type chip 3 of described support plate 5 carryings, and described a plurality of contact 31 electrically connects described a plurality of weld pads 51.Moreover a lower surface of described support plate 5 is provided with a plurality of projections 52, in order to electrically connect with an external device (ED) (not illustrating).
In first embodiment of the invention, described support plate 5 is base plate for packaging, for example printed circuit board (PCB) of single or multiple lift, ceramic circuit board or flexible electric circuit board etc., but be not limited to this.Above-mentioned base plate for packaging is applicable to the common packaging structure with substrate (substrate), for example chip encapsulation construction (BOC) etc. on baii grid array packaging structure (BGA), stitch grid array encapsulation structure (PGA), land grid array package structure (LGA) or the substrate; Described a plurality of contacts 31 of described up-right type chip 3 of the present invention can be to electrically connect described a plurality of weld pads 51 by a conducting resinl or scolder (solder).
In addition, the encapsulating structure of the up-right type chip of first embodiment of the invention comprises colloid 6 in addition, with the described up-right type chip 3 of support fixation in the upper surface of described support plate 5, described colloid 6 does not have the character of electrical conduction, it is preferably from general underfill (underfill), epoxy resin for example, but be not limited to this.
Shown in Fig. 4 B, described up-right type chip 3 is to be vertical on the described support plate 5, and the side that only has described contact 31 contacts with described support plate 5, and therefore the active surface of described up-right type chip 3 and the back side (not indicating) is directly to contact with air.Therefore, the present invention not only can save the area of the described up-right type chip 3 of described support plate 5 carryings, and can simplify the circuit design of described support plate 5, can increase the radiating efficiency of described up-right type chip 3 simultaneously relatively.
Please refer to shown in Figure 5, the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of its announcement second embodiment of the invention, wherein said encapsulating structure comprises a support plate 5 and a plurality of up-right type chip 3, one side of described each up-right type chip 3 is provided with a plurality of contacts 31, described support plate 5 correspondences are provided with a plurality of weld pads 51, described a plurality of up-right type chip 3 is spaced to be located on the described support plate 5, and the described a plurality of weld pads 51 of described a plurality of contact 31 electric connections, and described a plurality of weld pads 51 are rectangular arrangement.The lower surface of described support plate 5 is provided with a plurality of Metal Ball 52, tin ball for example, and it is in order to electrically connect with an external device (ED) (not illustrating).
As shown in Figure 5, described a plurality of up-right type chip 3 is to be vertical on the described support plate 5, the side that only has described contact 31 contacts with described support plate 5, and therefore the active surface of described up-right type chip 3 (not indicating) and the back side (not indicating) is directly to contact with air.Has a gap (not indicating) between each two adjacent described up-right type chip 3.Because described a plurality of up-right type chip 3 forms well-regulated arrangement mode, therefore can effectively utilize the confined space of described support plate 5 that a plurality of up-right type chips 3 are set, and can simplify the circuit design of described support plate 5, can increase the radiating efficiency of described up-right type chip 3 simultaneously relatively.In addition, the encapsulating structure of the up-right type chip of second embodiment of the invention comprises colloid 6 equally, with the described a plurality of up-right type chips 3 of support fixation on described support plate 5.In addition, owing to do not need the horizontal chip that stacks of level, so the present invention do not need described up-right type chip 3 is ground, so can reduce manufacturing cost and raising chip yields relatively.
Please refer to shown in Fig. 6 A and Fig. 6 B, the three-dimensional exploded view of the encapsulating structure of the up-right type chip of its announcement third embodiment of the present invention and encapsulation schematic diagram, the third embodiment of the present invention is similar in appearance to the second embodiment of the present invention, difference is: described a plurality of up-right type chips 3 are up-right type chip 3 structures that adopt as Fig. 2 A to 2C manufacturing, or, wherein has wall 4 between each two adjacent described up-right type chip 3 by stacking structure as the up-right type chip 3 of Fig. 3 A and 3B manufacturing.Because described a plurality of up-right type chip 3 is to form well-regulated arrangement mode, therefore can utilize the confined space of described support plate 5 a plurality of up-right type chips 3 effectively to be set in described support plate 5, the function of described a plurality of up-right type chip 3 can be identical or inequality, and can simplify the circuit design of described support plate 5.In addition, the active surface of outermost described up-right type chip 3 (not indicating) or the back side (not indicating) is directly to contact with air, therefore can increase the radiating efficiency of stacking structure relatively.In addition, owing to do not need the horizontal chip that stacks of level, so the present invention do not need described up-right type chip 3 is ground, so can reduce manufacturing cost and raising chip yields relatively.
Please refer to shown in Figure 7, the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of its announcement fourth embodiment of the present invention, the fourth embodiment of the present invention is similar in appearance to the third embodiment of the present invention, and difference is: described a plurality of up-right type chips 3 are to be located on the chip.Described encapsulating structure comprises one first support plate 7, one second support plate 5 and a plurality of up-right type chip 3, one side of described each up-right type chip 3 is provided with a plurality of contacts 31, described first support plate, 7 correspondences are provided with a plurality of weld pads 71, have wall 4 between each two adjacent described up-right type chip 3, described a plurality of up-right type chips 3 are arranged and are located on described first support plate 7.Described first support plate 7 in the present embodiment is chips.Described a plurality of contact 31 electrically connects described a plurality of weld pads 71, and described a plurality of weld pads 71 are rectangular arrangement and are formed on the active surface of described first support plate 7.Described first support plate 7 is located at again on described second support plate 5, described first support plate 7 electrically connects by a plurality of weld pads 51 of a plurality of connecting lines 72 with described second support plate 5, the lower surface of described second support plate 5 is provided with a plurality of Metal Ball 52, tin ball for example, it is in order to electrically connect with an external device (ED) (not illustrating).
As shown in Figure 7, the encapsulating structure of the up-right type chip of fourth embodiment of the invention comprises colloid 6 in addition, with the described a plurality of up-right type chips 3 of support fixation on described first support plate 7.In addition, described encapsulating structure also comprises an encapsulation 8, in order to coat described a plurality of up-right type chip 3 bottoms, described first support plate 7 and described connecting line 72 on described second support plate 5.Because described a plurality of up-right type chip 3 is to be carried on the chip, therefore can provide described a plurality of up-right type chip 3 to be packaged in the Combination Design diversity of a support plate.
Please refer to shown in Figure 8, the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of its announcement fifth embodiment of the present invention, the fifth embodiment of the present invention is similar in appearance to the third embodiment of the present invention, and difference is: described a plurality of up-right type chips 3 bottoms are to be located in one of described support plate 5 groove 53.Described encapsulating structure comprises a support plate 5 and a plurality of up-right type chip 3, one side of described each up-right type chip 3 is provided with a plurality of contacts 31, the corresponding described a plurality of up-right type chips 3 of the upper surface of described support plate 5 are provided with a groove 53, be provided with corresponding a plurality of weld pads 51 in the described groove 53, select between each two adjacent described up-right type chip 3 to have wall 4 or keep a gap, described a plurality of up-right type chip 3 is arranged and is located in the groove 53 of described support plate 52, described a plurality of contact 31 electrically connects described a plurality of weld pads 51, and described a plurality of weld pads 51 are rectangular arrangement.The lower surface of described support plate 5 is provided with a plurality of projections 52, in order to electrically connect with an external device (ED) (not illustrating).
As shown in Figure 8, the opening outer lip of the groove 53 of described a plurality of chips 3 bottoms and described support plate 52 is provided with colloid 6, the described a plurality of up-right type chips 3 of described colloid 6 support fixation.Because described a plurality of chip 3 bottoms are to be located in the groove 53 of stating support plate 52, therefore can improve the steadiness that described a plurality of up-right type chip 3 is packaged in a support plate.
Please refer to shown in Figure 9, the encapsulation schematic diagram of the encapsulating structure of the up-right type chip of its announcement sixth embodiment of the present invention, the sixth embodiment of the present invention is similar in appearance to the third embodiment of the present invention, and difference is: described a plurality of up-right type chips 3 are being located on the described support plate 5 of inclination.Described encapsulating structure comprises a support plate 5 and a plurality of up-right type chip 3, one side of described each up-right type chip 3 is provided with a plurality of contacts 31, the upper surface of described support plate 5 is established corresponding described a plurality of up-right type chips 3, described a plurality of up-right type chip 3, it is the adjacent arrangement of mode to tilt, be provided with a wall 4 ' between each described up-right type chip 3, described wall 4 ' is suitably bonding and form according to the design of the angle of inclination of described a plurality of up-right type chips 3, described a plurality of chip 3 bottoms and described support plate 5 are provided with colloid 6 ', a plurality of up-right type chips 3 of the described inclination of described colloid 6 ' support fixation.With respect to the upper surface of described support plate 5, the angle of inclination of described up-right type chip 3 is preferably between 45 degree are spent to 90.
As shown in Figure 9, described support plate 5 is provided with a plurality of weld pads 51 corresponding to described a plurality of contacts 31, is provided with a plurality of scolders 9 between described a plurality of contacts 31 and the described a plurality of weld pad 51, and described a plurality of scolders 9 electrically connect described a plurality of contacts 31 and described a plurality of weld pad 51.Because described a plurality of chip 3 is being located on the described support plate 52 of inclination, therefore can reduce the thickness that described a plurality of up-right type chip 3 is packaged in a support plate.
As mentioned above, the substrate encapsulation structure that existing chip stacks in Figure 1A to Fig. 1 D, it can't upwards stack too many chip, and its chip volume utilance of the also more past upper strata of the effect that stacks also reduces, chip cost more increases and connecting line designs defectives such as too complicated and easy fracture, the present invention is provided with described up-right type chip 3 among Fig. 2 A to 9 on described support plate 5, it can save the area of the described up-right type chip 3 of described support plate 5,7 carryings, also can effectively stack a plurality of up-right type chips 3 are set, and can simplify the circuit design of described support plate 5,7.In addition, the present invention also can provide combination diversity, steadiness that described up-right type chip is packaged in a support plate and the thickness that reduces described up-right type chip, and can improve the radiating efficiency of chip, and saves chip is carried out polish process.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is only for implementing example of the present invention.Must be pointed out that disclosed embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope is included in the scope of the present invention.
Claims (10)
1. the encapsulating structure of a up-right type chip, it is characterized in that: described encapsulating structure comprises: at least one up-right type chip, have a side, described side is provided with a plurality of contacts; And a support plate, having a upper surface, described upper surface carries described at least one up-right type chip, and described upper surface is provided with a plurality of weld pads, with a plurality of contacts of the side that electrically connects described up-right type chip.
2. the encapsulating structure of up-right type chip as claimed in claim 1, it is characterized in that: described at least one up-right type chip is two or above up-right type chip, has a gap between each two adjacent described up-right type chip.
3. the encapsulating structure of up-right type chip as claimed in claim 1, it is characterized in that: described at least one up-right type chip is two or above up-right type chip, is provided with a wall between each two adjacent described up-right type chip.
4. the encapsulating structure of up-right type chip as claimed in claim 3, it is characterized in that: described a plurality of walls are epoxy resin layers.
5. as the encapsulating structure of claim 1,2 or 3 described up-right type chips, it is characterized in that: described support plate is provided with a groove, and described groove is in order to the described up-right type chip of planting, and described weld pad is positioned at described groove.
6. as the encapsulating structure of claim 1,2 or 3 described up-right type chips, it is characterized in that: described encapsulating structure comprises colloid in addition, with the described up-right type chip of support fixation in described upper surface of said carrier plate.
7. as the encapsulating structure of claim 1 or 3 described up-right type chips, it is characterized in that: described a plurality of up-right type chips have an angle of inclination with respect to described support plate.
8. the encapsulating structure of up-right type chip as claimed in claim 1, it is characterized in that: described support plate is a base plate for packaging or a chip.
9. the encapsulating structure of up-right type chip as claimed in claim 1, it is characterized in that: the contact of described up-right type chip electrically connects the weld pad of described support plate by conducting resinl or scolder.
10. the encapsulating structure of up-right type chip as claimed in claim 1, it is characterized in that: a lower surface of described support plate more is provided with a plurality of Metal Ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910129703A CN101840893A (en) | 2009-03-19 | 2009-03-19 | Packaging structure of up-right type chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910129703A CN101840893A (en) | 2009-03-19 | 2009-03-19 | Packaging structure of up-right type chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101840893A true CN101840893A (en) | 2010-09-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910129703A Pending CN101840893A (en) | 2009-03-19 | 2009-03-19 | Packaging structure of up-right type chip |
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| Country | Link |
|---|---|
| CN (1) | CN101840893A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332462A (en) * | 2014-09-16 | 2015-02-04 | 山东华芯半导体有限公司 | Wafer-level package (WLP) unit with aslant stacked chips, and package method thereof |
| CN111968942A (en) * | 2020-08-24 | 2020-11-20 | 浙江集迈科微电子有限公司 | Interconnecting process for interconnecting radio frequency modules on side walls of adapter plates |
| US11482500B2 (en) * | 2018-02-27 | 2022-10-25 | Amkor Technology Singapore Holding Pte. Ltd. | Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures |
-
2009
- 2009-03-19 CN CN200910129703A patent/CN101840893A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332462A (en) * | 2014-09-16 | 2015-02-04 | 山东华芯半导体有限公司 | Wafer-level package (WLP) unit with aslant stacked chips, and package method thereof |
| CN104332462B (en) * | 2014-09-16 | 2017-06-20 | 山东华芯半导体有限公司 | A kind of chip inclines the wafer level packaging unit and its method for packing of stacking |
| US11482500B2 (en) * | 2018-02-27 | 2022-10-25 | Amkor Technology Singapore Holding Pte. Ltd. | Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures |
| CN111968942A (en) * | 2020-08-24 | 2020-11-20 | 浙江集迈科微电子有限公司 | Interconnecting process for interconnecting radio frequency modules on side walls of adapter plates |
| CN111968942B (en) * | 2020-08-24 | 2023-08-04 | 浙江集迈科微电子有限公司 | Interconnection technology for interconnecting radio frequency modules on side walls of adapter plates |
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