CN213482882U

CN213482882U - Core subsystem and module integrating DSP and FPGA

Info

Publication number: CN213482882U
Application number: CN202022916527.2U
Authority: CN
Inventors: 李卞俊; 王伟; 王秀涛
Original assignee: Nanjing Changfeng Space Electronics Technology Co Ltd
Current assignee: Nanjing Changfeng Space Electronics Technology Co Ltd
Priority date: 2020-12-08
Filing date: 2020-12-08
Publication date: 2021-06-18
Anticipated expiration: 2030-12-08

Abstract

The utility model discloses an integrated DSP and FPGA's core subsystem and module, a serial communication port, include: the device comprises a DSP unit, an FPGA unit, a DSP connector unit, an FPGA connector unit, a dynamic storage unit and a flash memory unit; the DSP unit and the FPGA unit are interconnected through EMIFA, uPP and I2C buses; the DSP connector unit comprises a network port, a serial port, a USB, a SATA, an EMIFA and an I2C interface which are used for data intercommunication between the DSP unit and external equipment; the FPGA connector unit comprises at least one of a single-ended input/output port or an LVDS interface for data intercommunication between the FPGA unit and external equipment; the dynamic storage unit is connected with the DSP unit; the flash memory unit is respectively connected with the DSP unit and the FPGA unit. The advantages are that: the utility model discloses integrated DSP and FPGA utilize FPGA to be used for realizing the extension of DSP bus and multichannel communication interface's extension interface, have integrated various interfaces, greatly reduced the development degree of difficulty and time.

Description

Core subsystem and module integrating DSP and FPGA

Technical Field

The utility model relates to an integrated DSP and FPGA core subsystem and module belongs to circuit technical field.

Background

The (digital signal processor) DSP is a high-performance processor, can meet the requirements of high energy efficiency and connectivity design, high integration level peripheral equipment, lower heat energy dissipation and longer service life of a battery, and the (field programmable logic device) FPGA can realize logic processing and interface expansion.

The currently used core sub-modules have many defects in the aspect of actual use, some of the defects are caused by the fact that the function of a system is not perfect due to pursuit of the small and exquisite core control card, and the peripheral circuit is complex during secondary development, so that the original design purpose is violated; some DSP single-core control cards are not satisfied for occasions with a large control requirement, so that a new scheme is urgently needed to solve the practical problem in the existing application.

Disclosure of Invention

The utility model aims to solve the technical problem that overcome prior art's defect, provide an integrated DSP and FPGA core subsystem and module.

In order to solve the technical problem, the utility model provides an integrated DSP and FPGA's core subsystem, include:

the device comprises a DSP unit, an FPGA unit, a DSP connector unit, an FPGA connector unit, a dynamic storage unit and a flash memory unit;

the DSP unit and the FPGA unit are interconnected through EMIFA, uPP and I2C buses;

the DSP unit is connected with the DSP connector unit, and the DSP connector unit comprises a network port, a serial port, a USB (universal serial bus), an SATA (serial advanced technology attachment), an EMIFA (enhanced authentication feature) and an I2C interface which are used for data intercommunication between the DSP unit and external equipment;

the FPGA unit is connected with the FPGA connector unit, and the FPGA connector unit comprises at least one of a single-ended input/output port or an LVDS interface for data intercommunication between the FPGA unit and external equipment;

the dynamic storage unit is connected with the DSP unit and is used for caching the running program of the DSP unit;

and the flash memory unit is respectively connected with the DSP unit and the FPGA unit and is used for storing data of the DSP unit and the FPGA unit.

Furthermore, the DSP unit and the FPGA unit are respectively connected with a storage unit by adopting SPI buses, and the storage unit is used for storing configuration data of the DSP unit or the FPGA unit.

Furthermore, the device also comprises a power supply unit which is used for respectively supplying power to the DSP unit and the FPGA unit.

A core submodule integrating a DSP and an FPGA comprises a circuit board, wherein the core subsystem is integrated on the circuit board.

Further, the DSP adopted by the DSP unit is TMS320C6748 fixed-point/floating-point DSP.

Further, the FPGA adopted by the FPGA unit is Spartan6 series FPGA.

Furthermore, the DSP connector unit and the FPGA connector unit both adopt ST5 series connectors.

Further, the dynamic memory unit adopts DDR2 memory; the flash memory cell is NAND FLASH.

Furthermore, the DSP unit and the FPGA unit are arranged in the middle of the circuit board, and the DSP connector unit, the FPGA connector unit, the dynamic storage unit and the flash memory unit are arranged on the outer sides of the DSP unit and the FPGA unit;

the DSP connector comprises a first connector CON1, and the FPGA connector unit comprises a second connector CON2, a third connector CON3, and a fourth connector CON 4;

the first connector CON1 is disposed on one of the four sides of the DSP unit near the edge of the circuit board, and the second connector CON2, the third connector CON3, and the fourth connector CON4 are disposed around the FPGA unit and disposed on the other three sides near the edge of the circuit board.

The utility model discloses the beneficial effect who reaches:

the utility model discloses integrated DSP and FPGA utilize FPGA to be used for realizing the extension of DSP bus and multichannel communication interface's expansion interface, provide high integration, support interfaces such as net gape, serial ports, USB, SATA, EMIFA and I2C, considered modularization and universalization demand, core control card module size is compact, and is multiple functional, secondary development and easy, greatly reduced development degree of difficulty and time cost shorten development cycle.

Drawings

Fig. 1 is a schematic diagram of the system and layout of the present invention.

Detailed Description

In order to make the objects, features and advantages of the present invention more obvious and understandable, the drawings in the embodiments of the present invention are combined below to clearly and completely describe the technical solutions in the embodiments of the present invention, and obviously, the embodiments described below are only some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

As shown in fig. 1, a core subsystem integrating a DSP and an FPGA includes:

the DSP unit and the FPGA unit are interconnected through an EMIFA (external memory interface), uPP and an I2C bus;

The DSP unit and the FPGA unit are respectively connected with a storage unit by adopting SPI buses, and the storage units are used for storing configuration data of the DSP unit or the FPGA unit. The storage unit adopts a W25Q64BV model, has a single capacity of 65Mb, adopts an SPI interface, is hung at a DSP end and an FPGA end, and can be used for storing configuration programs of the DSP and the FPGA or storing data.

The power supply unit is used for respectively supplying power to the DSP unit and the FPGA unit.

As shown in FIG. 1, the utility model also provides an integrated DSP and FPGA's core submodule piece, including the circuit board, the welding on the circuit board integrated DSP and FPGA's core subsystem.

The DSP units adopt TMS320C6748 fixed-point/floating-point DSP, 1.TI TMS320C6748 fixed-point/floating-point DSP, support DSP high-speed signal processing performance and reduced instruction computer (RISC) technology, and adopt a high-performance 456MHz TMS320C674x 32 bit processor.

The FPGA adopted by the FPGA unit is a Spartan6 series FPGA. Spartan-6 devices are based on well-established 45nm technology and can provide various industry-leading connection features, such as high logic pin ratio, small package size, and a wide variety of I/O protocol support. In the system, the FPGA is used for realizing the expansion of a DSP bus and the expansion of a multi-channel communication interface and meeting the requirements of simple algorithm and logic processing.

And the DSP connector unit and the FPGA connector unit both adopt ST5 series connectors.

The dynamic memory unit adopts DDR2 memory; the flash memory cell is NAND FLASH.

The DSP unit and the FPGA unit are arranged in the middle of the circuit board, and the DSP connector unit, the FPGA connector unit, the dynamic storage unit and the flash memory unit are arranged on the outer sides of the DSP unit and the FPGA unit;

The DDR2 adopts a MT47H64M16HR-3EIT model of Micron company, the capacity of a single particle is 1Gb, the data Bit width is 16Bit, and the rate is as high as 667 MT/s;

NAND FLASH adopts MT29F4G16ABADAH4 model D of Micron company, single grain capacity 4Gb, data Bit width 16Bit, the chip is hung at the DSP end and can be used for storing the configuration program of DSP or storing data;

the ST5 series connector of SAMTEC is 4mm high, a 100pin connector is selected, the series connector is a high-density and high-speed type electric connector, high-speed data transmission between boards is realized, and the transmission rate reaches 56 Gb/s.

The integrated DSP and FPGA core submodule use DSP as a main control chip, FPGA is used as an interface expansion chip, the DSP and the FPGA are interconnected through EMIFA, uPP and I2C, the DSP external interface is on CON1 and comprises a network port, a serial port, USB, SATA, EMIFA and I2C interfaces, the network port, the serial port and the USB can be used as external communication interfaces, the core submodule integrates a driving chip of the network port and the serial port, and the network port can be directly connected to a joint during secondary development; SATA can mount SATA disks for mass storage, EMIFA and I2C can mount other peripherals; the FPGA external interfaces are CON2, CON3 and CON4, and 90 are single-ended input/output ports, and 82 are LVDS, all of which can have 254-bit input/output ports as single-ended signals.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims

1. A core subsystem integrating a DSP and an FPGA, comprising:

2. The core subsystem according to claim 1, wherein the DSP unit and the FPGA unit are respectively connected to a storage unit by using SPI buses, and the storage unit is configured to store configuration data of the DSP unit or the FPGA unit.

3. The core subsystem of claim 1, further comprising a power supply unit for respectively powering the DSP unit and the FPGA unit.

4. A core submodule integrating a DSP and an FPGA, comprising a circuit board, wherein the core subsystem of any of claims 1-3 is integrated on the circuit board.

5. The core submodule according to claim 4, wherein the DSP used by the DSP unit is a TMS320C6748 fixed point/floating point DSP.

6. The core submodule according to claim 4, wherein the FPGA adopted by the FPGA unit is a Spartan6 series FPGA.

7. The core submodule according to claim 4, wherein the DSP connector unit and the FPGA connector unit are both ST5 series connectors.

8. The core submodule according to claim 4, wherein the dynamic memory unit employs DDR2 memory; the flash memory cell is NAND FLASH.

9. The core submodule according to claim 4, wherein the DSP unit and the FPGA unit are arranged in the middle of the circuit board, and the DSP connector unit, the FPGA connector unit, the dynamic storage unit and the flash memory unit are arranged outside the DSP unit and the FPGA unit;