CN213426115U - Signal processing device - Google Patents
Signal processing device Download PDFInfo
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- CN213426115U CN213426115U CN202022395645.3U CN202022395645U CN213426115U CN 213426115 U CN213426115 U CN 213426115U CN 202022395645 U CN202022395645 U CN 202022395645U CN 213426115 U CN213426115 U CN 213426115U
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Abstract
The utility model discloses a signal processing device, including processing module, set up a N first adjustable resistance between each input of processing module and ground and set up a M second adjustable resistance between each output of processing module and ground, the user can adjust the impedance value that each first adjustable resistance and each second adjustable resistance go on based on the quantity that needs input signal's quantity and needs output signal's quantity demand, thereby control processing module's input signal and output signal's quantity, processing module closes it or handles along separate routes based on input signal, in order to satisfy user's demand. Therefore, the signal processing device in the application can realize not only one-to-four shunting, but also three-to-four shunting by adjusting the impedance values of the first adjustable resistors and the second adjustable resistors, thereby meeting various requirements of users and reducing the cost.
Description
Technical Field
The utility model relates to a signal processing field especially relates to a signal processing device.
Background
In practical applications, when there are fewer input signal lines and more required output signal lines, for example, when there is only one input signal line and there are multiple output signals, a splitter is required to split the input signal of only one input signal line, that is, the power of the input signal is divided equally and output through the output signal lines respectively; when there are many input signal lines and/or communication systems and there are few lines requiring output signals, for example, when the input signals are multiple paths and the output signals only need one path, a combiner is required to combine the multiple input signals, combine the multiple input signals into one path, and output the path through the one path output signal line.
In the prior art, a plurality of combiners and splitters are designed by using microstrip lines, for example, a one-to-four circuit, a three-to-four circuit, and the like, wherein an input end and an output end of the one-to-four circuit can be used as a four-in-one circuit when being interchanged. In addition, each circuit board is arranged in the repeater, when the input of the circuit board is multipath and signals of multiple communication systems can be input at the same time, the repeater is a multimode repeater, and a plurality of circuit boards can be arranged in the multimode repeater, so that the signal splitting and combining processing of a single line and/or a plurality of lines can be realized. However, the circuit board has a large volume and a large number, which increases the pressure in the multimode repeater and increases the cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a signal processing device, through the adjustment to each first adjustable resistance and each second adjustable resistance's impedance value, can not only realize for example one divide four shunts, can also realize three divide four shunts, has satisfied user's multiple demand, the cost is reduced.
In order to solve the above technical problem, the utility model provides a signal processing device, include:
the processing modules are used for carrying out combination or shunt processing on input signals, and N and M are integers not less than 1;
the first ends of the N first adjustable resistors are respectively connected with the input ends of the processing module in a one-to-one corresponding mode, the second ends of the N first adjustable resistors are grounded, the N first adjustable resistors are used for adjusting the impedance value of the N first adjustable resistors to infinity after receiving a first instruction so as to enable the input ends to normally input signals, and adjusting the impedance value of the N first adjustable resistors to be a preset impedance value after receiving a second instruction so as to absorb signals flowing through the corresponding input ends;
each first end respectively with each output one-to-one of processing module is connected, and M second adjustable resistance of second end ground connection for adjust self impedance value to infinity after receiving the third instruction, so that the output is normal output signal, adjusts self impedance value after receiving the fourth instruction and to predetermine impedance value, in order to absorb the signal that self corresponding output flowed through.
Preferably, the processing module comprises:
the input ends of the first processing modules are respectively used as the input ends of the processing modules and used for combining the input signals;
the input end of the first processing module is connected with the output end of the first processing module, and the output end of the first processing module is respectively used as a second processing module of each output end of the processing module and used for carrying out shunt processing on input signals.
Preferably, the first processing module and the second processing module are both combiner/splitter chips.
Preferably, the method further comprises the following steps:
the first switch is used for switching off when only one path of input signals exists;
the first switch is connected with the first end of the first switch, and the second switch is connected with the input end of the second processing module and used for being closed when the first switch is opened;
and the third switch is used for being disconnected when the second switch is closed.
Preferably, the method further comprises the following steps:
and the fourth switch is used for being closed when the second switch is closed and being disconnected when the second switch is disconnected.
Preferably, the ith switch is an ith adjustable resistance switch, the ith switch is in a closed state when the impedance value of the ith adjustable resistance switch is 0, the ith switch is in an open state when the impedance value of the ith adjustable resistance switch is infinite, and i is any one of a value from one to four.
Preferably, the first adjustable resistor comprises:
the first controllable switch with a first end serving as the first end of the first adjustable resistor is used for being switched off after receiving the first instruction and being switched on after receiving the second instruction;
the first end is connected with the second end of the first controllable switch, the second end is grounded, and the first resistor with the impedance value of the preset impedance value is used for absorbing signals flowing through the input end when the first controllable switch is closed.
Preferably, the first resistor is a resistor having an impedance value of 50 ohms.
Preferably, the second adjustable resistor comprises:
the first end of the second controllable switch is used as the first end of the second adjustable resistor, and the second controllable switch is used for being switched off after receiving the third instruction and is switched on after receiving the fourth instruction;
the first end is connected with the second end of the second controllable switch, the second end is grounded, and the second resistor with the impedance value of the preset impedance value is used for absorbing signals flowing through the output end when the second controllable switch is closed.
Preferably, the second resistor is a resistor having an impedance value of 50 ohms.
The utility model provides a signal processing device, including processing module, set up a N first adjustable resistance between each input of processing module and ground and set up a M second adjustable resistance between each output of processing module and ground, the user can adjust the impedance value that each first adjustable resistance and each second adjustable resistance go on based on the quantity that needs input signal's quantity and needs output signal's quantity demand, thereby control processing module's input signal and output signal's quantity, processing module closes it or handles along separate routes based on input signal, in order to satisfy user's demand. Therefore, the signal processing device in the application can realize not only one-to-four shunting, but also three-to-four shunting by adjusting the impedance values of the first adjustable resistors and the second adjustable resistors, thereby meeting various requirements of users and reducing the cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a signal processing apparatus provided by the present invention;
fig. 2 is a schematic structural diagram of a signal processing apparatus with dual processing modules according to the present invention;
fig. 3 is a schematic structural diagram of a specific signal processing apparatus provided by the present invention;
fig. 4 is a schematic diagram of an example of a signal processing apparatus provided by the present invention.
Detailed Description
The core of the utility model is to provide a signal processing device, through the adjustment to each first adjustable resistance and each second adjustable resistance's impedance value, can not only realize for example one minute four shunts, can also realize three minutes four shunts, satisfied user's multiple demand, the cost is reduced.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a signal processing apparatus according to the present invention.
The device includes:
the processing modules 1 are provided with N input ends and M output ends and used for performing combination or shunt processing on input signals, wherein both N and M are integers not less than 1;
the N first adjustable resistors R11 with grounded second ends are used for adjusting the impedance value of the input end to infinity after receiving the first instruction, so that the input end inputs a signal normally, and adjusting the impedance value of the input end to a preset impedance value after receiving the second instruction, so as to absorb a signal flowing through the input end corresponding to the input end;
each first end is connected with each output end of the processing module 1 in a one-to-one correspondence manner, and the M second adjustable resistors R12, of which the second ends are grounded, are used for adjusting the impedance value of the resistors themselves to infinity after receiving the third instruction, so that the output ends normally output signals, and adjusting the impedance value of the resistors themselves to the preset impedance value after receiving the fourth instruction, so as to absorb signals flowing through the corresponding output ends.
In the prior art, when signals are combined or split processed, for example, a one-to-four circuit and a three-to-four circuit are respectively designed, wherein the input end and the output end of the one-to-four circuit are exchanged to realize the four-in-one processing of the signals, but because the structures of the one-to-four circuit and the three-to-four circuit are different, a plurality of circuits are required to be designed to realize the one-to-four processing and the three-to-four processing of the signals, the period for designing the plurality of circuits is long, two years is short, and three years is long. Because each circuit is arranged in the repeater, in order to enable the repeater to realize one-to-four processing and three-to-four processing of signals, a plurality of circuits are required to be arranged in the repeater, so that the space pressure inside the repeater is increased, and the cost is increased.
In order to reduce the space pressure inside the repeater, the processing module 1 is adopted to combine and divide signals, the input end and the output end of the processing module 1 are respectively provided with the first adjustable resistor R11 and the second adjustable resistor R12, and the number of the input end and the output end of the processing module 1 can be controlled by controlling the impedance values of the first adjustable resistor R11 and the second adjustable resistor R12 through the first instruction and the second instruction, wherein when the impedance value of the first adjustable resistor R11 is adjusted to be infinite, the corresponding input end can normally input signals; when the impedance value of the first adjustable resistor R11 is adjusted to the preset impedance value, the first adjustable resistor R11 may absorb the signal input from the port corresponding to the first adjustable resistor R11, so that the port corresponding to the threshold value cannot input the signal to the processing module 1. Similarly, when the impedance value of the second adjustable resistor R12 is adjusted to infinity, the corresponding output terminal can normally output a signal; when the impedance value of the second adjustable resistor R12 is adjusted to the preset impedance value, the second adjustable resistor R12 can absorb the signal output by the port corresponding to the second adjustable resistor R12, so that the port corresponding to the threshold value cannot output the signal. Therefore, the present application can realize both the one-to-four processing and the three-to-four processing of the signal, and the four-in-one processing of the signal, for example, by controlling the impedance values of the first adjustable resistor R11 and the second adjustable resistor R12.
In addition, the number of signals input into the processing module 1 may be controlled based on the adjustment of the impedance value of the first adjustable resistor R11, the number of signals input into the processing module 1 may be one or more, the communication systems of a plurality of signals may be the same or different, and the communication system of each signal may be 2G, 3G, 4G or 5G, which is not limited in this application.
Because the number of the signals input into the processing module 1 may be one or more, and the communication systems of the multiple signals may be the same or different, when the processing module 1 performs combining or splitting processing on the multiple input signals, for example, each input signal is combined into one path first, and then the power of the input signal is evenly distributed, so that the signal with the evenly distributed power is output from each output terminal, because the user can control whether the output terminal can output the signal or not based on the adjustment of the impedance value of the second adjustable resistor R12, through the control of the user, the output signal is absorbed by the second adjustable resistor R12 when passing through the output terminal which cannot output the signal, so as to meet the requirement of the user on the number of the output signals. When a user needs to combine the input signals, only one path of output end is reserved, and the combination processing of the input signals can be realized; when a user needs to output multiple paths of signals, the second adjustable resistors R12 of other output ends are adjusted to be preset electrical impedance values.
In the present application, the first command, the second command, the third command, and the fourth command are not limited to electric signals, and the impedance values of the first adjustable resistor and the second adjustable resistor may be adjusted.
In addition, the selectable impedance value of the first adjustable resistor is a preset impedance value or an infinite impedance value; the selectable impedance value of the second adjustable resistor is a preset impedance value or an infinite impedance value.
In summary, the signal processing apparatus in the present application can not only realize, for example, a four-in-one shunt, but also a four-in-one shunt by adjusting the impedance values of each of the first adjustable resistors R11 and each of the second adjustable resistors R12, thereby satisfying various requirements of users and reducing the cost.
On the basis of the above-described embodiment:
as shown in fig. 2, fig. 2 is a schematic structural diagram of a signal processing apparatus with dual processing modules according to the present invention.
As a preferred embodiment, the processing module 1 comprises:
the input ends of the first processing modules 11 are respectively used as the input ends of the processing modules 1, and are used for performing combination processing on input signals;
the input end of the second processing module 12 is connected to the output end of the first processing module 11, and the output ends of the second processing module are respectively used as the output ends of the processing modules 1, so as to perform shunt processing on the input signals.
In order to facilitate combining or splitting processing of the input signals, the present application provides two processing modules, as shown in fig. 2, where a first processing module 11 first performs combining processing on the input signals, for example, when there is only one input signal, the input signals are directly output; when the input signals are multi-path, the multi-path input signals are combined, that is, the multi-path input signals are combined into one path of signal to be output. After receiving the signal of the same path output by the first processing module 11, the second processing module 12 directly equally divides the power of the signal of the same path, so that the signal after the power is equally divided is output by each output end, and a user can control the number of output signals by controlling the impedance value of each second adjustable resistor R12, thereby facilitating the processing of the signal.
As a preferred embodiment, the first processing module 11 and the second processing module 12 are both a combining/splitting chip.
The splitting circuit and the combining circuit in the prior art cannot well process a wide range of frequency bands between 700M-3G in signals, that is, indexes of each port are different, and results of signal processing for different frequency bands are different, specifically, when signal frequency bands input by each input end are exchanged, frequencies of output signals are different, for example, a frequency of an input signal at a first input end is 2G, a frequency of an input signal at a second input end is 3G, and a frequency of an input signal at a first input end is 3G, and a frequency of an input signal at a second input end is 2G. The indicators of each output end include, for example: the input standing wave, the output standing wave, and the insertion loss are not limited in this application. In order to meet the requirements of users, in the prior art, each input end corresponds to the frequency band of an input signal one by one, and the complexity of debugging is increased.
In order to solve the above technical problems, the present application adopts a combining/splitting chip as the first processing module 11 and the second processing module 12, the combining/splitting chip can not only realize splitting and combining processing of signals, but also has better indexes, each input end does not need to correspond to the frequency band of each signal one by one, and the output signals can both meet the requirements of users no matter how the frequency band of the signals input by each input end is, thereby facilitating debugging and installation of users.
In addition, the combining/splitting chip also has the characteristic of small volume, thereby effectively reducing the volume of the repeater and reducing the cost.
As a preferred embodiment, the method further comprises the following steps:
a first switch K1, having a first end as a signal input end and a second end connected to the first input end of the first processing module 11, for switching off when there is only one path of input signal;
a second switch K2 having a first terminal connected to the first terminal of the first switch K1 and a second terminal connected to the input terminal of the second processing module 12, and configured to be closed when the first switch K1 is open;
and a third switch K3 having a first terminal connected to the output terminal of the first processing module 11 and a second terminal connected to the input terminal of the second processing module 12, for being opened when the second switch K2 is closed.
Considering that when the input signal is only one path and the output signal of the first processing module 11 is also only one path, the present application directly inputs an input signal of one path into the second processing module 12, specifically, as shown in fig. 3, fig. 3 is a schematic structural diagram of a specific signal processing apparatus provided by the present invention, in which the first input terminal of the first processing module 11 is disconnected from the first processing module 11 by the first switch K1, the output terminal of the first processing module 11 is disconnected from the input terminal of the second processing module 12 by the third switch K3, the first input terminal of the processing module 1 of the first processing module 11 is directly connected to the input terminal of the second processing module 12 by the second switch K2, so that the input signal is directly input into the second processing module 12, and the processing module 1 of the second processing module 12 divides the power of the input signal, thereby realizing the shunt processing of the input signal.
In addition, when the input signals are multiplexed, the first switch K1 is in a closed state, the second switch K2 is in an open state, and the third switch K3 is in a closed state.
As shown in fig. 4, fig. 4 is a schematic diagram of an example of a signal processing apparatus provided by the present invention. In the figure, the first processing module 11 has four input terminals, the second processing module 12 has four output terminals, and when the first switch K1 and the third switch K3 are closed and the second switch K2 and the fourth switch K4 are open, and the resistance value of the first adjustable resistor R11 connected to one of the input terminals is a preset impedance value, the number of ports capable of inputting signals is three, that is, the circuit is a divide-by-four circuit; when the first switch K1 and the third switch K3 are turned off and the second switch K2 and the fourth switch K4 are turned on, there is only one input terminal and the input signal is inputted into the second processing module 12, i.e. the circuit is a one-to-four circuit. Similarly, the control of different inputs and outputs is realized by controlling the first adjustable resistor R11, the second adjustable resistor R12, the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4.
In summary, in the present application, one input signal is directly input to the second processing module 12, so that the time for the first processing module 11 to process one input signal is saved.
As a preferred embodiment, the method further comprises the following steps:
and a fourth switch K4, having a first terminal connected to the second terminal of the second switch K2 and a second terminal connected to the input terminal of the second processing module 12, and configured to be closed when the second switch K2 is closed and open when the second switch K2 is open.
In the present application, considering that when the second switch K2 is closed, the second end of the second switch K2 is connected to the input end of the second processing module 12 through a microstrip line, but the impedance of the microstrip line may affect the input signal, therefore, the fourth switch K4 is further connected between the second end of the second switch K2 and the second processing module 12, so that the influence of the impedance of the microstrip line on the input signal is reduced.
As a preferred embodiment, the ith switch is an ith adjustable resistance switch, the ith switch is in a closed state when the impedance value of the ith adjustable resistance switch is 0, the ith switch is in an open state when the impedance value of the ith adjustable resistance switch is infinity, and i is any one of one to four.
In the present application, a first adjustable resistance switch, a second adjustable resistance switch, a third adjustable resistance switch, and a fourth adjustable resistance switch are respectively used as a first switch K1, a second switch K2, a third switch K3, and a fourth switch K4, and when the impedance value of each adjustable resistance switch is infinite, each switch is in an off state; when the impedance value of each adjustable resistance switch is 0, each switch is in a closed state. The impedance values of the first adjustable resistance switch, the second adjustable resistance switch, the third adjustable resistance switch and the fourth adjustable resistance switch are controlled respectively, so that the states of the corresponding first switch K1, the second switch K2, the third switch K3 and the fourth switch K4 are controlled respectively, and the operation by a user is facilitated.
As a preferred embodiment, the first adjustable resistor R11 includes:
the first controllable switch with a first end serving as a first end of the first adjustable resistor R11 is used for being opened after receiving a first instruction and being closed after receiving a second instruction;
the first end is connected with the second end of the first controllable switch, the second end is grounded, and the first resistor with the impedance value of a preset impedance value is used for absorbing signals flowing through the input end when the first controllable switch is closed.
In this application, connect first controllable switch and first resistance, as first adjustable resistance R11, control first controllable switch's state through first instruction and second instruction to whether the realization is controlled the input signal that corresponds with it. When the first controllable switch is turned off, that is, the impedance value of the first adjustable resistor R11 is the preset impedance value, the first resistor can absorb the input signal of the input terminal corresponding to the first resistor, so that the input signal cannot be input to the input terminal, and thus the number of the input signals is controlled, and the operation by a user is facilitated.
As a preferred embodiment, the first resistor is a resistor having a resistance value of 50 ohms.
In the present application, it is considered that the first resistor needs to absorb a signal of the corresponding input terminal, and therefore, the first resistor has a resistance value of 50 ohms, where 50 ohms is a resistance value capable of absorbing a signal and is a minimum resistance value of signal reflection, and is a resistance value at which a signal does not mismatch.
In addition, the first resistor is not limited to a resistor with a resistance value of 50 ohms, and whether a signal is input to the input end or not may be controlled.
As a preferred embodiment, the second adjustable resistor R12 includes:
the first end of the second controllable switch is used as the first end of the second adjustable resistor R12, and the second controllable switch is used for being opened after receiving a third instruction and being closed after receiving a fourth instruction;
the first end is connected with the second end of the second controllable switch, the second end is grounded, and the second resistor with the impedance value of the preset impedance value is used for absorbing signals flowing through the output end when the second controllable switch is closed.
In this application, connect second controllable switch and second resistance, as second adjustable resistance R12, control second controllable switch's state through third instruction and fourth instruction to whether the realization is controlled the output signal that corresponds with it. When the second controllable switch is turned off, that is, the impedance value of the second adjustable resistor R12 is the preset impedance value, the second resistor can absorb the output signal of the output terminal corresponding to the second adjustable resistor R12, so that the output terminal cannot output the signal, thereby controlling the number of the output signals and facilitating the user operation.
In a preferred embodiment, the second resistor has a resistance value of 50 ohms.
In the present application, the second resistor needs to absorb a signal at an output terminal corresponding to the second resistor, and therefore, the second resistor has a resistance value of 50 ohms, where 50 ohms is a resistance value capable of absorbing a signal and is a minimum resistance value of signal reflection, and is a resistance value at which a signal does not mismatch.
In addition, the second resistor is not limited to a resistor with a resistance value of 50 ohms, and whether the output signal is output from the output terminal or not can be controlled.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A signal processing apparatus, characterized by comprising:
the processing modules are used for carrying out combination or shunt processing on input signals, and N and M are integers not less than 1;
the first ends of the N first adjustable resistors are respectively connected with the input ends of the processing module in a one-to-one corresponding mode, the second ends of the N first adjustable resistors are grounded, the N first adjustable resistors are used for adjusting the impedance value of the N first adjustable resistors to infinity after receiving a first instruction so as to enable the input ends to normally input signals, and adjusting the impedance value of the N first adjustable resistors to be a preset impedance value after receiving a second instruction so as to absorb signals flowing through the corresponding input ends;
each first end respectively with each output one-to-one of processing module is connected, and M second adjustable resistance of second end ground connection for adjust self impedance value to infinity after receiving the third instruction, so that the output is normal output signal, adjusts self impedance value after receiving the fourth instruction and to predetermine impedance value, in order to absorb the signal that self corresponding output flowed through.
2. The signal processing apparatus of claim 1, wherein the processing module comprises:
the input ends of the first processing modules are respectively used as the input ends of the processing modules and used for combining the input signals;
the input end of the first processing module is connected with the output end of the first processing module, and the output end of the first processing module is respectively used as a second processing module of each output end of the processing module and used for carrying out shunt processing on input signals.
3. The signal processing apparatus of claim 2, wherein the first processing module and the second processing module are each a combiner/divider chip.
4. The signal processing apparatus of claim 2, further comprising:
the first switch is used for switching off when only one path of input signals exists;
the first switch is connected with the first end of the first switch, and the second switch is connected with the input end of the second processing module and used for being closed when the first switch is opened;
and the third switch is used for being disconnected when the second switch is closed.
5. The signal processing apparatus of claim 4, further comprising:
and the fourth switch is used for being closed when the second switch is closed and being disconnected when the second switch is disconnected.
6. The signal processing apparatus of claim 5, wherein the ith switch is an ith adjustable resistance switch, the ith switch is in a closed state when the impedance value of the ith adjustable resistance switch is 0, the ith switch is in an open state when the impedance value of the ith adjustable resistance switch is infinite, and i is any one of one to four.
7. The signal processing apparatus of any of claims 1 to 6, wherein the first adjustable resistance comprises:
the first controllable switch with a first end serving as the first end of the first adjustable resistor is used for being switched off after receiving the first instruction and being switched on after receiving the second instruction;
the first end is connected with the second end of the first controllable switch, the second end is grounded, and the first resistor with the impedance value of the preset impedance value is used for absorbing signals flowing through the input end when the first controllable switch is closed.
8. The signal processing apparatus of claim 7, wherein the first resistor is a resistor having an impedance value of 50 ohms.
9. The signal processing apparatus of any of claims 1 to 6, wherein the second adjustable resistance comprises:
the first end of the second controllable switch is used as the first end of the second adjustable resistor, and the second controllable switch is used for being switched off after receiving the third instruction and is switched on after receiving the fourth instruction;
the first end is connected with the second end of the second controllable switch, the second end is grounded, and the second resistor with the impedance value of the preset impedance value is used for absorbing signals flowing through the output end when the second controllable switch is closed.
10. The signal processing apparatus of claim 9, wherein the second resistor is a resistor having an impedance value of 50 ohms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022395645.3U CN213426115U (en) | 2020-10-23 | 2020-10-23 | Signal processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022395645.3U CN213426115U (en) | 2020-10-23 | 2020-10-23 | Signal processing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213426115U true CN213426115U (en) | 2021-06-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022395645.3U Expired - Fee Related CN213426115U (en) | 2020-10-23 | 2020-10-23 | Signal processing device |
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| Country | Link |
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| CN (1) | CN213426115U (en) |
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2020
- 2020-10-23 CN CN202022395645.3U patent/CN213426115U/en not_active Expired - Fee Related
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Granted publication date: 20210611 Termination date: 20211023 |