CN213338366U - Standby wake-up circuit and intelligent device - Google Patents
Standby wake-up circuit and intelligent device Download PDFInfo
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- CN213338366U CN213338366U CN202022139315.8U CN202022139315U CN213338366U CN 213338366 U CN213338366 U CN 213338366U CN 202022139315 U CN202022139315 U CN 202022139315U CN 213338366 U CN213338366 U CN 213338366U
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Abstract
The utility model relates to a standby wake-up circuit and intelligent equipment, wherein the first control signal output end of the second processor is connected with the first processor, the second control signal output end of the second processor is connected with the third processor, and the control signal output end of the first processor is connected with the control end of the first electronic switch device; and the standby power consumption of the first processor is lower than the standby power consumption of the second processor. When the standby signal is received, the second processor controls all the peripheral equipment to be turned off, and sends a control signal to the third processor to control the second electronic switch equipment to be turned off, so that the corresponding peripheral equipment is turned off, and then sends another control signal to the first processor to control the electronic switch equipment to be turned off, so that the power supply to the second processor and the third processor is turned off, so that the power supply of all the peripheral equipment is turned off, and only the first processor with extremely low standby power consumption is maintained to supply power, so that the low power consumption state of the whole equipment is realized, the low power consumption requirement is met, and the electric energy is saved.
Description
Technical Field
The utility model relates to a standby awakening circuit and smart machine belongs to the power control field.
Background
At present, some household intelligent devices such as televisions, television boxes, projectors and the like have increasingly high requirements on standby power consumption, a common processing scheme for reducing the power consumption is to control a main control CPU chip of each peripheral to enter a low-power-consumption sleep mode, and although the power consumption of the main control CPU is low in the sleep mode, certain standby power consumption still exists, and the current requirement on extremely low standby power consumption cannot be met.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that needs to solve is the problem that the unsatisfied low-power consumption of consumption required when overcoming current smart machine standby.
The utility model provides a standby wake-up circuit, which is characterized in that the standby wake-up circuit comprises a signal trigger device, a first processor, a second processor, an electronic switch device and a power management device;
the output end of the signal trigger equipment is simultaneously connected with the first processor and the second processor;
the control end of the first processor is connected with the control signal output end of the second processor, and the control signal output end of the first processor is connected with the control end of the electronic switch device;
the input end of a switch of the electronic switch equipment is connected with a power supply, and the output end of the switch of the electronic switch equipment is connected with the power supply management equipment, so that the power supply supplies power to the power supply management equipment through the switch; the power supply output end of the power supply management equipment is connected with the second processor, so that the power supply management equipment outputs a power supply to supply power to the second processor;
the standby power consumption of the first processor is lower than the standby power consumption of the second processor.
Optionally, the electronic switching device includes a second NMOS transistor, a first PMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor;
one end of the seventh resistor is a control end of the electronic switching device, the other end of the seventh resistor is connected with a grid electrode of the second NMOS tube, a source electrode of the second NMOS tube is grounded, and a drain electrode of the second NMOS tube is commonly connected with one end of the fifth resistor and one end of the sixth resistor;
the other end of the fifth resistor and the drain electrode of the first PMOS tube are connected to the input end of the electronic switching device in a sharing mode, the source electrode of the first PMOS tube is the output end of the electronic switching device, and the grid electrode of the first PMOS tube is connected with the other end of the sixth resistor.
Optionally, the electronic switching device includes a second NPN triode, a first PMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor;
one end of the seventh resistor is a control end of the electronic switching device, the other end of the seventh resistor is connected with a base electrode of the second NPN triode, an emitting electrode of the second NPN triode is grounded, and a collector electrode of the second NPN triode is commonly connected with one end of the fifth resistor and one end of the sixth resistor;
the other end of the fifth resistor and the drain electrode of the first PMOS tube are connected to the input end of the electronic switching device in a sharing mode, the source electrode of the first PMOS tube is the output end of the electronic switching device, and the grid electrode of the first PMOS tube is connected with the other end of the sixth resistor.
Optionally, the standby wake-up circuit further includes a sixth capacitor, and the sixth capacitor is connected in parallel to the gate and the drain of the first PMOS transistor.
Optionally, the standby wake-up circuit further comprises a third electronic switching device,
a second control signal output end of the third processor is connected with a control end of the third electronic switch device;
and/or further comprising a fourth electronic switching device,
and a third control signal output end of the third processor is connected with a control end of the fourth electronic switching device.
Optionally, the standby wake-up circuit further includes a voltage conversion device, and the voltage conversion device is configured to step down the voltage at the input point and then supply power to the first processor.
Optionally, the signal triggering device is an infrared receiving device or a key device.
Optionally, the infrared receiving device includes an infrared receiving head, a third diode and a fourth diode;
the output end of the infrared receiving head is connected to the cathode of the third diode and the cathode of the fourth diode in common;
the anode of the third diode and the anode of the fourth diode are two output ends of the infrared receiving device respectively.
Optionally, the infrared receiving device further includes a first electrostatic diode and a second electrostatic diode;
the positive end of the power supply of the infrared receiving head and the output end of the infrared receiving head are connected in parallel with the first electrostatic diode and the second electrostatic diode respectively in a ground connection mode.
The utility model discloses still provide an intelligent equipment, set up foretell standby wake-up circuit on intelligent equipment's the control circuit board, intelligent equipment is one in TV box, TV set, the projecting apparatus.
Adopt the utility model discloses a standby wake-up circuit, it includes signal trigger equipment, first treater, second treater, third treater, first electronic switch device and second electronic switch device, wherein the first control signal output end of second treater connects the first treater, the second control signal output end of second treater connects the third treater, the control signal output end of first treater connects the control end of first electronic switch device; and the standby power consumption of the first processor is lower than the standby power consumption of the second processor. Therefore, when the standby signal is received, the second processor controls all the peripheral equipment to be closed, and sends a control signal to the third processor to control the second electronic switch equipment to be closed, so that the corresponding peripheral equipment is closed, then another control signal is sent to the first processor, the first processor controls the electronic switch equipment to be disconnected, so that the power supply to the second processor and the third processor is disconnected, the power supply of all the peripheral equipment is disconnected, and only the first processor with extremely low standby power consumption is maintained to supply power, so that the low power consumption state of the whole equipment is realized, the low power consumption requirement is met, and the electric energy is saved.
Drawings
Fig. 1 is a block diagram of a standby wake-up circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a standby wake-up circuit according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a standby wake-up circuit according to another embodiment of the present invention;
fig. 4 is a circuit diagram of a voltage converting device of a standby wake-up circuit according to another embodiment of the present invention;
fig. 5 is a flowchart of a control method for power management according to an embodiment of the present invention;
fig. 6 is a flowchart of a control method for power management according to another embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to examples.
The utility model provides a standby wake-up circuit, as shown in fig. 1, the standby wake-up circuit includes a signal trigger device 10, a first processor 20, a second processor 30, a third processor 50, a first electronic switch device 40 and a second electronic switch device 60;
wherein the output terminal of the signal triggering device 10 is connected to the first processor 20 and the second processor 30 at the same time;
a first control signal output end of the second processor 30 is connected to the first processor 20, and a second control signal output end of the second processor 30 is connected to the third processor 50;
a control signal output end of the first processor 20 is connected with a control end of the first electronic switching device 40, an input end of a switch of the first electronic switching device 40 is connected with a power supply, and an output end of the switch of the first electronic switching device 40 is connected with a power supply end of the third processor 50;
a first control signal output terminal of the third processor 50 is connected to a control terminal of the second electronic switching device 60;
the standby power consumption of the first processor 20 is lower than that of the second processor 30.
When the device where the standby wake-up circuit is located normally works, the first processor 20 outputs a control signal to control the electronic switch of the first electronic switching device 40 to be switched on, so that the second processor 30 and the third processor 50 are powered to work, the second processor 30 controls the corresponding peripheral to normally work, and the third processor 50 controls the switch of the second electronic switching device 60 to be switched on to control the corresponding peripheral to normally work.
When the device is powered off, the signal trigger device 10 outputs a standby signal to the first processor 20 and the second processor 30 at the same time, where the first processor 20 is a low-power processor with a simpler function, the second processor 30 has a complex function such as an ARM processor with a larger standby power consumption, the third processor 50 may have the same standby power consumption as the first processor 20, and the second processor 30 executes a power-off action after receiving the standby signal, such as turning off a corresponding peripheral load, taking a device where the standby wake-up circuit is located as a projector, turning off HDMI output and AV output, and turning off peripherals such as WIFI and bluetooth; meanwhile, the second processor 30 sends a first control signal to the third processor 50 through the second control signal output end, so that the third processor 50 controls the second electronic switch device 60, which is handed over to the third processor, to be turned off according to the first control signal, so as to control the corresponding peripheral devices such as fans or turn off power supply to other control circuits; after the second processor 30 determines that the corresponding peripheral has been controlled to be turned off and the third processor 50 also controls the corresponding peripheral to be turned off, a second control signal is sent to the first processor 20 through the first control signal output terminal to control the first electronic switch to be turned off, so as to simultaneously turn off the power supply to the second processor 30 and the third processor 50, and also simultaneously turn off the power supply to the second electronic switch, so that only the first processor 20 of the entire device is in the working state, after the first processor 20 controls the electronic switch to control the power failure to the second processor 30, the third processor 50 and the second electronic switch device 60, the device can enter into the sleep low power consumption mode, because the standby power consumption of the first processor 20 is extremely low and is lower than that of the second processor 30, for example, the working current is in the milliampere level or even in the microampere level, so as to ensure that the entire device is in the extremely low power consumption state, for example, lower than 0.1W, therefore, the standby power requirement of low power consumption is met, energy is saved, and the related low-power-consumption energy standard is met.
In some embodiments of the present invention, as shown in fig. 2, the first electronic switching device 40 includes a second NMOS transistor Q2, a first PMOS transistor Q1, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7;
one end of the seventh resistor R7 is a control end of the first electronic switching device 40, the other end of the seventh resistor R7 is connected to the gate of the second NMOS transistor Q2, the source of the second NMOS transistor Q2 is grounded, and the drain of the second NMOS transistor Q2 is commonly connected to one end of the fifth resistor R5 and one end of the sixth resistor R6;
the other end of the fifth resistor R5 and the drain of the first PMOS transistor Q1 are commonly connected to the input terminal of the first electronic switching device 40, the source of the first PMOS transistor Q1 is the output terminal of the first electronic switching device 40, and the gate of the first PMOS transistor Q1 is connected to the other end of the sixth resistor R6.
Here, the first PMOS transistor Q1 and the second NMOS transistor Q2 constitute a basic switching circuit of the first electronic switching device 40, and when the second NMOS transistor Q2 is turned on, a voltage is applied between the drain and the gate of the first PMOS transistor Q1, so as to turn on, thereby turning on the electronic switching device 40.
Further, the first electronic switch device 40 further includes a sixth capacitor C6, and the sixth capacitor C6 is connected in parallel to the gate and the drain of the first PMOS transistor Q1. As shown in fig. 2, the sixth capacitor C6 functions to filter noise interference signals, and prevents the interference signals from loading between the gate and the drain of the first PMOS transistor Q1 to cause the mis-conduction of the first PMOS transistor Q1, thereby improving the stability of the operation thereof.
In some embodiments of the present invention, the signal triggering device 10 is an infrared receiving device or a key device. I.e. the triggering signals that the first processor 20 and the second processor 30 can receive are infrared signals or key signals.
Taking the trigger signal device as an infrared receiving device as an example, as shown in fig. 2, the infrared receiving device includes an infrared receiving head IR, a first electrostatic diode D1, a second electrostatic diode D2, a third diode D3 and a fourth diode D4;
the output end of the infrared receiving head IR is commonly connected with the cathode of the third diode D3 and the cathode of the fourth diode D4, and the positive power supply end of the infrared receiving head IR and the output end of the infrared receiving head IR are connected in parallel with the first electrostatic diode D1 and the second electrostatic diode D2 in a ground mode respectively;
the anode of the third diode D3 and the anode of the fourth diode D4 are two output terminals of the infrared receiving device, respectively.
The circuit diagram of the second electronic switching device is the same as that of the first electronic switching device, and is not described herein again.
The operation of the standby wake-up circuit is described below with reference to fig. 2.
When the remote controller sends a standby signal, the remote control receiving head receives the signal and simultaneously sends the signal to the first processor 20 and the second processor 30 through the third diode D3 and the fourth diode D4, wherein the third diode D3 and the fourth diode D4 play a role in isolation, and the port damage caused by short circuit caused by high and low levels between the receiving ports of the first processor 20 and the second processor 30 is avoided; the first electrostatic diode D1 and the second electrostatic diode D2 respectively function to filter the interference signals at the output terminal of the infrared receiver IR and the positive terminal of the power supply. The first processor 20 and the second processor 30 simultaneously analyze the remote control signal and recognize the remote control signal as a standby instruction, and the second processor 30 sends a shutdown instruction to control the relevant peripheral where the device is located to be turned off, for example, taking the device as a projector, to turn off HDMI output and AV output, and turn off WIFI, bluetooth and display lamp peripherals; the second processor 30 also sends a first control signal to the third processor 50 at the same time, the third processor 50 outputs a low level according to the first control signal to control the fourth NMOS transistor Q4 to turn off, when the fourth NMOS transistor Q4, the voltage loaded between the gate and the drain of the third PMOS transistor Q3 disappears, so that the corresponding peripheral controlled by the voltage output from the source of the third PMOS transistor Q3, such as a fan or other control circuit, is powered off along with the turn off; after the second processor 30 confirms that the peripherals are turned off, a second control signal is sent to the first processor 20, where the first processor 20 and the second processor 30 can transmit the control signal based on communication, or based on level if the control signal is simple. When the first processor 20 confirms that the standby instruction is received and receives the second control signal, the first processor outputs a low level to the gate of the second NMOS transistor Q2, so that the second NMOS transistor Q2 is turned off, and when the second NMOS transistor Q2 is turned off, the voltage applied between the gate and the drain of the first PMOS transistor Q1 disappears, so that with the turning off, the power supply to the second processor 30 and the third processor 50 is cut off, and the power supply to the fourth NMOS transistor Q4 and the third PMOS transistor Q3 is simultaneously cut off, so that only the first processor 20 of the whole device maintains the power supply, and the power supply to other processors and peripheral devices is cut off, because the second electronic switching device 60 composed of the third PMOS transistor Q3 and the fourth NMOS transistor Q4 has certain power consumption, so that the power supply to the second electronic switching device is cut off, and the standby power consumption of the device can be further reduced. And the first processor 20 enters a low power consumption state of sleep, thereby ensuring that the entire device is in a very low power consumption state.
When the remote controller sends a power-on signal, the first processor 20 receives and is awakened from the low-power-consumption sleep mode, and resolves the power-on command into a power-on command, so as to output a high-level signal to the gate of the second NMOS transistor Q2 to enable the second NMOS transistor Q2 to be conducted, and further, a voltage is loaded between the gate and the drain of the first PMOS transistor Q1 to enable the first NMOS transistor Q3526 to be conducted, so that the second processor 30 supplies power, the second processor 30 works after being powered on, executes related actions of power-on, and sends a third control signal to the third processor 50, so that the third processor outputs a high level to enable the fourth NMOS transistor Q4 to be conducted, and further enables the third PMOS transistor Q3 to be conducted, so that corresponding peripherals such as a fan and other control circuits are powered on to work, and accordingly, the power-.
In some embodiments of the present invention, as shown in fig. 3, the first electronic switching device 40 includes a second NPN triode Q2, a first PMOS transistor Q1, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7;
one end of the seventh resistor R7 is a control end of the first electronic switching device 40, the other end of the seventh resistor R7 is connected to the base of the second NPN triode Q2, the emitter of the second NPN triode Q2 is grounded, and the collector of the second NPN triode Q2 is commonly connected to one end of the fifth resistor R5 and one end of the sixth resistor R6;
the other end of the fifth resistor R5 and the drain of the first PMOS transistor Q1 are input terminals of the first electronic switching device 40, the source of the first PMOS transistor Q1 is an output terminal of the first electronic switching device 40, and the gate of the first PMOS transistor Q1 is connected to the other end of the sixth resistor R6.
The difference from the previous embodiment is that the second NPN transistor Q2 is used instead of the second NMOS transistor Q2, and the second NPN transistor Q3578 is turned on when the base of the second NPN transistor Q2 inputs a high level, so that the gate and the drain of the first PMOS transistor Q1 are loaded with a voltage and are also turned on. Therefore, the second NMOS transistor Q2 has the same function of driving the first PMOS transistor Q1 to work.
Other electronic switching devices such as the fourth NMOS transistor of the second electronic switching device 60 may also be replaced by a fourth NPN transistor Q4 to achieve the same function.
In some embodiments of the present invention, as shown in fig. 1, the standby wake-up circuit further comprises a third electronic switching device 70,
a second control signal output terminal of the third processor 50 is connected to a control terminal of the third electronic switching device 70;
and/or further comprises a fourth electronic switching device 80,
a third control signal output of the third processor 50 is connected to a control terminal of the fourth electronic switching device 80.
In order to meet the requirement that the device has more other control loads or peripherals, one or more electronic switch devices such as the rising third electronic switch device 70 and the fourth electronic switch device 80 are added on the basis of the second electronic switch 60 and are controlled by the third processor 50, so that the third processor 50 controls the on/off of the electronic switch devices to control the operation of more peripherals or control circuits in the device.
The specific circuit of the third electronic switching device 70 and the fourth electronic switching device 80 is shown in fig. 2 and 3, and the circuit may be the same as the first electronic switching device 40.
The utility model discloses an in some embodiments, the standby awakening circuit still includes voltage conversion equipment, and voltage conversion equipment supplies power for first treater 20 after stepping down to the input point voltage. As shown in fig. 4, since the power supply voltage of the first processor 20 is different from the power supply voltage, for example, the power supply voltage of the first processor 20 is 3.3V, and the power supply voltage is 5V, a voltage conversion circuit, mainly composed of the power management chip IC2, needs to be added to supply power to the first processor 20. Since the first processor 20 is powered at any time, the voltage conversion circuit needs to be separately provided.
The utility model discloses still provide a smart machine, set up the standby awakening circuit who mentions according to above-mentioned embodiment on this smart machine's the control circuit board. These smart devices may be one of a television box, a television set, a projector. By arranging the standby wake-up circuit, the intelligent devices realize extremely low power consumption such as less than 0.1W when in standby, so that the low power consumption requirement is met, and energy is saved.
The utility model discloses still provide a power management's control method, this control method is based on the standby wake-up circuit that above-mentioned embodiment mentioned. As shown in fig. 5, the control method includes:
step S100, acquiring and identifying a standby signal in a trigger signal output by a signal trigger device;
step S200, the second processor executes a shutdown action according to the standby signal and sends a first control signal to the third processor, so that the third processor controls the electronic switch equipment connected with the third processor to be disconnected according to the first control signal;
step S300, the second processor sends a second control signal to the first processor
In step S400, the first processor controls the first electronic switch device to turn off according to the standby signal and the second control signal, so as to turn off the power supply to the second processor and the third processor.
In step S100, taking the trigger signal as an infrared remote control signal as an example, the trigger signal is received and decoded to identify the trigger signal as a standby instruction.
In step S200, the second processor 30 executes a shutdown action according to the standby signal, taking the device where the standby wake-up circuit is located as an example of a projector, and at this time, the projector is controlled to close the HDMI output and the AV output, and close the WIFI, the bluetooth and the display lamp peripherals, wherein some peripherals such as the WIFI and the bluetooth need the second processor 30 to communicate with the related control chips to confirm that the projector is closed, so that a short time such as 1-5 seconds is provided, and a bulb of the projector for display is affected by a large working heat value and cannot be closed immediately, and the corresponding heat dissipation device such as a fan needs to be operated for a period of time such as 15 seconds-1 minutes to be closed, otherwise, the bulb is easily caused to have an excessively high temperature to affect the life of the bulb, so that the high temperature affects the life of other electronic components. And the second processor 30 further sends a first control signal to the third processor 50, so that the third processor 50 controls the correspondingly connected electronic switching device, such as the second electronic switching device 60, and/or simultaneously controls the third electronic switching device 70 and the fourth electronic switching device 80 to be turned off to cut off the power supply of other peripheral devices, such as the fan and other control circuits.
In step S300, after the second processor 30 confirms that all the peripherals are turned off, a second control signal is sent to the first processor 20 to inform the first processor 20 that the peripherals of the device are turned off.
In step S400, the first processor 20, after decoding the standby instruction and receiving the control signal, confirms that the self-shutdown operation is possible, and then outputs the control signal to control the electronic switching device 40 to turn off, so as to turn off the power supply to the second processor 30 and the third processor 50, and the second electronic switching device 60 and/or the third electronic switching device 70, and the fourth electronic switching device 80, and thus turn off the power supply to all the power consuming devices except the first processor 20. And the first processor 20 enters the sleep mode with low power consumption again, since the standby power consumption of the first processor 20 is very low and lower than that of the second processor 30, the whole projector is ensured to be in a very low power consumption state when in standby, such as lower than 0.1W. Therefore, the requirement of low power consumption is met, and electric energy is saved.
In some embodiments of the present invention, before the second processor sends the second control signal to the first processor, the control method further comprises:
the second processor receives a feedback signal of the third processor to confirm that an electronic switching device connected with the third processor is completely closed.
Since some peripherals controlled by the third processor 50 may not be immediately turned off, for example, a fan in a projector needs to be turned off in a delayed manner, the third processor needs to control the relevant peripherals to be turned off in a delayed manner after receiving the first control signal, at this time, the second processor 30 and the third processor 50 may be connected based on a communication manner, and the third processor 50 feeds back an acknowledgement signal to the second processor 30 after controlling the relevant peripherals to be turned off in a delayed manner, so that the second processor 30 confirms that the third processor 50 has all the peripherals connected correspondingly through the electronic switch device. The second processor then sends a second control signal to the first processor 20 to perform the final power-down action.
In some embodiments of the present invention, as shown in fig. 6, the control method further includes:
step S400, acquiring and identifying a starting signal in a trigger signal output by a signal trigger device;
step S500, the first processor controls the first electronic switch device to be conducted according to the starting signal so as to supply power to the second processor and the third processor;
in step S600, the second processor executes a power-on and power-on operation and sends a third control signal to the third processor, so that the third processor controls the electronic switch device connected thereto to be turned on.
In step S400, still taking the projector as an example, when receiving the power-on signal sent by the remote controller, only the first processor 20 is in the low power consumption state of power supply, and is awakened by the infrared remote control signal to exit the low power consumption state of the sleep mode, and decodes and recognizes the power-on command.
In step S500, the first processor 20 controls the first electronic switching device 40 to be turned on according to the power-on command, so as to supply power to the second processor 30 and the third processor 50, and other electronic switching devices, such as the second electronic switching device 60.
In step S600, the second processor 30 executes related power-on actions, such as turning on a bulb of the display, turning on an output port, such as an HDMI port, and the like, after obtaining the power-on action. Meanwhile, the second processor 30 sends a third control signal to the third processor 50, so that the third processor 50 controls the corresponding electronic switching device, such as the second electronic switching device 60, to be turned on, or further controls other electronic switching devices, such as the third electronic switching device 70 and the fourth electronic switching device 80, to be turned on, so as to supply power to other peripherals, such as a fan or other control circuits, to control the operation of the peripherals, thereby completing the power-on operation.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship indicated based on the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the present application, unless expressly stated or limited otherwise, the first feature may be directly on or directly under the second feature or indirectly via intermediate members. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the scope of the present invention.
Claims (10)
1. A standby wake-up circuit, comprising a signal triggering device, a first processor, a second processor, a third processor, a first electronic switching device and a second electronic switching device;
wherein the output end of the signal trigger device is simultaneously connected with the first processor and the second processor;
a first control signal output end of the second processor is connected with the first processor, and a second control signal output end of the second processor is connected with the third processor;
the control signal output end of the first processor is connected with the control end of the first electronic switch device, the input end of a switch of the first electronic switch device is connected with a power supply, and the output end of the switch of the first electronic switch device is connected with the power supply end of the third processor;
a first control signal output end of the third processor is connected with a control end of the second electronic switch device;
the standby power consumption of the first processor is lower than the standby power consumption of the second processor.
2. The standby wake-up circuit according to claim 1, wherein the first electronic switching device comprises a second NMOS transistor, a first PMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor;
one end of the seventh resistor is a control end of the electronic switching device, the other end of the seventh resistor is connected with a grid electrode of the second NMOS tube, a source electrode of the second NMOS tube is grounded, and a drain electrode of the second NMOS tube is connected to one end of the fifth resistor and one end of the sixth resistor in common;
the other end of the fifth resistor and the drain electrode of the first PMOS tube are connected to the input end of the electronic switching device in a shared mode, the source electrode of the first PMOS tube is the output end of the electronic switching device, and the grid electrode of the first PMOS tube is connected to the other end of the sixth resistor.
3. The standby wake-up circuit according to claim 1, wherein the first electronic switching device comprises a second NPN triode, a first PMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor;
one end of the seventh resistor is a control end of the electronic switching device, the other end of the seventh resistor is connected with a base electrode of the second NPN triode, an emitter electrode of the second NPN triode is grounded, and a collector electrode of the second NPN triode is commonly connected to one end of the fifth resistor and one end of the sixth resistor;
the other end of the fifth resistor and the drain electrode of the first PMOS tube are connected to the input end of the electronic switching device in a shared mode, the source electrode of the first PMOS tube is the output end of the electronic switching device, and the grid electrode of the first PMOS tube is connected to the other end of the sixth resistor.
4. The standby wake-up circuit according to claim 2 or claim 3, further comprising a sixth capacitor connected in parallel to the gate and the drain of the first PMOS transistor.
5. The standby wake-up circuit according to claim 1, further comprising a third electronic switching device,
a second control signal output end of the third processor is connected with a control end of the third electronic switch device;
and/or further comprising a fourth electronic switching device,
and a third control signal output end of the third processor is connected with a control end of the fourth electronic switching device.
6. The standby wake-up circuit of claim 1, further comprising a voltage conversion device for stepping down an input voltage to power the first processor.
7. The standby wake-up circuit according to claim 1, wherein the signal triggering device is an infrared receiving device or a key device.
8. The standby wake-up circuit according to claim 7, wherein the infrared receiving device comprises an infrared receiving head, a third diode and a fourth diode;
the output end of the infrared receiving head is commonly connected with the cathode of the third diode and the cathode of the fourth diode;
and the anode of the third diode and the anode of the fourth diode are two output ends of the infrared receiving equipment respectively.
9. The standby wake-up circuit according to claim 8, wherein the infrared receiving device further comprises a first electrostatic diode, a second electrostatic diode;
and the positive power supply end of the infrared receiving head and the output end of the infrared receiving head are connected in parallel with the first electrostatic diode and the second electrostatic diode respectively in a ground connection mode.
10. An intelligent device, wherein the standby wake-up circuit according to any one of claims 1 to 9 is disposed on a control circuit board of the intelligent device, and the intelligent device is one of a television box, a television set, and a projector.
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| CN202022139315.8U CN213338366U (en) | 2020-09-25 | 2020-09-25 | Standby wake-up circuit and intelligent device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112255940A (en) * | 2020-09-25 | 2021-01-22 | 深圳市当智科技有限公司 | Control circuit, electrical equipment and control method in standby mode |
| CN115549669A (en) * | 2022-12-01 | 2022-12-30 | 北京理工大学 | Low-power-consumption designed high-level wake-up circuit |
| CN117411162A (en) * | 2023-12-14 | 2024-01-16 | 天津云圣智能科技有限责任公司 | Unmanned aerial vehicle battery low-power consumption control device and system |
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2020
- 2020-09-25 CN CN202022139315.8U patent/CN213338366U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112255940A (en) * | 2020-09-25 | 2021-01-22 | 深圳市当智科技有限公司 | Control circuit, electrical equipment and control method in standby mode |
| CN115549669A (en) * | 2022-12-01 | 2022-12-30 | 北京理工大学 | Low-power-consumption designed high-level wake-up circuit |
| CN117411162A (en) * | 2023-12-14 | 2024-01-16 | 天津云圣智能科技有限责任公司 | Unmanned aerial vehicle battery low-power consumption control device and system |
| CN117411162B (en) * | 2023-12-14 | 2024-03-08 | 天津云圣智能科技有限责任公司 | Unmanned aerial vehicle battery low-power consumption control device and system |
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