CN213212163U

CN213212163U - SiC MOSFET device with protection structure

Info

Publication number: CN213212163U
Application number: CN202022073374.XU
Authority: CN
Inventors: 倪炜江
Original assignee: Wuhu Qiyuan Microelectronics Technology Partnership LP
Current assignee: Anhui Xinta Electronic Technology Co.,Ltd.
Priority date: 2020-09-21
Filing date: 2020-09-21
Publication date: 2021-05-14
Anticipated expiration: 2030-09-21

Abstract

The utility model relates to the technical field of semiconductors, especially, relate to a SiC MOSFET device with protective structure, the SiC MOSFET device includes terminal area and scribing groove area, p + main ring, bars runway and source runway on the p + main ring, active area and the briquetting metal of source and bars on the active area that are parallelly connected by a plurality of primitive cell structures from the edge to the center in proper order; two Schottky diode structures which are connected in series in an opposite direction are integrated between the gate track and the source track and are used as protection structures of devices. The utility model discloses an integrated temperature protection architecture on the chip can trigger protection architecture when the junction temperature of device surpasss the uniform temperature, reduces the grid source voltage of short circuit device even, turn-offs the device to device and circuit have been protected.

Description

SiC MOSFET device with protection structure

Technical Field

The utility model belongs to the technical field of the semiconductor technology and specifically relates to a SiC MOSFET device with protection architecture is related to.

Background

The wide bandgap semiconductor material SiC has a bandgap width of about 3 times, a critical breakdown electric field strength of 10 times, and a thermal conductivity of 3 times as compared with Si. Therefore, compared with a Si device, the SiC device has the advantages of higher voltage resistance, higher working frequency, higher high temperature resistance and the like. Both theory and practice have demonstrated that SiC MOSFETs have switching frequencies above 10 and better switching efficiency than Si-based IGBTs, and therefore SiC devices will have a very large field of application and market.

Although the theoretical maximum junction temperature of a general SiC device can reach above 600 ℃, in a SiC MOSFET, the maximum junction temperature is limited due to the presence of a MOS gate structure. As the junction temperature increases, the threshold voltage of the gate decreases while the current tunneling through the gate dielectric increases, resulting in a sharp decrease in the lifetime of the gate. Therefore, the requirement that the device operate below the highest junction temperature is very important for long term reliability and lifetime of the device. Generally, specifications for semiconductor devices strictly specify the maximum junction temperature at which the device operates. In the practical application of the device, the device can be operated at the highest temperature lower than the specified temperature, so that the stable and reliable operation of the device and a system is ensured. However, in some cases, such as when a short-circuit fault occurs in a circuit, the MOSFET is subjected to high voltage and short-circuit current, the power consumption is very large, the temperature rise is very fast, the junction temperature is easily caused to exceed the highest junction temperature and even exceed the melting point of a metal or a semiconductor material, and the device and the circuit are damaged. Therefore, limiting the junction temperature of the device below damaging temperatures (e.g., the melting point of a metal or semiconductor material) and limiting the time that the junction temperature exceeds a specified maximum junction temperature is important for the lifetime and safe use of the device.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a SiC MOSFET device with protection architecture, through integrated temperature protection architecture on the chip, can trigger protection architecture when the junction temperature of device surpasss the uniform temperature, reduce the grid source voltage of short-circuit device even, turn-off device to device and circuit have been protected.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the utility model provides a SiC MOSFET device with a protection structure, which comprises a terminal area, a scribing groove area, a p + main ring, a grid runway and a source runway on the p + main ring, an active area formed by connecting a plurality of primitive cell structures in parallel, and briquetting metal of a source and a grid on the active area from the edge to the center in sequence; two Schottky diode structures which are connected in series in an opposite direction are integrated between the gate track and the source track and are used as protection structures of devices.

As a further technical scheme, the protection structure sequentially comprises a drain electrode, an n + substrate, an n + type buffer layer, an n type drift region, a p + region, an n region, a field oxide layer, polycrystalline silicon, an interlayer dielectric, ohmic contact metal, schottky contact metal, gate track metal, source track metal and a passivation layer from bottom to top.

As a further technical scheme, the active region sequentially comprises a drain electrode, an n + substrate, an n + buffer layer, an n-type drift region, an n-type JFET region, a p-well, a p + region, an n + region, a gate dielectric, a polysilicon gate, an interlayer dielectric, a source ohmic contact and a source press metal from bottom to top.

As a further aspect, the electrodes of the source runner are in electrical communication with the source of the active region, and the electrodes of the gate runner are in electrical communication with the gate of the active region.

As a further technical solution, the polysilicon is formed simultaneously with the polysilicon gate of the active region and connected by a polysilicon bridge.

As a further technical scheme, the gate runway and the source runway are isolated by a passivation layer.

As a further aspect, the source racetrack is in electrical communication with the p + region.

As a further technical solution, the schottky metal of the schottky diode structure is Ti, Ni, Mo or polysilicon.

As a further technical scheme, the primitive cell structure is hexagonal, strip-shaped or rectangular.

Adopt above-mentioned technical scheme, the utility model discloses following beneficial effect has:

the utility model discloses an integrated temperature protection architecture on the chip can trigger protection architecture when the junction temperature of device surpasss the uniform temperature, reduces the grid source voltage of short circuit device even, turn-offs the device to device and circuit have been protected.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a top view of a SiC MOSFET device with a protection structure according to an embodiment of the present invention;

FIG. 2 is a schematic view of the cross-sectional structure of FIG. 1 taken along the line A-A';

fig. 3 is a schematic circuit diagram of a SiC MOSFET device with a protection structure according to an embodiment of the present invention;

icon: 01-terminal region and scribe line region, 02-p + main ring, 03-gate track, 04-source track, 05-primitive cell structure, 06-source compact metal, 07-gate compact metal, 1-drain, 2-n + substrate, 3-n + buffer layer, 4-n drift region, 5-p + region, 6-n region, 7-field oxide layer, 8-polysilicon, 9-interlayer dielectric, 10-ohmic contact metal, 11-schottky contact metal, 12-gate track metal, 13-source track metal, 14-passivation layer, 111-schottky junction, 112-schottky junction, 21-n type JFET region, 22-p well, 23-p + region, 24-n + region, 25-gate dielectric, 26-polysilicon gate, 27-interlayer dielectric, 28-source ohmic contact, 29-source compact metal.

Detailed Description

The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings. It is to be understood that the description of the embodiments herein is for purposes of illustration and explanation only and is not intended to limit the invention.

The n-type doping and the p-type doping mentioned in the embodiments of the present invention are relative, and may also be referred to as the first doping and the second doping, i.e., the interchanging of the n-type and the p-type is also applicable to the device. In the embodiment of the present invention, the structure of the MOSFET device takes SiC as an example.

Referring to fig. 1, the present embodiment provides a SiC MOSFET device with a protection structure, where the SiC MOSFET device sequentially includes, from an edge to a center, a scribe lane region and a termination region 01, a p + main ring 02, a gate runner 03 and a source runner 04 on the p + main ring 02, an active region formed by connecting a plurality of primitive cell structures 05 in parallel, and a source bulk metal 06 and a gate bulk metal 07 on the active region; two Schottky diode structures which are connected in series in an opposite direction are integrated between the gate track 03 and the source track 04 and serve as protection structures of devices. The active region is composed of a series of regularly arranged cells (cells), each of which is a small MOSFET functional unit. Because the two Schottky diodes are connected in series in an inverted mode, the gate source and the source gate are not conducted, and both have certain breakdown voltage. The circuit diagram of the chip is shown in fig. 3.

As shown in fig. 2, in this embodiment, as a further technical solution, the protection structure sequentially includes, from bottom to top, a drain 1, an n + substrate 2, an n + buffer layer 3, an n type drift region 4, a p + region 5, an n region 6, a field oxide layer 7, polysilicon 8, an interlayer dielectric 9, an ohmic contact metal 10, a schottky contact metal 11, a gate track metal 12, a source track metal 13, and a passivation layer 14. The width of the n region 6 is greater than a certain value, typically greater than 0.5 microns in SiC, and is required to withstand the maximum allowed gate voltage. The ohmic contact in the integrated schottky diode is completed with the ohmic contact in the active region. The p + region 5 and the n region 6 are completed by multiple times of ion implantation. For N-type doping, N or P ions are implanted. For p-type doping, Al ion implantation is used.

In this embodiment, as a further technical solution, the active region sequentially includes, from bottom to top, a drain 1, an n + substrate 2, an n + buffer layer 3, an n-type drift region 4, an n-type JFET region 21, a p well 22, a p + region 23, an n + region 24, a gate dielectric 25, a polysilicon gate 26, an interlayer dielectric 27, a source ohmic contact 28, and a source briquetting metal 29. The drain electrode 1 consists of a drain electrode ohmic contact and drain electrode briquetting metal, wherein the briquetting metal is TiNiAg and the like, and the thickness is more than 1 micron. The n + type buffer layer 3 has a doping concentration less than that of the n + substrate, and is typically 1E18cm^-3And the thickness is between 0.5 and 5 microns. The doping concentration and thickness of the n-type drift region 4 are determined according to the designed breakdown voltage of the device, for example, for a 1200V device, the concentration can be 5E15-2E16cm^-3And a thickness of between 8-12 microns. The width of the n-type JFET region 21 is determined by the breakdown voltage of the device and the turn-off lower gate dielectricThe maximum electric field and the on-resistance. The doping concentration is greater than that of the n-type drift region 4, which is beneficial to reducing the on-resistance. p-well 22 bulk doping concentration greater than 1E18cm^-3The surface channel region is 1E15-2E17cm^-3Depending on the threshold voltage. Bulk doping of p + region 23 greater than 1E18cm^-3Surface concentration greater than 1E19cm^-3And low-resistance ohmic contact is formed. Doping of n + region 24 is greater than 1E19cm^-3. The gate dielectric 25 is typically a thermally oxidized grown SiO₂The thickness is between 20nm and 100nm according to the design of threshold voltage. The polysilicon gate 26 is heavily doped low resistivity polysilicon and the interlayer dielectric 27(ILD) is SiO₂Or SiN, typically greater than 0.5 microns thick. The source ohmic contact 28 is formed by RTA rapid annealing after Ni deposition and the source block metal 29 may be TiAl, or TiNiAg, or TiAu, etc., with a thickness greater than 3 microns.

In this embodiment, as a further technical solution, the electrode of the source track 04 is electrically communicated with the source of the active region, and the electrode of the gate track 03 is electrically communicated with the gate of the active region.

In this embodiment, as a further technical solution, the polysilicon 8 is formed simultaneously with the polysilicon gate 26 of the active region and connected by a polysilicon bridge.

In this embodiment, as a further technical solution, the gate track 03 and the source track 04 are separated by a passivation layer, and the distance is set to satisfy the condition that the breakdown voltage is greater than the maximum allowable gate-source voltage.

In this embodiment, as a further solution, there are both metal 11 in schottky contact with n region 6 and metal 10 in ohmic contact with p + region 5 in source track 04. Thus, the source racetrack is also in electrical communication with p + region 5. The ohmic contact 10 may be completed together with the ohmic contact in the active region.

In this embodiment, as a further technical solution, the schottky metal of the schottky diode structure is Ti, Ni, Mo or polysilicon. The size of the schottky metal and the barrier needs to be determined according to the gate leakage limit and the maximum temperature limit of the device. The Schottky barrier is small, the reverse bias leakage current is large, and the gate-source short circuit can be caused earlier to turn off the device. Since the fermi level of polysilicon is related to the doping concentration, the barrier height between polysilicon and SiC is related to the doping concentration of polysilicon, and can be adjusted by adjusting the doping concentration of polysilicon here.

As a further technical solution, the cell structure is hexagonal, bar-shaped or rectangular, in this embodiment, the cell structure is hexagonal.

The gate runner metal 12, the source runner metal 13 and the active area source metal are the same and can be done simultaneously.

The working principle of the utility model is as follows:

when the gate-source voltage is positive and the gate-source voltage is on, the Schottky junction 111 is forward biased, the Schottky junction 112 is reverse biased, and the gate and the source are not conducted. Or when the grid source voltage is negative voltage and is switched off, the Schottky junction 111 is reversely biased, the Schottky junction 112 is forwardly biased, and the grid source is not conducted. Thus, the integrated protection structure does not affect the normal operation of the device.

When the device is short-circuited, the voltage and current on the device are very large, which causes large power consumption, resulting in rapid rise of junction temperature. When the junction temperature rises to a certain temperature, the reverse leakage current of the integrated Schottky diode is increased sharply, the gate source is close to short circuit, and the device is turned off immediately. Therefore, the integrated two Schottky diode structures which are connected in series in the reverse direction can cause grid-source short circuit when the junction temperature of the device reaches a certain value, and the device is turned off, so that the device is effectively protected finally.

When the gate voltage is larger than the threshold voltage and the device is in a conducting state, the Schottky junction 111 is forward biased, the Schottky junction 112 is reverse biased, and the current and voltage relationship of the reverse biased Schottky diode is as the formula:

A^**is the function of the richard constant,

is the metal-semiconductor contact barrier, n is the contact ideality factor, and T is the temperature. Under a certain reverse bias voltage V, the relationship between the reverse leakage current and the temperature can be further simplified as follows:

the reverse leakage current increases exponentially with temperature. Therefore, when a certain temperature is reached, reverse leakage current is very large, short circuit occurs between the grid sources, the voltage between the grid sources tends to zero volt, and the device is turned off.

The utility model provides a protection architecture can be applied to on the multiple SiC transistor chip, like planar MOSFET, ditch slot type MOSFET, integrated Schottky diode's MOSFET, integrated current sensor's MOSFET, SiC IGBT, SiC JFET etc. principle and method are unanimous. The method of the present invention can also be used for transistor devices of other materials, such as GaN, Ga₂O₃And various semiconductor material devices such as GaAs and Si.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A SiC MOSFET device with a protection structure comprises a terminal region, a scribing groove region, a p + main ring, a gate runway and a source runway on the p + main ring, an active region formed by connecting a plurality of cell structures in parallel, and briquetting metal of a source and a gate on the active region in sequence from the edge to the center; the Schottky diode structure is characterized in that two Schottky diode structures which are connected in series in an opposite direction are integrated between the gate track and the source track and are used as a protection structure of a device.

2. The SiC MOSFET device of claim 1, wherein the protection structure comprises, in order from bottom to top, a drain, an n + substrate, an n + buffer layer, an n-drift region, a p + region, an n region, a field oxide layer, polysilicon, an interlayer dielectric, an ohmic contact metal, a schottky contact metal, a gate runner metal, a source runner metal, and a passivation layer.

3. The SiC MOSFET device with the protection structure of claim 1, wherein the active region comprises a drain electrode, an n + substrate, an n + type buffer layer, an n type drift region, an n type JFET region, a p well, a p + region, an n + region, a gate dielectric, a polysilicon gate, an interlayer dielectric, a source ohmic contact and a source blocking metal in sequence from bottom to top.

4. The SiC MOSFET device of claim 1, wherein the electrodes of the source runner are in electrical communication with the source of the active region and the electrodes of the gate runner are in electrical communication with the gate of the active region.

5. The SiC MOSFET device with the protection structure of claim 2, wherein the polysilicon is formed simultaneously with the polysilicon gate of the active region and connected by a polysilicon bridge.

6. The SiC MOSFET device of claim 1, wherein the gate runner and the source runner are separated by a passivation layer.

7. The SiC MOSFET device with protection structure of claim 2, wherein the source runner is in electrical communication with the p + region.

8. The SiC MOSFET device with the protection structure of claim 1, wherein the schottky metal of the schottky diode structure is Ti, Ni, Mo or polysilicon.

9. The SiC MOSFET device with the protection structure of claim 1, wherein the cell structure is hexagonal, bar-shaped, or rectangular.